OKI ML67Q4002TC User Manual

ML674K Series

ML674001/ML67Q4002/ML67Q4003

32-Bit ARM

®

-Based General Purpose Microcontrollers

Description

Oki Semiconductor’s ML674001, ML67Q4002, and
ML67Q4003 microcontrollers (MCUs) have been added to an
extensive and growing family of ARM
for standard products that require 32-bit CPU performance
and the low cost afforded by MCU integrated features.

Oki’s new Family members provide on-board SRAM (32
KBytes), boot ROM (4 KBytes) and a host of other useful
peripherals such as seven general-purpose timers, a watch­dog timer, pulse-width modulators, AD converter, SIOs, I
serial interface, GPIO pins, external-memory controller, and
boundary-scan capability. In addition, the ML67Q4002 and
ML67Q4003 offer 256 KBytes and 512 KBytes of built-in
Flash ROM, respectively. The ML674001, ML67Q4002, and
ML67Q4003 are pin-for-pin compatible with each other for
easy performance upgrades.

®

based 32-bit MCUs

2

C

Features

• ARM7TDMI 32-bit RISC CPU

- 16-bit Thumb™ instruction set for power efficiency
applications

• 32-bit mode (ARM) and/or 16-bit mode (Thumb)

• Built-in external memory controller supports glue­less connectivity to memory (including SDRAM and
EDO DRAM) and I/O

• Built in Flash ROM

- 256 KB (ML67Q4002)

- 512 KB (ML67Q4003)

• 32-KBytes built in zero-wait-state SRAM

• 28 interrupt sources

The ARM7TDMI

Oki Semiconductor’s Family of low-cost ARM-based MCUs
offers system designers a bridge from 8- and 16-bit propri­etary MCU architectures to ARM’s 32-bit industry standard
architecture with no price premium. The ARM industry-wide
support infrastructure offers system developers many advan­tages including software compatibility, many ready-to-use
software applications, and a large choice among hardware
and software development tools to better leverage engineer­ing resources, lower development costs, minimize project
risks, and reduce their product time to market.

In addition, migration of a design with an Oki standard MCU
to an Oki custom solution is easily facilitated with its award­winning µPLAT™ product development architecture.

• DMA: Two channels with external access

•Timers: Seven 16-bit timers

•Watch-Dog Timer: Dual-stage 16 bit

• PWM: Two 16-bit channels

• Serial Interfaces: SIO, UART, SSIO, I

• GPIO: 42 bits

• A/D Converter: Four 10-bit channels

• Built-in boot ROM accommodates in-circuit Flash
ROM re-programming and field-updates

•Packages

- 144-pin plastic LQFP

- 144-pin plastic LFBGA

®

Advantage

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C

April 2004, Rev 2.0

Data Sheet

Applications

• Flexible solution for various cost-effective, power­sensitive embedded real-time control applications

ML674001/Q4002/Q4003 MCUs

Part Number Clock Frequency Built-in Flash Size Packages

ML674001 33 MHz none 144-pin plastic LQFP (ML674001TC)

ML67Q4002 33 MHz 256 KB

(128K x 16 bits)

ML67Q4003 33 MHz 512 KB

(256K x 16 bits)

• Security / Surveillance, Telecom, Industrial Control,
Electronic Peripherals, and Consumers Electronics
embedded applications

144-pin plastic LFBGA (ML674001LA)
144-pin plastic LQFP (ML67Q4002TC)

144-pin plastic LFBGA (ML67Q4002LA)
144-pin plastic LQFP (ML67Q4003TC)

144-pin plastic LFBGA (ML67Q4003LA)

ML674001/ML67Q4002/ML67Q4003

Block Diagram

TDI

TDO

nTRST

TMS

TCK

RESET_N

PIOB[6] / STXD
PIOB[7] / SRXD

OSC0
OSC1_N
CKOE_N

CKO

PIOE[8:5] / EXINT[3:0]

PIOE[9] / EFIQ_N

VDD_CORE

VDD_IO

GND
AVDD
AGND

DRAME_N

TEST

BSEL[1:0]

FWR

JSEL

5

Internal RAM

32KB

µPLAT-7B

ARM7TDMI

AHB Bridge

APB Bridge

System

TIMER

5

Internal & External
Memory Controller

AMBA

AHB Bus

AMBA

APB Bus

SIO

TIC

IRC

System

Controller

CGB

DRAMC

Exp. IRC

ML67Q4002: 256KB
ML67Q4003: 512KB

Boot ROM

4KB

APB Bridge

APB Bus

Internal (MCP)

FLASH ROM

DMAC

TIMER

16 bit x 6ch

16 bit x 2ch

(16550)

PWM

GPIO

WDT

SSIO

I2C

A/D

UART

PIOC[6:2] / XA[23:19]
XA[18:0]
XD[15:0]
PIOC[7] / XWR
XOE_N
XWE_N
XBWE_N[1:0]
XROMCS_N
XRAMCS_N
XIOCS_N[3:0]
XBS_N[1:0]
PIOD[0] / XWAIT
PIOD[1] / XCAS_N
PIOD[2] / XRAS_N
PIOD[3] / XSDCLK
PIOD[4] / XSDCS_N
PIOD[5] / XSDCKE
PIOD[6] / XDQM[1] / XCAS_N[1]
PIOD[7] / XDQM[0] / XCAS_N[0]

PIOB[0] / DREQ[0]

2

PIOB[2] / DREQ[1]
PIOB[1] / DREQCLR[0]

2

PIOB[3] / DREQCLR[1]
PIOB[5:4] / TCOUT[1:0]

2

PIOC[1:0] / PWMOUT[1:0]

2

PIOA[7:0]

42

PIOB[7:0]
PIOC[7:0]
PIOD[7:0]
PIOE[9:0]

PIOE[0] / SDO

3

PIOE[1] / SDI
PIOE[2] / SCLK

PIOE[3] / SDA

2

PIOE[4] / SCL

AIN[3:0]

5

VREF

PIOA[0] / SIN

8

PIOA[1] / SOUT
PIOA[2] / CTS
PIOA[3] / DSR
PIOA[4] / DCD
PIOA[5] / DTR
PIOA[6] / RTS
PIOA[7] / RI

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April 2004, Rev 2.0

Functional Description

ML674001/ML67Q4002/ML67Q4003

CPU

CPU core: ARM7TDMI
Operating frequency: 1 MHz to 33 MHz (max)
Instructions: ARM instruction (32-bit length) and Thumb

instruction (16-bit length) can be mixed
General register bank: 31 x 32 bits
Built-in barrel shifter: ALU and barrel shift operations can be executed

by one instruction.
Multiplier: 32 bits x 8 bits (Modified Booth’s Algorithm)
Built-in debug function: JTAG interface, break point register
Byte Ordering: Little Endian

Built-in Memory

FLASH ROM: ML674001 is the ROM-less version

ML67Q4002: 256 KBytes (128K x 16 bits)
ML67Q4003: 512 KBytes (256K x 16 bits)
Access timing of this FLASH memory is configured by the

ROM bank control register of the external memory
controller.

SRAM: 32KB
(8K x 32 bits)

Read access (8/16/32 bit): 1 cycle
Write access (32 bit): 1 cycle
Write access (8/16 bit): 2 cycle

Interrupt Controller

Fast interrupt request (FIQ) and interrupt request (IRQ) are employed as inter­rupt input signals. The interrupt controller controls these interrupt signals
going to ARM core.

1. Interrupt sources

- FIQ: 1 external source (external pin: EFIQ_N)

- IRQ: Total of 27 sources. 23 internal sources, and 4 external sources
(EXINT[3:0])

2. Interrupt priority level

- Configurable, 8-level priority for each source

3. External interrupt pin input

- EXINT[3:0] Can be set as Level or Edge sensing

- Configurable High or Low when Level sensing. Configurable Rising- or
Falling-edge triggering when Edge sensing. EFIQ_N is set as Falling-Edge
triggering.

Timer

Seven channels of 16-bit reload timers are employed. Of these, 1 channel is
used as system timer for OS.

The timers of other 6 channels are used in application software.

1. System timer: 1 channel

- 16-bit auto reload timer: Used as system timer for OS. Interrupt request
by timer overflow.

2. Application timer: 6 channels

- 16-bit auto reload timer

-One shot, interval

- Clock can be independently set for each channel

Watch Dog Timer

Functions as an interval timer or a watch dog timer.

• 16-bit timer

•Watch dog timer or interval timer mode can be selected

• Interrupt reset generation

• Maximum period: longer than 200 msec

Serial Interface

This MCU contains four serial interfaces.

1. SIO without FIFO: 1 channel

This is the serial port which performs data transmission, taking a synchro­nization per character.
Selection of various parameters, such as addition of data length, a stop
bit, and a parity bit, is possible.

- Asynchronous full duplex operation

- Sampling Rate = Baud rate x 16 samples

- Character Length: 7, 8 bit

- Stop Bit Length: 1, 2 bit

-Parity: Even, Odd, none

- Error Detection: Parity, Framing, Over run

- Loop Back Function: ON/OFF, Parity, framing, Over run Compulsive
addition

- Built-in Baud Rate Generator (8-bit counter) - Independent from a bus
clock

- Internal-Baud-Rate-Clock-Stop at the Time of HALT Mode.

2. UART with 16-byte FIFO: 1 channel
Features 16-byte FIFO in both send and receive. Uses the industry stan-

dard 16550A ACE (Asynchronous Communication Element).

- Asynchronous full duplex operation

- Reporting function for all status

- 16-Byte Transmit FIFO

- 16-Byte Receive FIFO

-Transmission, reception, interrupt of line status Data set and Indepen-

dent FIFO control.

-Modem control signals: CTS, DCD, DSR, DTR, RI and RTS

- Data length: 5, 6, 7, or 8 bits

- Stop bit length: 1, 1.5, or 2 bits

- parity: Even, Odd, or none

- Error Detection: Parity, Framing, Overrun

- Built-in Baud Rate Generation

3. Synchronous serial interface: 1 channel
Clock-synchronous 8 bit serial port

- selectable 1/8, 1/16 or 1/32 of the system clock frequency.

- LSB First or MSB First.

-Master / Slave Mode

-Transceiver buffer empty interrupt

- Loopback Test Function

2

C: 1 channel

4. I
Based on the I

- Communication mode: Master transmitter /master receiver

-Transmission Speed: 100 kbps (Standard mode) / 400 kbps (Fast mode)

- Addressing format: 7-bit / 10-bit

- Data buffer: 1 Byte (1 step)

- Communication Voltage: 2.7 V to 3.3 V

2

C Bus specification. Operates as a single master device.

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Oki Semiconductor • 3

ML674001/ML67Q4002/ML67Q4003

Direct Memory Access Controller (DMAC)

Two-channel direct memory access controller (DMAC) which transfers data
between memory and memory, between I/O and memory, and between I/O
and I/O.

1. Number of
channels:

2. Channel priority
level:

3. Maximum number
of transfers:

4. Data transfer size: Byte (8 bits), Half-word (16 bits), Word (32 bits)

5. Bus request
system:

6. DMA transfer
request:

7. Interrupt request: Interrupt request is generated in CPU after the end

2 channels

Fixed mode: Channel priority level is always

fixed (channel 0 >1).

Roundrobin: Priority level of the channel

requested for transfer is kept
lowest.

65,536 per DMA operation.

Cycle steal
mode:

Burst mode: Bus request signal is asserted until

Software
request:

External
request:

of DMA transfer for the set number of transfer
cycles, or after the occurrence of an error.

Interrupt request signal is output separately for
each channel.

Interrupt request signal output can be masked for
each channel.

Bus request signal is asserted for
each DMA transfer cycle.

all transfers of transfer cycles are
complete.

By setting the software transfer
request bit inside the DMAC, the
CPU starts DMA transfer.

DMA transfer is started by exter­nal request allocated to each
channel.

External Memory Controller

Controls access of externally connected devices such as ROM (FLASH), SRAM,
SDRAM (EDO DRAM), I/O devices and external FLASH memory.

1. ROM (FLASH) access function: 1 bank (supports up to 16 MBytes)

Supports 16-bit devices
Supports FLASH memory: Byte write (can be written only by IF equivalent
to SRAM).
In ML67Q4002/4003, control internal FLASH access.
Configurable access timing.

2. SRAM access function : 1 bank

Supports 16-bit devices
Supports asynchronous SRAM
Configurable access timing.

3. DRAM access function : 1 bank

Supports 16-bit devices
Supports EDO-DRAM/SDRAM: Simultaneous connections to EDO-DRAM
and SDRAM cannot be made.
Configurable access timing.

4. External I/O access function: 2 banks

Supports 8-bit/16-bit access: Independent configuration for each bank.
Each bank has two chip selects: XIOCS_N[3:0].
Supports external wait input: XWAIT
Access timing configurable for bank independently.

GPIO

42-bit parallel port (four 8-bit ports and one 10-bit port).

PIOA[7:0]
PIOB[7:0]
PIOC[7:0]
PIOD[7:0]
PIOE[9:0]

1. Input/output selectable at bit level.

2. Each bit can be used as an interrupt source.

3. Interrupt mask and interrupt priority can be set for all bits.

4. The ports are configured as input, immediately after reset.

5. Primary/secondary function of each port can be set independently.

Combination port
Combination port
Combination port
Combination port
Combination port

UART
DMAC, SIO (µPLAT-7B)
PWM, XA[23:19], XWR
DRAM control signals etc.
SSIO, I2C, External interrupt signal

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April 2004, Rev 2.0

ML674001/ML67Q4002/ML67Q4003

Pulse Width Modulation

This MCU contains two channels of Pulse Width Modulation (PWM) function
which can change the duty cycle of a waveform with a constant period. The
PWM output resolution is 16 bits for each channel.

A/D Converter

Successive approximation type A/D converter.

1. 10 bits x 4 channels

2. Sample and hold function

3. Scan mode and select mode are supported

4. Interrupt is generated after completion of conversion.

5. Conversion time: 5 µs (min).

Power Management

HALT, STANDBY and clock gear clock control functions are supported as
power save functions.

1. HALT mode

HALT object

- CPU, internal RAM, AHB bus control

HALT mode setting: Set by the system control register.
Exit HALT mode due to: Reset, interrupt

2. STANDBY mode
Stops the clock for the entire device.

STANDBY mode setting: Specified by the system control register.
Exit STANDBY mode due to: Reset, external interrupt (other than EFIQ_N)

3. Clock gear

The MCU has two clock systems, HCLK and CCLK. Configure HCLK
and CCLK frequency.
HCLK: CPU, bus control, synchronous serial interface, I2C.
CCLK: Timers, PWM SIO, AD converter, etc.

4. Clock control by each function unit

AD converter, PWM, Timers, DRAMC, DMAC, UART(FIFO), SIO, SSIO,
I2C.

Built-In Flash ROM Programming

The robust features of the flash permit simple and optimized programming of
the flash-ROM.

1. There are three methods for programming the FLASH-ROM

- Programming via the JTAG interface

- Programming using boot mode

Boot mode is used by the host to download data to the FLASH ROM via
the UART interface.
A program stored in the on-chip boot ROM is used to transfer the
incoming serial data on the UART interface to the internal Flash ROM.

- Programming via a user application running from external memory

Internal flash can be programmed by executing a user flash program­ming application from external memory.

2. Single power source for reading and programming of FLASH: 3.0V to

3.6V

3. Programming units: 2 bytes

4. Selectable erasing size

- Sector erase: 2 KBytes/sector

- Block erase: 64 KBytes/block

- Chip erase: All memory cell

5. Word program time: 20 µsec (2 bytes)

6. Sector/block erase time: 25 msec

7. Chip erase time: 100 msec

8. Write protection

- Block protect: top address 8Kwords can be protected

- Chip protect: all words can be protected

9. Number of commands: 9

10. Highly reliable read/program

- Sector programming: 1,000 times

- Data hold period: 10 years

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Oki Semiconductor • 5

ML674001/ML67Q4002/ML67Q4003

Pin Configuration

PIOD[6]/

XIOCS_N

XDQM[1]

PIOD[7]/
XDQM[0]

PIOB[1]/

DREQCL

R[0]

PIOB[3]/

DREQCLR[

1]

PIOC[0]/

PWMOUT[

0]

XBS_N

[0]

PIOD[2]/
XRAS_N

XIOCS_N

[3]

XIOCS_N

XIOCS_N

[2]

PIOB[2]/

PIOB[0]/

DREQ[1]

DREQ[0]

PIOB[5]/

VDD_IO GND VDD_IO VDD_

TCOUT

[1]

PIOB[4]/

GND VDD_IO XD[15] XD[11] XD[14]

TCOUT

XBS_N

PIOD[0]/

[1]

XWAIT

PIOD[1]/

VDD_IO GND VDD_IO XD[8] NC XD[9]

XCAS_N

XRAMCS_NXBWE

[1]

XWE_N PIOC[7]/

[0]

XROMCS_NXBWE_N

PIOC[1]/

PWMOUT

[0]

[1]

VDD_
CORE

_N[0]

XWR

[1]

PIOC[4]/

XOE_N

PIOC[6]/

XA[23]

PIOC[5]/

XA[22]

CORE

144-Pin LFBGA

(TOP VIEW)

XA[16] XA[14] XA[11] XA[9] XA[7] XA[6]

XA[21]

PIOC[2]/

XA[17] XA[15] XA[13] XA[10] XA[4] XA[5]

XA[19]

PIOC[3]/

XA[18] XA[12] VDD_IO XA[8] XA[2] GND

XA[20]

VDD_IO GND GND XA[3] XA[0] XD[13] XA[1]

VDD_

XD[10] NC XD[12]

CORE

N

M

L

K

J

H

G

BSEL[1] PIOD[5]/

PIOE[7]/

EXINT[2]

PIOE[0]/

SCLK

TDI PIOE[1]/

nTRST TDO TCK GND VDD_IO PIOA[0/

NC NC JSEL DRAME_NOSC0 TEST AIN[2] PIOA[2]/

13 12 11 10 987654321

PIOD[3]/

XSDCKE

XSDCLK

BSEL[0] PIOE[8]/

EXINT[3]

PIOE[6]/

PIOE[9]/

EXINT[1]

EFIQ_N

CKO TMS CKOE_N AVDD AIN[1] AIN[3] VDD_

SDI

PIOD[4]/

XSDCS_N

PIOE[5]/

EXINT[0]

PIOE[2]/

SDO

OSC1_N PIOA[1]/

SOUT

SIN

Figure 1. 144-Pin LFBGA

Notes:

1. For pins that have multiple functions, the signals are noted by their pri­mary / secondary functions.

2. NC pins can be connected to VDD_IO or GND.

GND XD[7] XD[6] XD[5]

GND XD[2] NC XD[4]

AIN[0] NC VDD_IO GND VDD_IO XD[3] XD[1]

PIOA[5]/

CORE

VREF AGND GND PIOA[3]/

PIOA[4]/

DCD

PIOA[6]

CTS

FWR XD[0] RESET

DTR

PIOA[7]/RIPIOE[4]/

DSR

PIOE[3]/

RTS

SDA

SCL

PIOB[6]/

STXD

_N

PIOB[7]/

SRXD

NC

F

E

D

C

B

A

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April 2004, Rev 2.0