Oki MSM66591, ML66592 User Manual

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Page 1

MSM66591/ML66592

User's Manual

CMOS 16-bit microcontroller

FEUL66591-66592-01

Issue Date: Mar. 4, 2002

Page 2

Preface

This document describes the hardware of the 16-bit microcontrollers MSM66591/ML66592 that employ Oki-original CPU core nX-8/500S. Shown below are the related manuals. Refer to them as required.

■ nX-8/500S Core Instruction Manual

• Description of nX-8/500S core instruction set

• Description of addressing modes

■ MAC66K Assembler Package User’s Manual

• Package overview

• Description of RAS66K [relocatable assembler] operation

• Description of RAS66K assembly language

• Description of RL66K [linker] operation

• Description of LIB66K [librarian] operation

• Description of OH66K [object converter] operation

■ Macroprocessor (MP) User’s Manual

• Description of MP operation

• Description of macro processing language

This document is subject to change without notice.

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Notation

Classification Notation Description

n Numeric value xxH Represents a hexadecimal number

xxb Represents a binary number

n Unit Word, W 1 word = 16 bits

byte, B 1 byte = 2 nibbles = 8 bits nibble, N 1 nibble = 4 bits mega-, M 10

kilo-, K 210 = 1024

kilo-, k 103 = 1000

milli-, m 10

-3

micro-, m 10

-6

nano-, n 10

-9

second, s second

n Terminology “H” level The signal level of the high side of the

voltage; indicates the voltage level of VIH and V

described in the electrical characteristics.

“L” level The signal level of the low side of the

voltage; indicates voltage level of VIL and VOL described in the electrical characteristics.

Opcode trap Operation code trap. Occurs when an empty

area that has not been assigned an instruction is fetched, or when an instruction code combination that does not contain an instruction is addressed.

n Register description

—

SCNC05SNEX04ADRUN0

"0"

2 1

ADSNM02 ADSNM01ADSNM00

ADCON0L

Invalid bit

Bit name

Bit number

Fixed bit

Invalid bit : Indicates that the bit does not exist. Writing into this bit is invalid. Fixed bit : When writing, always write the specified value. If read, the specified

value will be read. Values of fixed bits are specified as “0” or “1”.

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Contents-1

Contents

Chapter 1 Overview

1.1 Features.........................................................................................................1-2

1.2 Block Diagram ...............................................................................................1-4

1.3 Pin Configuration ...........................................................................................1-5

1.4 Basic Operation Timing .................................................................................1-6

Chapter 2 Description of Pins

2.1 P0_0–P0_7: Input/Output Pins ......................................................................2-1

2.2 P1_0–P1_7: Input/Output Pins ......................................................................2-1

2.3 P2_0–P2_7: Input/Output Pins ......................................................................2-1

2.4 P3_0–P3_7: Input/Output Pins ......................................................................2-2

2.5 P4_0–P4_7: Input/Output Pins ......................................................................2-3

2.6 P5_0–P5_7: Input/Output Pins ......................................................................2-3

2.7 P6_0–P6_7: Input/Output Pins ......................................................................2-4

2.8 P7_0–P7_7: Input/Output Pins ......................................................................2-5

2.9 P8_0–P8_7: Input/Output Pins ......................................................................2-6

2.10 P9_0–P9_7: Input/Output Pins ......................................................................2-6

2.11 P10_0–P10_7: Input/Output Pins ..................................................................2-7

2.12 P11_0–P11_7: Input/Output Pins ..................................................................2-8

2.13 P12_0, P12_1: Input/Output Pins ..................................................................2-9

2.14 AI0–AI23: Input Pins ......................................................................................2-9

2.15 AVDD: Input Pin..............................................................................................2-9

2.16 V

REF

: Input Pin ..............................................................................................2-9

2.17 AGND: Input Pin ............................................................................................2-9

2.18 OSC0, OSC1: Input Pin, Output Pin ..............................................................2-9

2.19 OE: Input Pin..................................................................................................2-9

2.20 NMI: Input Pin ................................................................................................2-9

2.21 RES: Input Pin................................................................................................ 2-9

2.22 EA: Input Pin ................................................................................................2-10

2.23 TEST: Input Pin ...........................................................................................2-10

2.24 VDD: Input Pin .............................................................................................. 2-10

2.25 GND: Input Pin............................................................................................. 2-10

2.26 Structure of Pins .......................................................................................... 2-10

2.27 Handling of Unused Pins ............................................................................. 2-12

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Contents-2

Chapter 3 CPU Architecture

3.1 Memory Space...............................................................................................3-1

3.1.1 Memory Space Expansion..........................................................................3-1

3.1.2 Program Memory Space............................................................................. 3-2

[1] Accessing Program Memory Space ...........................................................3-4

[2] Vector Table Area.......................................................................................3-4

[3] VCAL Table Area........................................................................................3-6

[4] ACAL Area..................................................................................................3-7

3.1.3 Data Memory Space ...................................................................................3-8

[1] Special Function Register (SFR) Area........................................................ 3-9

[2] Expanded Special Function Register (Expanded SFR) Area ..................... 3-9

[3] Internal RAM Area ...................................................................................... 3-9

[4] Fixed Page (FIX) Area.............................................................................. 3-10

[5] Local Register Setting Area......................................................................3-11

[6] ROM Window Setting Area.......................................................................3-11

3.1.4 Data Memory Access................................................................................3-12

[1] Byte Operation..........................................................................................3-12

[2] Word Operation ........................................................................................3-12

3.2 Registers......................................................................................................3-13

3.2.1 Arithmetic Register (ACC) ........................................................................3-13

3.2.2 Control Register........................................................................................ 3-14

[1] Program Status Word (PSW).................................................................... 3-14

[2] Program Counter (PC)..............................................................................3-17

[3] Local Register Base (LRB) .......................................................................3-17

[4] System Stack Pointer (SSP).....................................................................3-18

3.2.3 Pointing Register (PR) ..............................................................................3-19

3.2.4 Local Registers (R, ER) ............................................................................3-20

3.2.5 Segment Register .....................................................................................3-21

[1] Code Segment Register (CSR) ................................................................3-21

[2] Table Segment Register (TSR) ................................................................3-22

3.2.6 Special Function Register (SFR) ..............................................................3-23

3.3 Addressing Mode.........................................................................................3-37

3.3.1 RAM Addressing.......................................................................................3-37

[1] Register Addressing .................................................................................3-37

[2] Page Addressing ......................................................................................3-40

[3] Direct Data Addressing.............................................................................3-43

[4] Pointing Register Indirect Addressing....................................................... 3-44

[5] Special Bit Area Addressing .....................................................................3-50

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3.3.2 ROM Addressing ......................................................................................3-51

[1] Immediate Addressing..............................................................................3-51

[2] Table Data Addressing .............................................................................3-51

[3] Program Code Addressing .......................................................................3-53

[4] ROM Window Addressing......................................................................... 3-55

Chapter 4 CPU Control Functions

4.1 Standby Function...........................................................................................4-1

4.1.1 Standby Control Register (SBYCON)......................................................... 4-3

4.1.2 Operation in Each Standby Mode............................................................... 4-4

[1] HALT Mode................................................................................................. 4-4

[2] STOP Mode................................................................................................4-5

4.2 Reset Function...............................................................................................4-6

Chapter 5 Memory Control Functions

5.1 ROM Window Function..................................................................................5-1

5.2 READY Function............................................................................................5-3

Chapter 6 Port Functions

6.1 Hardware Configuration of Each Port ............................................................ 6-1

6.1.1 Configuration of Type A (P0_0–P0_7, P1_0–P1_7, P12_0).......................6-4

6.1.2 Configuration of Type B

(P2_0–P2_7, P3_0–P3_3, P7_4–P7_7, P8_0–P8_7, P10_0–P10_4) .......6-5

6.1.3 Configuration of Type C

(P3_4–P3_7, P4_0–P4_7, P5_0–P5_7, P6_0–P6_7, P7_2, P7_3,

P9_0–P9_7, P10_5–P10_7, P11_0–P11_3) ..............................................6-6

6.1.4 Configuration of Type D (P7_0, P7_1, P11_4–P11_7)............................... 6-7

6.1.5 Configuration of Type E (P12_1) ................................................................6-7

6.2 Port Control Registers ...................................................................................6-8

6.2.1 Port Data Register (Pn: n = 0–12) .............................................................6-8

6.2.2 Port Mode Register (PnIO: n = 0–12) ........................................................ 6-8

6.2.3 Port Secondary Function Control Register (PnSF: n = 2–10)....................6-8

6.3 Port 0 (P0) ...................................................................................................6-11

6.4 Port 1 (P1) ...................................................................................................6-12

6.5 Port 2 (P2) ...................................................................................................6-13

6.6 Port 3 (P3) ...................................................................................................6-15

6.7 Port 4 (P4) ...................................................................................................6-17

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Contents-4

6.8 Port 5 (P5) ...................................................................................................6-19

6.9 Port 6 (P6) ...................................................................................................6-21

6.10 Port 7 (P7) ...................................................................................................6-23

6.11 Port 8 (P8) ...................................................................................................6-25

6.12 Port 9 (P9) ...................................................................................................6-27

6.13 Port 10 (P10) ...............................................................................................6-29

6.14 Port 11 (P11) ...............................................................................................6-31

6.15 Port 12 (P12) ...............................................................................................6-32

Chapter 7 Output Pin Control Pin (OE)

Chapter 8 Clock Generation Circuit

Chapter 9 Time Base Counter (TBC)

9.1 1/n Counter ....................................................................................................9-2

Chapter 10 Watchdog Timer (WDT)

10.1 WDT Control Register (WDTCON) ..............................................................10-1

10.2 Operation of WDT ........................................................................................10-1

10.3 Time until Overflow of WDT .........................................................................10-2

10.4 Program Runaway Detection Timing Diagram ............................................10-2

Chapter 11 Flexible Timer (FTM)

11.1 Configuration of Counter Part ......................................................................11-6

11.2 Counter Selection Part................................................................................. 11-8

11.3 Type A1 Register Modules (TMR0–TMR3) ...............................................11-10

11.3.1 Configuration of Type A1 Register Modules (TMR0–TMR3) ................ 11-10

[1] Timer Registers (TMR0, TMR0L–TMR3, TMR3L)..................................11-10

[2] Capture Control Register (CAPCON) .....................................................11-11

[3] Event Control Registers (EVNTCONL, EVNTCONH)............................. 11-12

[4] Event Dividing Counters 0–3 (EVDV0–EVDV3) ..................................... 11-14

[5] EVDV0–EVDV3 Buffer Registers (EVDV0BF–EVDV3BF) ..................... 11-14

11.3.2 Operation of Type A1 Register Modules (TMR0–TMR3) ..................... 11-15

11.3.3 Capture Pin Dividing Circuit..................................................................11-16

[1] Configuration of Dividing Circuit .............................................................11-16

[2] Operation of Dividing Circuit...................................................................11-16

[3] Operation to Switch Dividing Ratio .........................................................11-16

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11.4 Type A2 Register Modules (TMR14, TMR15) ........................................... 11-17

11.4.1 Configuration of Type A2 Register Modules (TMR14, TMR15) ............ 11-17

[1] Timer Registers (TMR14, TMR15) .........................................................11-17

[2] Capture Control Register (CAPCON) .....................................................11-18

[3] Event Control Register 2 (EVNTCON2).................................................. 11-19

[4] Event Dividing Counters 14, 15 (EVDV14, EVDV15) ............................. 11-20

[5] EVDV14, EVDV15 Buffer Registers (EVDV14BF, EVDV15BF) ............. 11-20

11.4.2 Operation of Type A2 Register Modules (TMR14, TMR15) ................. 11-21

11.4.3 Capture Pin Dividing Circuit..................................................................11-22

[1] Configuration of Dividing Circuit .............................................................11-22

[2] Operation of Dividing Circuit...................................................................11-22

[3] Operation to Switch Dividing Ratio .........................................................11-22

11.5 Type B Register Modules (TMR4–TMR13) ...............................................11-23

11.5.1 Configuration of Type B Register Modules (TMR4–TMR13) ................ 11-23

[1] Timer Registers (TMR4–TMR13) ...........................................................11-24

[2] Timer Register Buffer Registers (TMR4BF–TMR13BF) ......................... 11-24

[3] Real-time Output Control Registers (RTOCON4–RTOCON13) ............. 11-24

11.5.2 Operation of Type B Register Modules (TMR4–TMR13) ....................... 11-26

11.6 Type D Register Module (TMR17) .............................................................11-27

11.6.1 Configuration of Type D Register Module (TMR17) .............................11-27

[1] Timer Register (TMR17).........................................................................11-29

[2] Real-time Output Control Registers (RTOCON17, RTO4CON) ............. 11-29

[3] TMR Mode Register (TMRMODE).......................................................... 11-31

[4] Capture Control Register (CAPCON) .....................................................11-32

11.6.2 Operation of Type D Register Module (TMR17) ...................................11-33

[1] Operation in Real-time Output Mode (RTO)...........................................11-33

[2] Operation in 4-Port Output Real-time Output Mode (4-Port RTO).......... 11-34

[3] Operation in CAP Mode..........................................................................11-35

11.7 Type E Register Module (TMR16) .............................................................11-36

11.7.1 Configuration of Type E Register Module (TMR16)..............................11-36

[1] Timer Register (TMR16).........................................................................11-37

[2] Real-time Output Control Register (RTOCON16)...................................11-37

[3] TMR Mode Register (TMRMODE).......................................................... 11-38

[4] Capture Control Register (CAPCON) ..................................................... 11-39

11.7.2 Operation of Type E Register Module (TMR16) ...................................11-40

[1] Operation in Real-time Output Mode (RTO)...........................................11-40

[2] Operation in CAP Mode..........................................................................11-40

11.8 RTO Mode Output Timing Changes .......................................................... 11-41

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Chapter 12 General-Purpose 8-Bit Timer Function

12.1 General-Purpose 8-Bit Timer (GTM) ........................................................... 12-2

[1] General-Purpose 8-Bit Timer Counter (GTMC)........................................12-3

[2] General-Purpose 8-Bit Timer Register (GTMR) .......................................12-3

[3] General-Purpose 8-Bit Timer Control Register (GTMCON) .....................12-3

[4] General-Purpose 8-Bit Timer Interrupt Control Register (GTINTCON) .... 12-5

12.2 General-Purpose 8-Bit Event Counter (GEVC) ...........................................12-6

[1] General-Purpose 8-Bit Event Counter (GEVC) ........................................12-6

[2] General-Purpose 8-Bit Timer Control Register (GTMCON) .....................12-6

[3] General-Purpose 8-Bit Timer Interrupt Control Register (GTINTCON) .... 12-7

Chapter 13 PWM Functions

13.1 Configuration of PWM.................................................................................. 13-4

[1] PWM Counters (PWC0–PWC11) .............................................................13-4

[2] PWM Counter Buffer Registers (PWC0BF–PWC11BF)...........................13-4

[3] PWM Registers (PWR0–PWR11)............................................................. 13-5

[4] PWM Buffer Registers (PW0BF–PW11BF)..............................................13-5

[5] Comparison Circuit ...................................................................................13-5

[6] Output F/F................................................................................................. 13-5

[7] PWM Control Registers (PWCON0–PWCON5) ....................................... 13-5

[8] PWMRUN Register (PWRUN)..................................................................13-9

[9] PWM Interrupt Registers (PWINTQ0, PWINTQ1) .................................. 13-10

[10] PWM Interrupt Enable Registers (PWINTE0, PWINTE1).......................13-13

13.2 Operation of PWM ..................................................................................... 13-16

Chapter 14 Baud Rate Generator Functions

14.1 Configuration of SCI0 Timer (S0TM) ........................................................... 14-3

[1] SCI0 Timer Counter..................................................................................14-3

[2] SCI0 Timer Register .................................................................................14-3

[3] SCI0 Timer Control Register (S0CON).....................................................14-3

14.2 Operation of SCI0 Timer..............................................................................14-5

14.3 Configuration of SCI1 Timer (S1TM) ........................................................... 14-6

[1] SCI1 Timer Counter..................................................................................14-6

[2] SCI1 Timer Register .................................................................................14-6

[3] SCI1 Timer Control Register (S1CON).....................................................14-6

14.4 Operation of SCI1 Timer..............................................................................14-8

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Contents-7

14.5 Configuration of SCI2 Timer (S2TM) ........................................................... 14-9

[1] SCI2 Timer Counter..................................................................................14-9

[2] SCI2 Timer Register .................................................................................14-9

[3] SCI2 Timer Control Register (S2CON).....................................................14-9

14.6 Operation of SCI2 Timer ............................................................................14-11

14.7 Configuration of SCI3 Timer (S3TM) ......................................................... 14-12

[1] SCI3 Timer Counter................................................................................14-12

[2] SCI3 Timer Register ...............................................................................14-12

[3] SCI3 Timer Control Register (S3CON)...................................................14-12

14.8 Operation of SCI3 Timer ............................................................................14-14

14.9 Configuration of SCI4 Timer (S4TM) ......................................................... 14-15

[1] SCI4 Timer Counter................................................................................14-15

[2] SCI4 Timer Register ...............................................................................14-15

[3] SCI4 Timer Control Register (S4CON)...................................................14-15

14.10 Operation of SCI4 Timer............................................................................14-17

Chapter 15 Serial Port Functions

15.1 Configuration of Serial Ports ........................................................................15-2

15.2 Serial Port Control Registers ....................................................................... 15-5

15.2.1 Control Registers for SCI0......................................................................15-5

[1] SCI0 Transmit Control Register (ST0CON)..............................................15-5

[2] SCI0 Receive Control Register (SR0CON) ..............................................15-7

[3] SCI0 Transmit/Receive Buffer Register (S0BUF0)...................................15-9

[4] SCI0 Receive Buffer Registers (S0BUF1, S0BUF2, S0BUF3).................15-9

[5] SCI0 Transmit and Receive Registers...................................................... 15-9

[6] SCI0 Status Register 0 (S0STAT0) ........................................................15-10

[7] SCI0 Status Register 1 (S0STAT1) ........................................................15-13

[8] SCI0 Status Register 2 (S0STAT2) ........................................................15-15

[9] SCI0 Interrupt Control Register (SR0INT) .............................................. 15-17

15.2.2 Control Registers for SCI1....................................................................15-19

[1] SCI1 Transmit Control Register (ST1CON)............................................15-19

[2] SCI1 Receive Control Register (SR1CON) ............................................15-21

[3] SCI1 Transmit/Receive Buffer Register (S1BUF)...................................15-23

[4] SCI1 Transmit and Receive Registers.................................................... 15-23

[5] SCI1 Status Register (S1STAT) .............................................................15-23

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Contents-8

15.2.3 Control Registers for SCI2....................................................................15-26

[1] SCI2 Transmit Control Register (ST2CON)............................................15-26

[2] SCI2 Receive Control Register (SR2CON) ............................................15-28

[3] SCI2 Transmit/Receive Buffer Register (S2BUF0).................................15-30

[4] SCI2 Receive Buffer Registers (S2BUF1, S2BUF2, S2BUF3)...............15-30

[5] SCI2 Transmit and Receive Registers.................................................... 15-30

[6] SCI2 Status Register 0 (S2STAT0) ........................................................15-31

[7] SCI2 Status Register 1 (S2STAT1) ........................................................15-34

[8] SCI2 Status Register 2 (S2STAT2) ........................................................15-36

[9] SCI2 Interrupt Control Register (SR2INT) .............................................. 15-38

15.2.4 Control Registers for SCI3....................................................................15-40

[1] SCI3 Transmit Control Register (ST3CON)............................................15-40

[2] SCI3 Receive Control Register (SR3CON) ............................................15-42

[3] SCI3 Transmit/Receive Buffer Register (S3BUF0).................................15-44

[4] SCI3 Receive Buffer Registers (S3BUF1, S3BUF2, S3BUF3)...............15-44

[5] SCI3 Transmit and Receive Registers.................................................... 15-44

[6] SCI3 Status Register 0 (S3STAT0) ........................................................15-45

[7] SCI3 Status Register 1 (S3STAT1) ........................................................15-48

[8] SCI3 Status Register 2 (S3STAT2) ........................................................15-50

[9] SCI3 Interrupt Control Register (SR3INT) .............................................. 15-52

15.2.5 Control Registers for SCI4....................................................................15-54

[1] SCI4 Transmit Control Register (ST4CON)............................................15-54

[2] SCI4 Receive Control Register (SR4CON) ............................................15-56

[3] SCI4 Transmit/Receive Buffer Register (S4BUF0).................................15-58

[4] SCI4 Receive Buffer Registers (S4BUF1, S4BUF2, S4BUF3)...............15-58

[5] SCI4 Transmit and Receive Registers.................................................... 15-58

[6] SCI4 Status Register 0 (S4STAT0) ........................................................15-59

[7] SCI4 Status Register 1 (S4STAT1) ........................................................15-62

[8] SCI4 Status Register 2 (S4STAT2) ........................................................15-64

[9] SCI4 Interrupt Control Register (SR4INT) .............................................. 15-66

15.3 Operation of Serial Ports ...........................................................................15-68

15.3.1 Transmit Operation ...............................................................................15-68

15.3.2 Receive Operation ................................................................................15-74

[1] Single Buffer Mode .................................................................................15-74

[2] 4-Stage Buffer Mode............................................................................... 15-81

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Chapter 16 A/D Converter Functions

16.1 Configuration of A/D Converter.................................................................... 16-4

[1] Scan Mode................................................................................................ 16-4

[2] Select Mode..............................................................................................16-4

[3] Hard Select Mode..................................................................................... 16-4

16.2 Control Register of A/D Converter ...............................................................16-7

[1] A/D Control Register 0L (ADCON0L) .......................................................16-7

[2] A/D Control Register 1L (ADCON1L) .......................................................16-9

[3] A/D Control Register 0H (ADCON0H) ....................................................16-11

[4] A/D Control Register 1H (ADCON1H) ....................................................16-13

[5] A/D Interrupt Control Register 0 (ADINTCON0) .....................................16-15

[6] A/D Interrupt Control Register 1 (ADINTCON1) .....................................16-17

[7] A/D Hard Select Register 0 (ADHSEL0).................................................16-19

[8] A/D Hard Select Register 1 (ADHSEL1).................................................16-22

[9] A/D Hard Select Software-Control Register (ADHSCON) ......................16-25

[10] A/D Hard Select Enable Register (ADHENCON) ...................................16-26

[11] A/D Result Registers (ADCR0–ADCR23)...............................................16-28

16.3 Generated Timing of the A/D Hard Select Mode ....................................... 16-29

Chapter 17 Transition Detector Functions

17.1 Transition Detector Control Register (TRNSCON) ...................................... 17-1

17.2 Transition Detector Register (TRNSIT)........................................................17-3

Chapter 18 Peripheral Functions

18.1 Clockout Function ........................................................................................18-1

18.2 RES Pin Valid Level Detection Function ......................................................18-1

18.3 OE Pin Monitor Function .............................................................................. 18-1

Chapter 19 External Interrupt Request Function

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Contents-10

Chapter 20 Interrupt Request Processing Function

20.1 Non-maskable Interrupt (NMI) ..................................................................... 20-2

20.2 Maskable Interrupt .......................................................................................20-4

[1] Interrupt Request Flag Disable Register IRQD

(IRQD0L, IRQD0H, IRQD1L, IRQD1H, IRQD2L) ........................... 20-6

[2] Interrupt Request Register IRQ (IRQ0L, IRQ0H, IRQ1L, IRQ1H, IRQ2L) ... 20-6

[3] Interrupt Enable Register IE (IE0L, IE0H, IE1L, IE1H, IE2L)....................20-6

[4] Master Interrupt Enable Flag (MIE) ..........................................................20-6

[5] Master Interrupt Priority Flag (MIPF) ........................................................20-6

[6] Interrupt Priority Control Register

IPX0 (IP00L, IP00H, IP10L, IP10H, IP20L),

IPX1 (IP01L, IP01H, IP11L, IP11H, IP21L) ....................................20-7

20.3 Operation of Maskable Interrupt .................................................................. 20-8

Chapter 21 Bus Port Functions

21.1 Bus Port (P0, P1, P12_0, P12_1) Functions ............................................... 21-1

21.1.1 Operation of P0, P1, P12_0 and P12_1 During a Program Memory

Access ....................................................................................................21-1

21.2 External Memory Access .............................................................................21-2

21.2.1 External Program Memory Access .........................................................21-2

21.2.2 External Program Memory Access Timing ............................................. 21-2

Chapter 22 Expansion Port

22.1 Expansion Port Configuration ......................................................................22-1

22.2 Expansion Port Control Register (EXTPCON)............................................. 22-2

22.3 Expansion Port Register (EXTPD)............................................................... 22-3

22.4 Expansion Port Operation............................................................................ 22-3

[1] Input Mode................................................................................................22-3

[2] Output Mode.............................................................................................22-4

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Chapter 23 Serial Port with FIFO (SCI5)

23.1 SCI5 Configuration ...................................................................................... 23-1

23.2 SCI5 Control Register 0 (SCI5CON0) ......................................................... 23-2

23.3 SCI5 Control Register 1 (SCI5CON1) ......................................................... 23-4

23.4 SCI5 Interrupt Register (SCI5INT) ...............................................................23-5

23.5 Serial Address Output Register (SFADR).................................................... 23-6

23.6 Serial Data Input Register (SFDIN) ............................................................. 23-7

23.7 Serial Data Output Register (SFDOUT)....................................................... 23-7

23.8 SCI5 Operation ............................................................................................23-8

Chapter 24 RAM Monitor Function

24.1 Configuration of RAM Monitor Function....................................................... 24-1

24.2 Configuration of Serial Transfer Data ..........................................................24-3

24.3 RAM Monitor Function Operation ................................................................24-5

[1] Setting the addresses............................................................................... 24-5

[2] Detection of address matching .................................................................24-5

[3] Reading data ............................................................................................24-5

Chapter 25 Electrical Characteristics

[MSM66591 Electrical Characteristics] ............................................................... 25-1

25.1 Absolute Maximum Ratings .........................................................................25-1

25.2 Operating Range ......................................................................................... 25-2

25.3 DC Characteristics .......................................................................................25-3

25.4 AC Characteristics .......................................................................................25-5

[1] External Program Memory Control ........................................................... 25-5

25.5 A/D Converter Characteristics ..................................................................... 25-6

[ML66592 Electrical Characteristics] ..................................................................25-8

25.6 Absolute Maximum Ratings .........................................................................25-8

25.7 Operating Range ......................................................................................... 25-9

25.8 DC Characteristics .....................................................................................25-10

25.9 AC Characteristics (Preliminary)................................................................25-12

[1] External Program Memory Control .........................................................25-12

25.10 A/D Converter Characteristics ...................................................................25-13

Chapter 26 Package Dimensions Chapter 27 Revision History

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Contents-12

Page 16

Chapter 1 Overview

Chapter 2 Description of Pins

Chapter 3 CPU Architecture

Chapter 4 CPU Control Functions

Chapter 5 Memory Control Functions

Chapter 6 Port Functions

Chapter 7 Output Pin Control Pin (OE)

Chapter 8 Clock Generation Circuit

Chapter 9 Time Base Counter (TBC)

Chapter 10 Watchdog Timer (WDT)

Chapter 11 Flexible Timer (FTM)

Chapter 12 General-Purpose 8-Bit Timer Function

Chapter 13 PWM Functions

Chapter 14 Baud Rate Generator Functions

Chapter 15 Serial Port Functions

Chapter 16 A/D Converter Functions

Chapter 17 Transition Detector Functions

Chapter 18 Peripheral Functions

Chapter 19 External Interrupt Request Function

Chapter 20 Interrupt Request Processing Function

Chapter 21 Bus Port Functions

Chapter 22 Expansion Port

Chapter 23 Serial Port with FIFO (SCI5)

Chapter 24 RAM Monitor Function

Chapter 25 Electrical Characteristics

Chapter 26 Package Dimensions

Chapter 27 Revision History

Page 17

Page 18

Overview

Chapter 1

Page 19

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1-1

MSM66591/ML66592 User's Manual

Chapter 1 Overview

1. Overview

The MSM66591/ML66592 are high performance 16-bit microcontrollers that contain a 16-bit CPU (nX-8/500S), ROM, RAM, a 10-bit A/D converter, serial ports, flexible timers, and PWMs. The ML66592 is the same as the MSM66591 with the exception that the ML66592 has an increased ROM and RAM capacity and a higher operating speed. Table 1-1 lists the functional differences between the MSM66591 and ML66592.

The MSM66Q591 is a Flash EEPROM version of the MSM66591. The ML66Q592 is a Flash EEPROM version of the ML66592.

Modifications in

ML66592/ML66Q592 and notes

Operating frequency (internal)

Increased by 4 MHz (with increased supply current)

20 to 24 MHz 20 to 28 MHz

Program memory space

Operating temperature –40 to +115°C –40 to +95°C Changed from +115°C to +95°C

Increased by 64K bytes

(internal) (SEG2)

Increased by 128K bytes

(external) (SEG2, 3)

External A17 output (P12_1)

has been added.

(When EA = "L")

192K bytes (internal)

256K bytes (external)

0:0000H to 3:FFFFH

128K bytes

0:0000H to 1:FFFFH

6K bytes

200H to 19FFH

8K bytes

200H to 21FFH

6K bytes

200H to 19FFH

8K bytes

0200H to 21FFH

192K bytes

0:0000H to 2:FFFFH

128K bytes

0:0000H to 1:FFFFH

Increased by 2K bytes

(1A00H to 21FFH)

Increased by 2K bytes

(1A00H to 21FFH)

…Changed from 2000H to 3000H

Increased by 64K bytes (SEG2)

One valid bit has been added

to each of CSR and TSR.

Access forbidden to the

internal SEG3.

2000H

4000H

8000H

1/2 CLK (12 MHz)

1/4 CLK (6 MHz)

1/8 CLK (3 MHz)

1/16 CLK (1.5 MHz)

2/3 CLK (16 MHz)

1/3 CLK (8 MHz)

512 CLK (21.3 µs)

384 CLK (16 µs)

256 CLK (10.7 µs)

1/4 CLK (6 MHz*)

1/8 CLK (3 MHz)

1/16 CLK (1.5 MHz)

512 CLK (18.3 µs)

384 CLK (13.7µs)

256 CLK (9.1 µs)

Not provided

1/8 CLK (3.5 MHz)

1/16 CLK (1.75 MHz)

1/2 CLK (14 MHz)

1/4 CLK (7 MHz)

1/8 CLK (3.5 MHz)

1/16 CLK (1.75 MHz)

2/3 CLK (forbidden)

1/3 CLK (9.3 MHz)

3000H

4000H

8000H

…Use of 2/3 CLK is forbidden.

ML66592/66Q592MSM66591/66Q591Item

Data memory space

Internal ROM capacity

Internal RAM capacity

Starting address for the ROM Window function

CLKOUT function

(Values in parentheses are output frequencies of the device operating at the maximum frequency)

(Values in parentheses are conversion time when the device is operating at the maximum frequency)

Transfer clock during Flash ROM reprogramming in the user mode

(MSM66Q591/ML66Q592 only)

…Should be used at 16 ms or more

…1/4 CLK has been deleted.

10-bit A/D converter conversion time

* 6 MHz is outside the guarantee

range.

Note: In the ML66592/66Q592, the AC characteristics during external program memory access apply

only when the internal operating frequency is not more than 24 MHz.

Table 1-1 Differences between MSM66591/66Q591 and ML66592/66Q592 Specifications

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1-2

MSM66591/ML66592 User's Manual Chapter 1 Overview

1.1 Features

[1] Abundant Instruction Set

• Instruction set has superb orthogonal capability

• 8/16-bit arithmetic instructions

• Multiplication/division instructions

• Bit operation instructions

• Bit logic operation instructions

• ROM table reference instructions

[2] Abundant Addressing Modes

• Register addressing

• Page addressing

• Pointing register indirect addressing

• Stack addressing

• Immediate addressing

[3] Minimum Instruction Cycle

MSM66591: 83.3 nsec @ 12 MHz (internal: 24 MHz) ML66592: 71.4 nsec @ 14 MHz (internal: 28 MHz)

[4] Program Memory (ROM)

MSM66591: Internal: 128K bytes

External: 128K bytes, EA pin active

ML66592: Internal: 192K bytes

External: 256K bytes (EA pin active)

[5] Data memory (RAM)

MSM66591: Internal: 6K bytes ML66592: Internal: 8K bytes

[6] I/O Ports

• Analog input ports: 24

• I/O ports: 98

[7] Multiplier

MSM66591: MUL ERn instruction: 208 nsec @ 12 MHz ML66592: MUL ERn instruction: 178.6 nsec @ 14 MHz

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MSM66591/ML66592 User's Manual

Chapter 1 Overview

[8] Flexible Timer

• Freerun counter: 20-bit ¥ 1, 16-bit ¥ 1

• Capture register with divider: 6

• Double-buffer realtime output: 10

• Multifunction timer: 2

[9] General-Purpose 8-Bit Timers

• General-purpose 8-bit timer: 1

• 8-bit event counter: 1 [10] 16-Bit PWM: 12 [11] 8-Bit Serial Ports

• UART with BRG (provided with a 4-stage buffer on the receive side): 4

• UART/synchronous type with BRG: 1

• Synchronous (with 8-byte FIFO): 1 [12] A/D Converter

• 10-bit resolution: 24 channels (12-channel ¥ 2) [13] Transition Detector: 8 [14] Watchdog Timer: 1 [15] Expansion Port (serial-parallel conversion): 1 [16] Interrupts

• Non-maskable: 1

• Maskable internal: 63/external: 3 (38 vectors)

• 4-level priority [17] ROM Window Functions [18] RAM Monitor Functions [19] Standby Modes

• HALT mode

• STOP mode [20] Clock Multiplier (2x original oscillation clock) [21] Package

• 144-pin plastic LQFP (LQFP144-P-2020-0.50-K)

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MSM66591/ML66592 User's Manual Chapter 1 Overview

1.2 Block Diagram

CAP0/P3_4

CAP3/P3_7 RTO4/P2_0

RTO13/P10_1 CAP14/P10_2

CAP15/P10_3 FTM16/P10_4

FTM17A/P3_0

FTM17D/P3_3

RXD1/P6_2

TXD1/P6_3

RXC1/P6_4

TXC1/P6_5

RXD0/P6_6

TXD0/P6_7

RXD2/P9_0

TXD2/P9_1

RXD3/P9_2

TXD3/P9_3

RXD4/P9_4

TXD4/P9_5

SDIN/P5_0

SDOUT/P5_1

SCLK/P5_2

RWB/P5_3

CS/P5_4

WAIT/P5_7

ETMCK/P9_6

ECTCK/P9_7

PWM0/P7_4

PWM11/P8_7

REF

AI0

AI23 AGND

P12 P11 P10 P9 P8 P7 P6 P5 P4 P3 P2 P1 P0

Serial Port

Serial Port with FIFO

General

Timer

PWM

A/D

Converter

Port Cont.

RAM

6K bytes

Memory Cont.

Pointing Reg.

Local Reg.

SSP

LRB

PSW

CSR

TSR

ALU

ALU Cont.

ACC

WDT

ROM

128K bytes

Instruction

Dec.

System

Cont.

BUS

Port

Cont.

ALE/P7_2 PSEN/P7_3

AD0/P0_0

AD7/P0_7 A8/P1_0

A16/P12_0 A17/P12_1

RES

OSC0

OSC1

SFTCLK/P10_5

SFTDAT/P10_6 SFTSTB/P10_7

TRNS0/P4_0

TRNS7/P4_7

INT0/P6_0

INT1/P6_1 INT2/P5_5 NMI

CLKOUT/P5_6

Extend

Port

Transition

Detector

Interrupt

Cont.

Peri. Cont.

CPU CORE

B U S

Flexible

Timer

*1 192K bytes for the ML66592/66Q592 *2 8K bytes for the ML66592/66Q592 *3 For the ML66592/66Q592 only

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Chapter 1 Overview

1.3 Pin Configuration

108 107 106 105 104 103 102 101 100

99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36

P2_5/RTO9 P2_4/RTO8 GND V

P2_3/RTO7 P2_2/RTO6 P2_1/RTO5 P2_0/RTO4 P11_7 P11_6 P11_5 P11_4 P11_3/(RMACK) P11_2/(RMCLK) P11_1/(RMTX) P11_0/(RMRX) TEST P12_1/A17

P12_0/A16 P1_7/A15 P1_6/A14 P1_5/A13 P1_4/A12 P1_3/A11 P1_2/A10 P1_1/A9 P1_0/A8 GND V

P0_7/AD7 P0_6/AD6 P0_5/AD5 P0_4/AD4 P0_3/AD3 P0_2/AD2 P0_1/AD1

NMI

RES

REF

AI0 AI1 AI2 AI3 AI4 AI5 AI6 AI7 AI8

AI9 AI10 AI11 AI12 AI13 AI14 AI15 AI16 AI17 AI18 AI19 AI20 AI21 AI22 AI23

AGND

GND P6_0/INT0 P6_1/INT1

P6_2/RXD1

P6_3/TXD1

3738394041424344454647484950515253545556575859606162636465666768697071

144

143

142

141

140

139

138

137

136

135

134

133

132

131

130

129

128

127

126

125

124

123

122

121

120

119

118

117

116

115

114

113

112

111

110

109

P4_7/TRNS7

P4_6/TRNS6

P4_5/TRNS5

P4_4/TRNS4

P4_3/TRNS3

P4_2/TRNS2

P4_1/TRNS1

P4_0/TRNS0

P9_7/ECTCK

P9_6/ETMCK

P9_5/TXD4

P9_4/RXD4

P9_3/TXD3

P9_2/RXD3

P9_1/TXD2

P9_0/RXD2

GND

VDDP3_7/CAP3

P3_6/CAP2

P3_5/CAP1

P3_4/CAP0

P3_3/FTM17D

P3_2/FTM17C

P3_1/FTM17B

P3_0/FTM17A

P10_7/SFTSTB

P10_6/SFTDAT

P10_5/SFTCLK

P10_4/FTM16

P10_3/CAP15

P10_2/CAP14

P10_1/RTO13

P10_0/RTO12

P2_7/RTO11

P2_6/RTO10

P6_4/RXC1

P6_5/TXC1

P6_6/RXD0

P6_7/TXD0

OSC0

OSC1

GND

P5_0/SDIN

P5_1/SDOUT

P5_2/SCLK

P5_3/RWB

P5_4/CS

P5_5/INT2

P5_6/CLKOUT

P5_7/WAIT

P7_0

P7_1

P7_2/ALE

P7_3/PSEN

P7_4/PWM0

P7_5/PWM1

P7_6/PWM2

P7_7/PWM3

GND

P8_0/PWM4

P8_1/PWM5

P8_2/PWM6

P8_3/PWM7

P8_4/PWM8

P8_5/PWM9

P8_6/PWM10

P8_7/PWM11

P0_0/AD0

144-Pin Plastic LQFP (Top View)

*1 For the ML66592/66Q592 only Note: For the package dimensions, see Chapter 26.

For handling of unused pins, see Section 2.27.

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MSM66591/ML66592 User's Manual Chapter 1 Overview

1.4 Basic Operation Timing

The MSM66591/ML66592 utilize the Oki-original 16-bit CPU core (nX-8/500S). With the nX-8/500S, the basic instruction code unit is 8 bits, and instructions are 1 byte

to 6 bytes long. Instructions are classified as either NATIVE instructions for frequent operation or COMPOSIT instructions to realize a wide addressing range.

NATIVE instructions consist of 1 to 4 bytes and achieve high code efficiency and high processing efficiency.

COMPOSIT instructions consist of a 1- to 3-byte address specification field (PREFIX) and a 1- to 3-byte operation specification field (SUFFIX). A wide addressing range can be realized by combining the PREFIX and SUFFIX.

The MSM66591/ML66592 multiply the original oscillation clock by a factor of 2 to generate the master clock pulse (CLK). One master clock pulse (CLK) forms one state. In other words, one state is 41.7 nsec (@ 12 MHz) for the MSM66591 or 35.7 nsce (@ 14 MHz) for the ML66592. The execution of a single instruction is performed over several states (S2, S3, …Sn).

The number of states required for instruction execution depends upon the instruction. The minimum is 2 states and the maximum is 48 states. (For details, refer to the "nX-8/ 500S Core Instruction Manual.")

Figures 1-1 through 1-4 show examples of the basic timing. In the case of external program memory access (EA pin = "L" level), 1 cycle (= 1 state)

is automatically inserted for a 1 byte read (fetch) operation. In addition, the number of wait cycles (0 to 3 cycles) specified by the ROM ready control register (ROMRDY) are also inserted.

For further details regarding external memory access timing, see Chapter 21, "Bus Port Functions".

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MSM66591/ML66592 User's Manual

Chapter 1 Overview

Figure 1-1 Basic Operation Timing Example (Input of Port Data)

(M1S1)

S3 S4 S1 S2 S3 S4 S1 S2 S3 S4 S5 S6 S7 S8

(M1S1) (M1S1)

n + 4n n + 1 n + 3 n + 5

P3 DATA

STABLE

P4 DATA

STABLE

Execution of LB A, P3 instruction

Execution of MOVB off N8, [DP] instruction

(DP = 0024H, LRB: internal RAM area)

Execution of

next instruction

off N8¨[DP] (RAM¨P4)AL¨P3

Fetch of 2nd byte

of LB A, P3

instruction

Fetch of MOVB

off N8, [DP]

instruction

Fetch of LB A, P3

instruction

Fetch of 2nd byte of

MOVB off N8, [DP]

instruction

Fetch of 3rd byte of

MOVB off N8, [DP]

instruction

Fetch of next

instruction

Master clock

(CLK) (internal)

State

PC (internal)

P3 (pin)

P4 (pin)

n + 2

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MSM66591/ML66592 User's Manual Chapter 1 Overview

Figure 1-2 Basic Operation Timing Example (Output to Port)

(M1S1)

S3 S4 S1 S2 S3 S4 S1 S2 S3 S4 S5 S6 S1

(M1S1) (M1S1)

n + 4n n + 1 n + 5

Execution of STB A, P3 instruction Execution of MOVB P4, #N8 instruction

Execution of

next instruction

P4¨#N8P3¨AL

Fetch of 2nd byte

of STB A, P3

instruction

Fetch of MOVB

P4, #N8

instruction

Fetch of STB A, P3

instruction

Fetch of 2nd byte

of MOVB P4, #N8

instruction

Fetch of 3rd byte

of MOVB P4, #N8

instruction

Fetch of next

instruction

Master clock

(CLK) (internal)

State

PC (internal)

P3 (pin)

P4 (pin)

OLD DATA NEW DATA (AL value)

NEW DATA

(#N8 value)

n + 2 n + 3

Fetch of 2nd byte

of next instruction

OLD DATA

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MSM66591/ML66592 User's Manual

Chapter 1 Overview

Figure 1-3 TM1 Operation Timing

(M1S1)

S4 S1 S2 S3 S4 S1 S2 S3 S4 S5 S6 S1 S2 S3

(M1S1) (M1S1)

STB A, TMCON STB A, N16[X1]

N16[X1]

¨ACCL

• The timing for the RUN bit that becomes "1" differs depending on the instruction executed.

• The timing to read TM1 differs, depending on the instruction executed.

• The count timing of TM1 differs, depending on the selected clock of TM1.

OLD DATA

(M1S1)

Master clock

(CLK) (internal)

State

TM1 count clock

TM1RUN

TM1

ACC

m + 1

m + 2 m + 3 m + 4 m + 5 m + 6

m + 4 DATA

TMCON

¨ACCL

A¨TM1

TM1 Read

ACCL = 80H

L A, TM1

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MSM66591/ML66592 User's Manual Chapter 1 Overview

Figure 1-4 Interrupt Transition Timing Example

(M1S1)

S4 S1 S2 S3 S4 S1 S2 S3 S4 S5 S6 S1 S2 S3

(M1S1) (M1S1)

• The interrupt transition cycle has 14 cycles. However, it has 17 cycles if the program memory space is extended to 128K bytes.

• IRQ is reset ("0") at the 3rd cycle of the interrupt transition cycle.

(M1S1)

Master clock

(CLK) (internal)

State

FFFC

FFFD FFFE FFFF 0000 0001 0002 0003

Instruction A Instruction B Instruction C

Interrupt

transition cycle

FFFD

FFFE FFFF 0000 0001 0002 0003 0004

Instruction A

Instruction B

Interrupt transition cycle

0005

0004

TM1 count clock

TM1

IRQ

TM1

IRQ

Page 30

Description of Pins

Chapter 2

Page 31

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MSM66591/ML66592 User's Manual

Chapter 2 Description of Pins

2. Desacacription of Pins

Chapter 2 describes each pin of the MSM66591/ML66592. For handling of unused pins, see Section 2.27.

2.1 P0_0–P0_7: Input/Output Pins

8-bit I/O pins of Port 0. I/O can be specified in bit units by the Port 0 mode register (P0IO).

If the EA pin is set to "L" level, these pins automatically function as time-shared address output and data I/O pins (AD0–AD7) for external program memory access.

At reset (when the RES signal is input, the BRK instruction is executed, the watchdog timer (WDT) is overflown, or an operation code trap is generated), P0 becomes a high impedance input.

When Port 0 is in output status, "H" or "L" level is output if the OE pin (pin 71) is in "L" level, but Port 0 goes into high impedance status if the OE pin is in "H" level.

2.2 P1_0–P1_7: Input/Output Pins

8-bit I/O pins of Port 1. I/O can be specified in bit units by the Port 1 mode register (P1IO).

By setting the EA pin to "L" leve, P1_0–P1_7 also function as output pins for internal operations (secondary function).

• A8–A15 (P1_0–P1_7) If the externally expanded data memory is accessed with the EA pin in "L" level,

these pins function as output pins to output addresses A8–A15.

At reset (when the RES signal is input, the BRK instruction is executed, the watchdog timer is overflown, or an operation code trap is generated), P1 becomes high impedance input.

When Port 1 is in output status, "H" or "L" level is output if the OE pin (pin 71) is in "L" level, but Port 1 goes into high impedance status if the OE pin is in "H" level.

2.3 P2_0–P2_7: Input/Output Pins

8-bit I/O pins of Port 2. I/O can be specified in bit units by the Port 2 mode register (P2IO).

P2_0–P2_7 also function as output pins for internal operations (secondary function). The secondary functions for P2_0–P2_7 are set in bit units by the Port 2 secondary function control register (P2SF).

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MSM66591/ML66592 User's Manual Chapter 2 Description of Pins

For the pins that have secondary functions set by P2SF, I/O settings by P2IO become invalid.

• RTO4 (P2_0)–RTO11 (P2_7) The preset level is output when the value of registers 4–11 (TMR4–TMR11) of the

flexible timer match the selected counter values.

At reset (when the RES signal is input, the BRK instruction is executed, the watchdog timer is overflown, or an operation code trap is generated), P2 becomes a high impedance input.

When Port 2 is in output status, "H" or "L" level is output if the OE pin (pin 71) is in "L" level. If the OE pin is in "H" level, Port 2 goes into high impedance status.

2.4 P3_0–P3_7: Input/Output Pins

8-bit I/O pins of Port 3. I/O can be specified in bit units by the Port 3 mode register (P3IO).

P3_0–P3_7 also function as I/O pins for internal operations (secondary function). Secondary functions for P3_0–P3_7 are set in bit units by the Port 3 secondary function

control register (P3SF). For the pins that have secondary functions set by P3SF, I/O settings by P3IO become invalid.

• FTM17A (P3_0) When register 17 (TMR17) of the flexible timer is in RTO mode, and when the value

of the TMR17 matches the selected counter value, the preset level is output. When the TMR17 is in CAP mode, FTM17A is set to input pin status. If the specified

edge is input to this pin, the selected counter value is input to the TMR17.

• FTM17B (P3_1)–FTM17D (P3_3) When the TMR17 is in 4-port output RTO mode, and when the value of the TMR17

matches the selected counter value, the preset level is output.

• CAP0 (P3_4)–CAP3 (P3_7) If the edge specified to this pin is input for a specified number of times, the selected

counter value is input to timer registers 0–3 (TMR0–TMR3).

At reset (when the RES signal is input, the BRK instruction is executed, the watchdog timer is overflown, or an operation code trap is generated), P3 becomes a high impedance input.

When P3_0–P3_3 are in output status, "H" or "L" level is output if the OE pin (pin 71) is in "L" level. If the OE pin is in "H" level, they go into high impedance status.

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Chapter 2 Description of Pins

2.5 P4_0–P4_7: Input/Output Pins

8-bit I/O pins of Port 4. I/O can be specified in bit units by the Port 4 mode register (P4IO).

P4_0–P4_7 also function as input pins for internal operations (secondary function). Secondary functions for P4_0–P4_7 are set in bit units by the Port 4 secondary function

control register (P4SF). For the pins that have secondary functions set by P4SF, I/O settings by P4IO become

invalid. <Description of Secondary Functions of Each Pin>

• TRNS0 (P4_0)–TRNS7 (P4_7) Input pins of transition detectors 0–7.

At reset (when the RES signal is input, the BRK instruction is executed, the watchdog timer is overflown, or an operation code trap is generated), P4 becomes a high impedance input.

2.6 P5_0–P5_7: Input/Output Pins

8-bit I/O pins of Port 5. I/O can be specified in bit units by the Port 5 mode register (P5IO).

P5_0–P5_7 also function as output pins for internal operations (secondary function). Secondary functions for P5_0–P5_7 are set in bit units by the Port 5 secondary function

control register (P5SF). For the pins that have secondary functions set by P5SF, I/O settings by P5IO become invalid.

• SDIN (P5_0) Data input pin of serial port 5 (synchronous SCI with FIFO)

• SDOUT (P5_1) Data output pin of serial port 5 (synchronous SCI with FIFO)

• SCLK (P5_2) Synchronous clock output pin of serial port 5 (synchronous SCI with FIFO)

•R/W (P5_3) Data read/write switch signal output pin of serial port 5 (synchronous SCI with FIFO)

• CS (P5_4) Chip select signal output pin of serial port 5 (synchronous SCI with FIFO)

• INT2 (P5_5) Dual function interrupt and external interrupt 2 input pin of serial port 5 (synchronous

SCI with FIFO)

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MSM66591/ML66592 User's Manual Chapter 2 Description of Pins

• CLKOUT (P5_6) Output pin that outputs clock pulses specified by the peripheral control register

(PRPHF)

• WAIT (P5_7) BUSY signal input pin of serial Port 5 (synchronous SCI with FIFO)

At reset (when the RES signal is input, the BRK instruction is executed, a watchdog timer is overflown, or an operation code trap is generated), P5 becomes a high impedance input.

2.7 P6_0–P6_7: Input/Output Pins

8-bit pins of Port 6. I/O can be specified in bit units by the Port 6 mode register (P6IO). P6_0–P6_7 also function as I/O pins for internal operations (secondary function). Secondary functions for P6_0–P6_7 are set in bit units by the Port 6 secondary function

control register (P6SF). For pins that have secondary functions set by P6SF, I/O settings by P6IO become

invalid. <Description of Secondary Functions of Each Pin>

• INT0 (P6_0), INT1 (P6_1) Input pins for external interrupts 0 and 1.

• RXD1 (P6_2) Input pin to input receive data at the serial port 1 receive side.

• TXD1 (P6_3) Output pin to output transmit data at the serial port 1 transmit side.

• RXC1 (P6_4) Configured to be the output pin for the shift clock if the serial port 1 receive side is in

synchronous and master mode, and configured to be the input pin of the shift clock if the receive side is in slave mode.

• TXC1 (P6_5) Becomes the output pin of the shift clock if the serial port 1 transmit side is in

synchronous mode and master mode, and becomes the input pin of the shift clock if in slave mode.

• RXD0 (P6_6) Input pin to input receive data at the serial port 0 receive side.

• TXD0 (P6_7) Output pin to output transmit data at the serial port 0 transmit side.

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Chapter 2 Description of Pins

At reset (when the RES signal is input, the BRK instruction is executed, the watchdog timer is overflown, or an operation code trap is generated), P6 becomes a high impedance input.

2.8 P7_0–P7_7: Input/Output Pins

8-bit pins of Port 7. I/O can be specified in bit units by the Port 7 mode register (P7IO). P7_2–P7_7 also function as I/O pins for internal operations (secondary function). Secondary functions for P7_2–P7_7 are set in bit units by the Port 7 secondary function

control register (P7SF). For the pins that have secondary functions set by P7SF, I/O settings by P7IO become

invalid. <Description of Secondary Functions of Each Pin>

• ALE (P7_2) When accessing external memory, this pin outputs a strobe signal to externally latch

the lower 8 bits of the address output from P0. If the EA pin has been set to a "L" level, the pin function automatically changes to the

secondary function. If both the EA and RES pins have been set to a "L" level, this pin is pulled up.

• PSEN (P7_3) When accessing external program memory, this pin outputs a strobe signal for the

read operation. If the EA pin has been set to a "L" level, the pin function automatically changes to the

secondary function. If both the EA and RES pins have been set to a "L" level, this pin is pulled up.

• PWM0 (P7_4)–PWM3 (P7_7) PWM0–PWM3 output pins.

At reset (when the RES signal is input, the BRK instruction is executed, the watchdog timer is overflown, or an operation code trap is generated), P7 becomes a high impedance input.

If the OE pin (pin 71) is in "L" level when P7_4 (PWM0)–P7_7 (PWM3) are in output status, these pins output "H" or "L" level, but if the OE pin is in "H" level, these pins go into high impedance status.

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2.9 P8_0–P8_7: Input/Output Pins

8-bit I/O pins of Port 8. I/O can be specified in bit units by the Port 8 mode register (P8IO).

P8_0–P8_7 also function as output pins for internal operations (secondary function). Secondary functions for P8_0–P8_7 are set in bit units by the Port 8 secondary function

control register (P8SF). For the pins that have secondary functions set by P8SF, I/O settings by P8IO become

invalid. <Description of Secondary Functions of Each Pin>

• PWM4 (P8_0)–PWM11 (P8_7) Output Pins of PWM4–PWM11

At reset (when the RES signal is input, the BRK instruction is executed, the watchdog timer is overflown, or an operation code trap is generated), P8 becomes a high impedance input.

If the OE pin (pin 71) is in "L" level when P8 is in output status, these pins output "H" or "L" level, but if the OE pin is in "H" level, these pins go into high impedance status.

2.10 P9_0–P9_7: Input/Output Pins

8-bit I/O pins of Port 9. I/O can be specified in bit units by the Port 9 mode register (P9IO).

P9_0–P9_7 also functions as an output pin for internal operations (secondary function). Secondary functions for P9_0–P9_7 are set in bit units by the Port 9 secondary function

control register (P9SF). For the pins that have secondary functions set by P9SF, I/O settings by P9IO become invalid.

• RXD2 (P9_0) Receive data for the receive side serial port 2 is input through this pin.

• TXD2 (P9_1) Transmit data for the transmit side serial port 2 is output through this pin.

• RXD3 (P9_2) Receive data for the receive side serial port 3 is input through this pin.

• TXD3 (P9_3) Transmit data for the transmit side serial port 3 is output through this pin.

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Chapter 2 Description of Pins

• RXD4 (P9_4) Receive data for the receive side serial port 4 is output through this pin.

• TXD4 (P9_5) Transmit data for the transmit side serial port 4 is input through this pin.

• ETMCK (P9_6) External clock input pin of the general-purpose 8-bit timer counter.

• ECTCK (P9_7) External clock input pin of the general-purpose 8-bit event counter.

At reset (when the RES signal is input, the BRK instruction is executed, a watchdog timer is overflown, or an operation code trap is generated), P9 becomes a high impedance input.

2.11 P10_0–P10_7: Input/Output Pins

8-bit I/O pins of Port 10. I/O can be specified in bit units by the Port 10 mode register (P10IO).

P10_0–P10_7 also function as output pins for internal operations (secondary function). Secondary functions for P10_0–P10_7 are set in bit units by the Port 10 secondary

function control register (P10SF). For the pins that have secondary functions set by P10SF, I/O settings by P10IO be-

come invalid. <Description of Secondary Functions of Each Pin>

• RTO12 (P10_0), RTO13 (P10_1) The output pins from which the set level is output when the value of the registers 12

and 13 (TMR12, TMR13) for the flexible timer is consistent with the value of the selected counter. These are I/O pins that output the set level.

• CAP14 (P10_2), CAP15 (P10_3) When the specified edge is input to these pins for the specified number of times, the

value of the selected counter is input to TMR14, TMR15.

• FTM16 (P10_4) Output pins from which set level is output when the value of the register 16 (TMR16)

for the flexible timer matches the value of the selected counter. This is true when the TMR16 is in RTO mode.

If this register is in CAP mode, the FTM16 pin is configured to be input pin. When the specified edge is input to this pin, the value of the selected counter is input to TMR16.

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MSM66591/ML66592 User's Manual Chapter 2 Description of Pins

• SFTCLK (P10_5) Shift clock output pin for the expansion port.

• SFTDAT (P10_6) Serial data input/output pin for the expansion port.

• SFTSTB (P10_7) Strobe signal output pin for externally latching serial data through the expansion port.

At reset (when the RES signal is input, the BRK instruction is executed, the watchdog timer is overflown, or an operation code trap is generated), P10 becomes a high impedance input.

If the OE pin (pin 71) is in "L" level when P10_0–P10_4 are in output status, these pins output "H" or "L" level, but if the OE pin is in "H" level, these pins go into high impedance status.

2.12 P11_0–P11_7: Input/Output Pins

8-bit I/O pins of Port 11. Individual bits can be specified as input or output by the Port 11 mode register (P11IO).

P11_0–P11_3 also function (secondary and tertiary functions) as I/O pins for internal operation.

• RMRX (P11_0) Address input pin for RAM monitor function.

Also functions (tertiary function) as data I/O pin for serial write mode of the MSM66Q591/ML66Q592 flash EEPROM.

• RMTX (P11_1) Data output pin for RAM monitor function.

• RMCLK (P11_2) Synchronous clock input pin for RAM monitor function.

Also functions (tertiary function) as clock input pin for serial write mode of the MSM66Q591/ML66Q592 Flash EEPROM.

• RMACK (P11_3) Address match signal output pin for RAM monitor function.

At reset (when the RES signal is input, the BRK instruction is executed, the watchdog timer is overflown, or an operation code trap is generated), P11 becomes a high impedance input, except when the RAM monitor function is enabled.

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Chapter 2 Description of Pins

2.13 P12_0, P12_1: Input/Output Pins

2-bit I/O pins of Port 12. Individual bits can be specified as input or output by the Port 12 mode register (P12IO).

P12_0 can also be made to function (secondary function) as an output pin for internal operation by setting the EA pin to a "L" level. In the ML66592, P12_1, also, functions as its secondary function.

• A16 (P12_0) If the EA pin has been set to a "L" level, this pin functions to output address A16 that

is used to access external expanded program memory.

• A17 (P12_1) If the EA pin has been set to a "L" level, this pin functions to output address A17 that

is used to access external expanded program memory. (

ML66592 only)

2.14 AI0–AI23: Input Pins

Analog input pins of the A/D converter.

2.15 AVDD: Input Pin

Power input pin of the A/D converter. Supply the same voltage as VDD to this pin.

2.16 V

REF

: Input Pin

Reference voltage input pin of the A/D converter.

2.17 AGND: Input Pin

GND pin of the A/D converter.

2.18 OSC0, OSC1: Input Pin, Output Pin

Connection pins to connect the crystal oscillator, ceramic resonator or capacitors for basic clock oscillation. If the basic clock is supplied externally, input to the OSC0 pin, and leave the OSC1 pin open.

2.19 OE: Input Pin

When the OE pin is in "H" level, and when each of P0–P2, P3_0–P3_3, P7_4–P7_7, P8, P10_0–P10_4, P12_0, and P12_1 is in output status, each pin goes into high impedance state.

2.20 NMI: Input Pin

Input pin of a non-maskable interrupt request.

2.21 RES: Input Pin

Input pin of low active reset.

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2.22 EA: Input Pin

If the EA pin is set to "H" level, internal program memory is accessed for the entire program address (0H–1FFFFH).

When in "H" level, the RAM monitor function is enabled. If the EA pin is set to "L" level, external program memory is accessed for the entire

program address. In the MSM66Q591/ML66Q592 flash EEPROM version, the RAM monitor function

becomes enabled by setting the EA pin to a "H" level. Do not apply a high voltage (more than 5 V) to the EA pin when using the MSM66591/

ML66592 mask ROM version.

2.23 TEST: Input Pin

Load test pin. Connect to GND. In the MSM66Q591/ML66Q592 flash EEPROM version, this pin becomes a high

voltage supply pin while writing to the flash EEPROM. In the MSM66591/ML66592 mask ROM version, the RAM monitor function becomes

enabled by setting the TEST pin to "H" level. Do not apply a high voltage (more than 5 V) to this pin.

2.24 VDD: Input Pin

Power pin. Connect all the VDD pins (pins 4, 41, 61, 80, 105, 127) to the power supply. Connect a bypass capacitor of 0.01 to 0.1 µF between the VDD and GND pins.

2.25 GND: Input Pin

GND pin. Connect all the GND pins (pins 32, 44, 62, 81, 106, 128) to the ground.

2.26 Structure of Pins

Table 2-1 and Figure 2-1 show the basic structure of each MSM66591/ML66592 pin.

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Chapter 2 Description of Pins

Figure 2-1 Pin Structure Types

Type 1

Schmitt inverter input

Type 2

Schmitt inverter input with pull-up resistance

A/D ON

Type 4

IN/

OUT

The IN/OUT pin is pulled up if the EA and RES pins are both in "L" level.

"H" level CONT.

DATA

Hiz. CONT.

Type 5, 6

IN/

OUT

During output:

DATA

Hiz. CONT.

Type 3

During type 5 input: Schmitt inverter input (CMOS). During type 6 input: Schmitt inverter input (TTL).

push-pull output that can output high impedance.

Ø Ø

Pin Name Type No. Pin Name Type No.

P0_0–P0_7 6 P8_0–P8_7 5

P1_0–P1_7 5 P9_0–P9_7 5

P2_0–P2_7 5 P10_0–P10_7 5

P3_0–P3_7 5 P11_0–P11_7 5

P4_0–P4_7 5 P12_0, P12_1 5

P5_0–P5_7 5 AI0–AI23 3

P6_0–P6_7 5

OE 1

P7_0, P7_1 5 RES 2

P7_2, P7_3

4 EA 1

P7_4–P7_7

5 TEST 1

NMI

Table 2-1 Structure of Each Pin

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2.27 Handling of Unused Pins

Table 2-2 shows how unused pins should be handled.

Table 2-2 Handling of Unused Pins

Pin Recommended pin handling

P0_0–P0_7

P1_0–P1_7

P2_0–P2_7

P3_0–P3_7

P4_0–P4_7

P5_0–P5_5

P6_0–P6_7

P7_0–P7_7

P8_0–P8_7

P9_0–P9_7

P10_0–P10_7

P11_0–P11_7

AI0–AI23

REF

AGND

NMI

For input setting: "H" or "L" level For output setting: open

Connect to V

REF

or AGND

Connect to GND

Set to "L" level

Set to "H" or "L" level

Set to "H" level

Connect to V

P12_0, P12_1

TEST Set to "L" level

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CPU Architecture

Chapter 3

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Chapter 3 CPU Architecture

3. CPU Architecture

3.1 Memory Space

Program memory space and data memory space in MSM66591/ML66592 are set independently. At reset, up to 64K bytes (small-sized memory model) can be accessed for program memory space, and up to 6K bytes (MSM66591) or 8K bytes (ML66592) for data memory space. By changing the setting of the memory size control register allocated to the SFR, the program memory space can be expanded up to 128K bytes (MSM66591) or 192K bytes (ML66592) (medium-sized memory model).

3.1.1 Memory Space Expansion

The memory size control register (MEMSCON) is a register allocated to the SFR area and specifies the size of the memory space. The program memory space can be expanded to 128K bytes (medium-sized memory model) by setting the LROM bit (bit 1) to "1". (Write "0" to bit 0.)

To write to the LROM bit of MEMSCON, first write "5H" to the high-order 4 bits (loworder 4 bits are arbitrary data) of the memory size accepter (MEMSACP) allocated to the SFR area, then write "0AH" to them successively.

When an FJ or FCAL is executed with the LROM bit "0", an OP code trap is generated and a reset occurs.

When data is written to the LROM bit (setting to "1"), an actual memory space expansion is enabled after the instruction next to a LROM bit write instruction (setting to "1") is executed.

76543210

——————

LROM

"0"

MEMSCON

Program Memory Space 64K bytes

Program Memory Space 128K bytes

"—" indicates a bit that is not provided. "1" is read if a read instruction is executed. "0" indicates a bit that is not provided. "0" is read if a read instruction is executed. Always write "0" to this bit for write.

*1 192K bytes for the ML66Q592

76543210

MEMSACP

Writing to MEMSCON is enabled by writing "5H" and "0AH" succesively.

————

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Following is a programing example when expanding the program memory space. This example indicates that the program memory space is expanded up to 128K bytes

(MSM66591) or 192K bytes (ML66592) after the execution of NOP instruction.

MOVB MEMSACP, #50H MOVB MEMSACP, #0A0H SB LROM NOP

MSMSCON can be written only once after reset. Therefore, resetting (by RES signal input, by execution of BRK instruction, by watchdog timer (WDT) overflow, or by an operation code trap) is the only way to restore the program memory size to 64K bytes after it has been expanded to 128K bytes (MSM66591) or 192K bytes (ML66592).

3.1.2 Program Memory Space

Program memory space is referred to as "ROM space." The MSM66591 can access a maximum of 128K (131072) bytes of program memory in 64K (65536)-byte unit (segment) for segments 0 and 1. The ML66592 can access a maximum of 192K (196608) bytes of program memory in 64K (65536)-byte unit (segment) for segments 0, 1 and 2. Since segment 3 is not provided, do not try to access it. However, if more than 64K bytes (segments 1 and 2) are accessed, the LROM bit of the MEMSCON (memory size control register) allocated to SFR must be set to "1".

The code segment register (CSR) specifies the segment to be used, and the program counter (PC) specifies the address in the segment. However, the segment to be used at execution of ROM table reference instructions (LC A, obj etc.) and the ROM window functions is specified by the table segment register (TSR).

In the MSM66591, the entire 128K-byte area of the sum of the 64K (65536)-byte area in segment 0 and the 64K (65536)-byte area in segment 1 is the internal ROM area.

In the ML66592, the entire 192K (196608)-byte area of the sum of the 64K-byte area in segment 0 and each 64K-byte area in segment 1 and segment 2 is the internal ROM area.

The following areas are assigned to segment 0:

- Vector table area (86 bytes)

- VCAL table area (32 bytes) The ACAL area (2048 bytes) is assigned to each segment. Figures 3-1(a) and 3-1(b) show the memory maps of program memory space.

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Chapter 3 CPU Architecture

17FFH

1800H

FFFFH

0FFFH

1000H

0069H

006AH

0049H

004AH

0000H

Vector table area

(74 bytes)

VCAL table area

(32 bytes)

ACAL area

(2K bytes)

ACAL area

(2K bytes)

17FFH 1800H

FFFFH

0FFFH 1000H

0000H

Internal

ROM area

Segment 0 Segment 1

Internal

ROM area

0075H 0076H

Vector table area

(12 bytes)

Figure 3-1(a) Memory Map of MSM66591 Program Memory Space

Figure 3-1(b) Memory Map of ML66592 Program Memory Space

17FFH 1800H

FFFFH

0FFFH 1000H

0069H 006AH

0049H 004AH

0000H

Vector table area

(74 bytes)

VCAL table area

(32 bytes)

ACAL area

(2K bytes)

ACAL area

(2K bytes)

17FFH 1800H

FFFFH

0FFFH 1000H

0000H

Internal

ROM area

Segment 0 Segment 1

ACAL area

(2K bytes)

17FFH 1800H

FFFFH

0FFFH 1000H

0000H

Internal

ROM area

Segment 2

Internal

ROM area

0075H 0076H

Vector table area

(12 bytes)

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[1] Accessing Program Memory Space

Program memory space is usually accessed by the program counter (PC) and the code segment register (CSR). However, when a ROM table reference instruction (LC A, obj...etc.) or a ROM window function (see Section 5.1) is executed, program memory space is accessed by the content of the table segment register (TSR) and the register specified by the instruction.

Accessing the internal ROM area and the external memory (ROM) area of the program memory space is automatically switched by an internal MSM66591/ML66592 operation by the status of the EA pin (input: pin 3).

When "H" level is input to the EA pin, the internal program memory area is accessed for the entire program address. When "L" level is input to the EA pin, the external program memory area is accessed for the entire program address.

If the external memory area of the program memory space is accessed with the EA pin in "L" level, Port 0 (I/O: pins 72–79: output of low address and input of data), Port 1 (output: pins 82–89: output of high address) and P12_0/A16 pin (output: pin 90: output of code segment) operates as the bus port, and the P7_3/PSEN pin (output: pin 56) becomes active synchronizing with the P7_2/ALE pin (output: pin 55). In ML66592, P12_1/A17 (output: pin 91: output of code segment) also operates as a bus port.

In MSM66591, the internal program fetch enable area is 00000H–1FFFDH. This means that the final address of instruction code must not exceed 1FFFDH. The final address of the table data is 1FFFFH.

In ML66592, the internal program fetch enable area is 00000H–2FFFDH. This means that the final address of instruction code must not exceed 2FFFDH. The final address of the table data is 2FFFFH.

Segment 3 is not provided in the ML66592. Therefore, do not access address 30000H or later.

[2] Vector Table Area

The 74-byte area and 12-byte area of program memory space, which are 0000H–0049H and 006AH–0074H in segment 0 respectively, are the vector table area (43 types). This program memory space is used to store branch addresses caused by reset by RES (input: pin 2) input, reset by execution of BRK instruction, reset by watchdog timer (WDT) overflow, and reset by an operation code trap (OPTRP). It is also used to store branch addresses by various interrupt requests.

If a reset or interrupt occurs, a 2-byte content of a branch address, stored in the corresponding vector table, is loaded to the PC (an even address is insignificant data, the following odd address is significant data), while at the same time "0" is loaded to the CSR, and program execution starts from the loaded address in segment 0. Therefore, if the reset or interrupt occurs during execution of the instruction for segment 1, the program is executed from an address in segment 0.

If this area is not used as a vector table area, it can be used as a normal program area.

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Vector Table First Address [H] Cause

0000 Reset by RES pin input

0002 Reset by BRK instruction execution

0004 Reset by WDT

0006 Reset by OPTRP (operation code trap)

0008 Interrupt by NMI pin input

000A Interrupt by external interrupt pin input (INT0)

000C Interrupt by TM0 overflow

000E Interrupt by TM1 overflow

0010 Interrupt by CAP0 event generation

0012 Interrupt by CAP1 event generation

0014 Interrupt by CAP2 event generation

0016 Interrupt by CAP3 event generation

0018 Interrupt by double buffer RTO4 event generation

001A Interrupt by double buffer RTO5 event generation

001C Interrupt by double buffer RTO6 event generation

001E Interrupt by double buffer RTO7 event generation

0020 Interrupt by double buffer RTO8 event generation

0022 Interrupt by double buffer RTO9 event generation

0024 Interrupt by double buffer RTO10 event generation

0026 Interrupt by double buffer RTO11 event generation

0028 Interrupt by SCI1 transmit/receive

002A Interrupt by S0TM/S1TM/S2TM/S3TM/S4TM overflow

002C Interrupt by GTMC/GEVC overflow

002E

Interrupt by end of conversion by A/D converter 1 in scan/select/hard select mode

0030

Interrupt by end of conversion by A/D converter 0 in scan/select/hard select mode

0032

Interrupt by PWC0/PWC1 underflow or match

0034

Interrupt by PWC2/PWC3 underflow or match

0036 Interrupt by SCI0 transmit/receive

0038 Interrupt by external interrupt pin input (INT1)

0040

Interrupt by PWC6/PWC7 underflow or match

003A Interrupt by double buffer RTO12 event generation

003C Interrupt by double buffer RTO13 event generation

003E

Interrupt by PWC4/PWC5 underflow or match

0042 Interrupt by CAP14 event generation

0044 Interrupt by CAP15 event generation

0046 Interrupt by flexible FTM16 event generation

0048 Interrupt by flexible FTM17 event generation

[Example] If the program start address by RES pin input is 0200H:

Program Address Data Code

0000H 00H (insignificant data of program start address) 0001H 02H (significant data of program start address)

Table 3-1 Vector Table List

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Table 3-1 Vector Table List (continued)

Vector Table First Address [H] Cause

6AH Interrut by PWC8/PWC9 underflow or match

6CH Interrut by PWC10/PWC11 underflow or match

6EH Interrupt by SCI2 transmit/receive

70H Interrupt by SCI3 transmit/receive

72H Interrupt by SCI4 transmit/receive

74H

Interrupt by SCI5 transmit/receive or external interrupt pin input (INT2)

[3] VCAL Table Area

32-byte area of program memory space, 004AH–0069H in segment 0, is the VCAL table area to store branch addresses of 1 byte of a call instruction (VCAL: 16 types).

If a VCAL instruction is executed, the next address of the VCAL instruction is saved to the system stack, the system stack pointer (SSP) is decremented by 2, 2 bytes of the branch address content, stored in the corresponding vector address, is loaded to the PC (even address is insignificant data, the following odd address is significant data), and program execution is started from the loaded address.

If, however, the program memory space is expanded to 128K bytes (MSM66591) or 192K bytes (ML66592), the SSP is decremented by 4 because the CSR value is saved at the same time that the PC is saved. Also, "0" is loaded to the CSR at the same time that the branch address content is loaded to the PC. Therefore, if the VCAL instruction is executed in segment 1, the program is executed from a branch address in segment

0. When the program memory space is 64K bytes (the LROM bit of MEMSCON is ''0''), the

subroutine branched by the VCAL instruction is returned by the RT instruction. When the program memory space is 128K bytes (MSM66591) or 192K bytes (ML66592) (the LROM bit is ''1''), the subroutine is returned by the FRT instruction.

If this area is not used as the VCAL table area, it can be used as a normal program area.

Table 3-2 shows the VCAL vector address list.

[Example] The program start address by VCAL 4AH is 0400H.

Program Address Data Code

004AH 00H (insignificant data of subroutine first address) 004BH 04H (significant data of subroutine first address)

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Table 3-2 VCAL Vector Address List

VCAL Table First Address [H] VCAL Instruction

004A VCAL 4AH

004C VCAL 4CH

004E VCAL 4EH

0050 VCAL 50H

0052 VCAL 52H

0054 VCAL 54H

0056 VCAL 56H

0058 VCAL 58H

005A VCAL 5AH

005C VCAL 5CH

005E VCAL 5EH

0060 VCAL 60H

0062 VCAL 62H

0064 VCAL 64H

0066 VCAL 66H

0068 VCAL 68H

[4] ACAL Area

2K-byte area of program memory space for each segment, 1000H–17FFH, is an area that can directly call subroutines by a 2-byte call instruction (ACAL). Since the ACAL instruction can call subroutines in the current segment, when an ACAL instruction is executed in segment 1, the ACAL area in segment 1 is called. If an ACAL instruction is executed, the next address of the next ACAL instruction is saved to the system stack, the system stack pointer (SSP) is decremented by 2, 11 bits of data, included in ACAL instruction code, is loaded to the PC, and program execution is started from the loaded address (1000H–17FFH). The CSR value does not change.

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Figure 3-2(a) Memory Map of MSM66591 Data Memory Space

3.1.3 Data Memory Space

Data memory space is referred to "RAM space". The MSM66591 can access a maximum of 6K (6144) bytes of data memory. The ML66592 can access a maximum of 8K (8192) bytes of data memory. The following areas are assigned to the data memory space: a special function register

area (SFR area: 256 bytes), an expanded SFR area (256 bytes), a fixed page area (FIX area: 256 bytes), an internal RAM area (MSM66591: 6144 bytes, ML66592: 8192 bytes), a local register setting area (2048 bytes), and a ROM window setting area (MSM66591: 57344 bytes, ML66592: 53248 bytes).

The pointing register area (PR: 64 bytes) and the special bit addressing area (sbafix: 64 bytes) are located in the fixed page area.

In MSM66591, access to the area from 1A00H–FFFFH is inhibited since it is not located in internal RAM. However, the ROM window setting area (2000H–FFFFH) can be accessed only if the ROM window has been set.

In ML66592, access to the area from 2200H–FFFFH is inhibited since it is not located in internal RAM. However, the ROM window setting area (3000H–FFFFH) can be accessed only if the ROM window has been set.

Figures 3-2(a) and 3-2(b) show the memory maps of the data memory space.

0000H

00FFH 0100H 01FFH 0200H 02FFH 0300H

09FFH 0A00H

19FFH 1A00H

1FFFH 2000H

FFFFH

ROM Window

Setting Area

Internal RAM area

Local register setting area

SFR Area

Expanded SFR Area

FIX Area

Access Inhibit Area

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[1] Special Function Register (SFR) Area

The following are assigned to the 256-byte area of data memory space, 0000H–00FFH: such special function registers as mode registers of MSM66591/ML66592 internal peripheral hardware, control registers and a counter.

[2] Expanded Special Function Register (Expanded SFR) Area

The same special function registers that the SFR area has are assigned to the 256 byte area of data memory space, 0100H–01FFH.

[3] Internal RAM Area

In the MSM66591, internal RAM is assigned to the 6K (6144)-byte area of data memory space, 0200H–19FFH.

In the ML66592, internal RAM is assigned to the 8K (8192)-byte area of data memory space, 0200H–21FFH.

Figure 3-2(b) Memory Map of ML66592 Data Memory Space

0000H

00FFH 0100H 01FFH 0200H 02FFH 0300H

09FFH 0A00H

21FFH 2200H

2FFFH 3000H

FFFFH

ROM Window

Setting Area

Internal RAM area

Local register setting area

SFR Area

Expanded SFR Area

FIX Area

Access Inhibit Area

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Figure 3-3 Map of Fixed Page Area

USP

Pointing register set

SCB = 0

SCB = 1

SCB = 7

Expanded SFR Area

SBA Area

64 Bytes

Fixed page area

In this area, SB, RB, JBS and JBR instructions, with sba.bit as the object, can be used.

01FFH 0200H

0208H

0210H

0238H

0240H

02C0H

0300H

[4] Fixed Page (FIX) Area

The following are assigned to the 256-byte area of data memory space, 0200H–02FFH: a pointing register (PR) area, and a special bit address area (sbafix).

The pointing register area is assigned to 0200H–023FH, and it has 8 sets of the following 4 registers.

• index registers (X1, X2)

• data pointer (DP)

• user stack pointer (USP)

All are 16-bit registers. Even addresses are insignificant data, and the following odd addresses are significant data.

The special bit address area is assigned to 02C0H–02FFH, so that SB, RB, JBR and JBS instructions to this area can be implemented in a small number of bytes.

Figure 3-3 shows the map of the fixed page area.

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[5] Local Register Setting Area

A 2K-byte area of data memory, 0200H–09FFH, is the local register setting area. The local register is specified by LRB low-order 8 bits (LRBL) in 8-byte units.

Figure 3-4 shows the map of the local register setting area.

ER0

R0 R1

ER1

R2 R3

ER2

R4 R5

ER3

R6 R7

ER0

R0 R1

0200H

0208H

0A00H

R6 R7

LRBL = 00H

LRBL = 01H

LRBL = FFH

ER3

Local register setting area: specified by LRBL 8 bits, in 8-byte units

0000H

0100H

0200H

0300H

0A00H

19FFH

FIX Area

Expanded SFR Area

SFR Area

Internal

RAM area

*1 For the ML66592, the internal RAM area

is 200H to 21FFH.

[6] ROM Window Setting Area

The 56K (57344)-byte area from 2000H to FFFFH in the data memory space of the MSM66591 is not allocated as data memory. However, this area is used by the ROM window function if set by the ROM window setting register.

The 52K (53248)-byte area from 3000H to FFFFH in the data memory space of the MSM66591 is not allocated as data memory. However, this area is used by the ROM window function if set by the ROM window setting register.

Corresponding to the specified area (MSM66591: 2000H and above, ML66592: 3000H and above) of data memory, the ROM window function enables instructions to access (read operation) data in the program space at the same address instead of data in the data memory space.

There are two conditions for the ROM window function to be valid, (1) register settings (ROMWIN) must enable the ROM window function, and (2) the accessed address (read operation) must be in external data memory area.

Figure 3-4 Map of Local Register Setting Area

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3.1.4 Data Memory Access

Examples of memory access when a byte operation and a word operation are performed to a data memory space by an instruction are shown below.

[1] Byte Operation

In the case of a byte operation, the 8-bit data indicated by the address specified by an instruction becomes the target.

[Example] LB A, [DP]: when content of DP is 0335H

[2] Word Operation

In the case of a word operation, the target is 16-bit data with 8-bit data indicated by an address in which the least significant bit (LSB) "0" (even address) becomes low-order 8-bit data, and 8-bit data indicated by an address in which LSB "1" (odd address) becomes high-order 8-bit data.

16-bit data where low-order 8 bits are allocated in an odd address and high-order 8 bits are allocated in an even address is inaccessible. (A boundary exists during word operation.) Such a boundary does not exists in the program memory space.

[Example] L A, [DP]: when content of DP is 0334H (or 0335H)

In the avobe example, 16-bit data where low-order 8 bits are allocated in 0333H and highorder 8 bits are allocated in 0334H is inaccessible.

0335H

0336H

0337H

0338H

0332H

0333H

0334H

15 ACC 0

0334H

0335H

0336H

0337H

0331H

0332H

0333H

15 ACC 0

0330H

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3.2 Registers

Registers are classified by the following functions: the arithmetic registers, control registers, pointing registers, special function registers, local registers, and segment registers.

Figure 3-5 shows the configuration of each register.

Figure 3-5 Configuration of Register

ACC

15 0

Arithmetic register

15 0

Pointing register

USP

7 0 7 0

R3 R2

Local register

R5 R4

R7 R6

(ER0)

(ER1)

(ER2)

(ER3)

7 0 7 0

3 2

253 252

255 254

Special function register (SFR)

PSW

15 0

Control register

P C

LRB

SSP

CSR

7 0

Segment register

TSR

3.2.1 Arithmetic Register (ACC)

The 16-bit arithmetic register is the accumulator (ACC), a central register for various operations.

If the transfer, operation, etc. is

• Word type, all 16 bits (bits 15–0) are accessed.

• Byte type, the low-order 8 bits (bits 7–0) are accessed.

• Nibble type, the low-order 4 bits (bits 3–0) are accessed. If the target bits are specified (SBR, RBR...) by ACC with a bit operation instruction,

the high-order 5 bits (bits 7–3) of the low-order 8 bits become the offset specification of an address, and the low-order 3 bits (bits 2–0) become the bit position specification.

ACC is assigned to SFR, and the content becomes 0000H at reset (when the RES signal is input, the BRK instruction is executed, the watchdog timer is overflown, or an operation code trap is generated.)

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PSWLPSWH

PSW

1514131211109876543210

CY ZF HC DD S F2 OV MIE MAB F1

BCB

SCB

10 210

Figure 3-6 Configuration of PSW

3.2.2 Control Register

Control registers are a group of registers that have dedicated functions, such as functions for program status, program sequence, local registers, and stack control. Control registers consist of four 16-bit registers.

[1] Program Status Word (PSW)

PSW is a 16-bit register that consists of

• flags to be referred to when executing an instruction (DD)

• flags that are set to "1" or "0" depending on the result of an executing instruction (CY, ZF, HC, S, OV)

• flags to specify the pointing register set (SCB0–2)

• flags to specify enable ("1") or disable ("0") of an entire maskable interrupt (MIE)

• flags that the user can freely use (F0–2)

• flags available for future expansion of CPU core functions. The user can freely use these flags in MSM66591/ML66592. (BCB0, 1, MAB)

PSW can be divided into PSWH (bits 8–15) and PSWL (bits 7–0) in 8-bit units, and can perform 8-bit unit operations as well as 16-bit unit operations depending on the instruction.

Figure 3-6 shows the configuration of PSW.

High-order 8 bits (PSWH) of PSW include:

• flags to be referred to when executing an instruction (DD)

• flags that are set to "1" or "0" depending on the result of an executing instruction (CY, ZF, HC, DD, S, OV)

This means that if the following instructions are executed to PSW or PSWH, the operation may be different from the original operation of the flags.

A.PSW or PSWH content load instruction to ACC

(ZF becomes undefined)

B.Bit operation instruction to ZF (ZF becomes undefined)

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C.Instructions for increment, decrement, and arithmetic and logic operation and com-

parison to PSW or PSWH (content of PSW or PSWH is undefined after the instruction is executed).

If an interrupt occurs, PSW is automatically saved during an interrupt transition cycle, and automatically returns when an RTI instruction is executed.

PSW is assigned to SFR, and the content becomes 0000H at reset (when the RES signal is input, the BRK instruction is executed, the watchdog timer is overflown, or an operation code trap is generated.)

A description of each PSW bit follows: Bit 15: carry flag (CY)

A carry flag is set to "1" if:

• carry from bit 7 occurs in a byte operation

• borrow to bit 7 occurs in a byte operation

• carry from bit 15 occurs in a word operation

• borrow to bit 15 occurs in a word operation as a result of executing an arithmetic instruction and a comparison instruction, otherwise, it is set to "0". Carry flags can be set/reset depending on the instruction, and can transmit/receive data for the bit specified by register. A carry flag can be tested by a conditional branch instruction.

Bit 14: zero flag (ZF) A zero flag is set to "1" if:

• the value is zero as a result of an arithmetic instruction execution

• the loaded content is zero when a load instruction to ACC is executed

• the target bit is zero when a bit operation instruction is executed

otherwise, it is set to "0". A zero flag can be tested by a conditional branch instruction. Bit 13: half carry flag (HC)

A half carry flag is set to "1" if a carry or borrow from bit 3 occurs as a result of executing an arithmetic operation and comparison instruction (same for both byte and word operations), otherwise, it is set to "0".

Bit 12: data descriptor (DD) A data descriptor indicates the attributes of data stored in ACC, and

• If DD is "1", ACC data is valid for 16 bits

• If DD is "0", ACC data is valid for the low-order 8 bits

When DD is referred to for an arithmetic instruction and data transfer instruction execution with ACC:

• the operation and transfer in word units are executed if DD is "1"

• the operation and transfer in byte units are executed if DD is "0"

DD is set to "1" or "0" when the data transfer instruction to ACC is executed, and also

set or reset when a dedicated set or reset instruction is executed.

This means that:

• DD is set to "1" when a word type load instruction to ACC is executed, and when an

SDD instruction is executed.

• DD is set to "0" when a byte type load instruction to ACC is executed, and when an

RDD instruction is executed.

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If the state of DD is changed when a load instruction to ACC or a dedicated set or

reset instruction is executed, the next instruction, if it is an instruction to refers to DD, is executed referring to the DD whose state has been changed.

Since DD is assigned to PSW, DD can also be changed by instructions other than the instructions above. In this case, if the next is an instruction to refer to DD, the state of DD to be changed is referred to in order to execute the instruction. If DD is used in this manner, insert an NOP instruction, next to the instruction that directly changes the state of DD.

Bit 11: sign flag (S)

A sign flag is set if MSB is "1", as a result of executing an arithmetic or logic instruction, and is reset if MSB is "0".

Bit 10: user flag 2 (F2) Bit 6: user flag 1 (F1) Bit 3: user flag 0 (F0)

These flags can be set to "1" or "0" depending on the instruction.

Bit 9: overflow flag (OV)

An overflow flag is set to "1" if the result of executing an arithmetic instruction exceeds the range expressed by a complement of 2 (–128 to +127 in the case of a byte operation; –32768 to +32767 in the case of a word operation), otherwise it is set to "0".

Bit 8: master interrupt enable flag (MIE)

A master interrupt enable flag controls enable ("1") and disable ("0") of an entire maskable interrupt. This flag is set to "0" after it is saved to the system stack as PSW during a maskable interrupt transition cycle, and returns by executing an RTI instruction. If MIE is set to "1", the generation of an entire maskable interrupt is enabled from the next instruction. If MIE is set to "0", an entire maskable interrupt is disabled from

the next instruction. Bit 7: sum of product operation function bank flag (MAB) Since the MSM66591/ML66592 have no sum of product operation function, MAB can

be used as a user flag. Bit 5: bank common base 1 (BCB1) Bit 4: bank common base 0 (BCB0)

Since the MSM66591/ML66592 have no bank common base function, these flags can

be used as user flags. Bit 2: system control base 2 (SCB2) Bit 1: system control base 1 (SCB1) Bit 0: system control base 0 (SCB0)

These flags specify setting the pointing register (PR) assigned to a fixed page area.

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2 1 0

Setting of Pointing

S C B

0 0 0 PR0 (0200H–0207H) 0 0 1 PR1 (0208H–020FH) 010 PR2 (0210H–0217H) 0 1 1 PR3 (0218H–021FH) 100 PR4 (0220H–0227H) 1 0 1 PR5 (0228H–022FH) 1 1 0 PR6 (0230H–0237H) 1 1 1 PR7 (0238H–023FH)

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

LRBH

LRBL

LRB

Figure 3-7 Configuration of LRB

[2] Program Counter (PC)

The PC is a 16-bit counter that holds the address information in the segment of the program to be executed next. PC is normally incremented according to the number of bytes of an instruction to-be-executed. If a branch instruction or an instruction that requires a branch is executed, immediate data, register content, etc. are loaded.

The CSR value does not change even if an overflow occurs because of an increment in PC.

At reset (when the RES signal is input, the BRK instruction is executed, the watchdog timer is overflown, or an operation code trap is generated), or when an interrupt occurs, the content of the vector table area is loaded to the PC.

[3] Local Register Base (LRB)

The LRB is a 16-bit register. The low-order 8 bits (LRBL) specifies 2K bytes of data memory space, 0200H–09FFH, in 8 byte units (local register addressing).

The high-order 8 bits (LRBH) specify 64K bytes of data memory space in 256 byte units (current page addressing). 64 bytes of the current page, xxC0H–xxFFH, is an area that SB, RB, JBR, and JBS instructions can access by specifying the sba.bit addressing. Both LRBL (02H) and LRBH (03H) are assigned to SFR, and the content is undefined at reset (when the RES signal is input, the BRK instruction is executed, the watchdog timer is overflown, or an operation code trap is generated).

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76543210

LRBL

x x x

LRBL 8 bits specify 2K bytes of data memory space, 0200H–09FFH, in 8-byte units. (Value x is included in instruction code.)

76543210

LRBH

x x x x x x x x

LRBH 8 bits specify 64K bytes of data memory space, 0000H–FFFFH, in 256-byte units. (Value x is included in instruction code.) (The area of addresses 1A00H through 1FFFH is excluded.)

• LRBL 8 bits specify 2K bytes of data memory space, 0200H–09FFH, in 8-byte units.

• LRBH 8 bits specify 64K bytes of data memory space, in 256-byte units. (The area of

addresses 1A00H through 1FFFH is excluded.)

[4] System Stack Pointer (SSP)

SSP is a 16-bit register that indicates the stack address to save or return PC, registers, etc. while handling an interrupt and executing CAL, PUSH, RT, and POP instructions. SSP is automatically incremented or decremented depending on the process to be executed.

A save or return to the stack address indicated by SSP is performed in word units, so the least significant bit (LSB) of SSP is addressed as "0".

The SFR area and expanded SFR area cannot be used as the stack. SSP (00H) is assigned to SFR, and the content becomes FFFFH at reset (when the

RES signal is input, the BRK instruction is executed, the watchdog timer is overflown, or an operation code trap is generated).

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3.2.3 Pointing Register (PR)

PR has 8 sets. 1 set consists of the following four 16-bit registers.

• index register 1 (X1)

• index register 2 (X2)

• data pointer (DP)

• user stack pointer (USP)

PR is assigned to 0200H–023FH of the internal RAM area, and one of the 8 sets is selected by SCB0–2 of PSWL.

If the PR function is not used, PR can be used as internal RAM. For all of X1, X2, DP and USP, even addresses are low-order 8 bits. The following odd

addresses are high-order 8 bits.

USP

Pointing register set

SCB = 0

SCB = 1

SCB = 7

Expanded SFR area

01FFH 0200H

0208H

0210H

0238H

0240H

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3.2.4 Local Registers (R, ER)

R is an 8-bit register, ER is a 16-bit register. R and ER specify 2K bytes of data memory space, 0200H–09FFH, in 8 byte units by the LRBL low-order 8 bits of the local register base. 1 byte of the specified 8 bytes is assigned as R by 3-bit data of a local register operation instruction. (2 bytes are assigned as ER by 2-bit data.)

ER0

R0 R1

ER1

R2 R3

ER2

R4 R5

ER3

R6 R7

ER0

R0 R1

0200H

0208H

0A00H

LRBL = 00H

LRBL = 01H

LRBL = FFH

ER3

Specified in 8 byte units by LRBL 8 bits. R0 to R7 are specified by 3 bits included in instruction code. ER0 to ER3 are specified by 2 bits included in instruction code.

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"0" "0" "0" "0" "0" "0" "0"

76543210

CSR

"0" "0" "0" "0" "0" "0"

76543210

CSR

(MSM66591)

(ML66592)

3.2.5 Segment Register

The segment register consists of two 8-bit registers: code segment register (CSR) and table segment register (TSR). It selects a segment in the program memory space. Since the program memory space of MSM66591 has only two segments, segment 0 and segment 1, only bit 0 is valid for both the CSR and the TSR. Bits 1 to 7 are fixed to "0".

Since the program memory space of ML66592 has only segments 0, 1 and 2, only bits 0 and 1 are valid for both the CSR and the TSR. Bits 2 to 7 are fixed to "0". (Do not access segment 3.)

[1] Code Segment Register (CSR)

CSR specifies the segment in the program memory space to which the program code being executed belongs. CSR is given as an independent 8-bits register, and is not assigned to the SFR area.

CSR can be reloaded by the FJ, FCAL, FRT, and RTI instructions and an interrupt. No other methods can reload CSR. Since in the MSM66591 CSR has only one valid bit while in the emulator for the MSM66591 CSR has two valid bits, specify either segment 0 or segment 1 when executing the FJ or FCAL instruction for MSM66591.

Since in the ML66592 segment 3 is not provided, specify segment 0, 1 or 2 when executing the FJ or FCAL instruction (do not access segment 3).

Each segment is assigned offset addresses of 0 through 0FFFFH. The address calculation for determining the addressing target is performed by a 16-bit offset address, and the resulting overflow and underflow are ignored, which therefore never results in change in the CSR. Similarly, a PC overflow never updates the CSR. Therefore, without the use of the CSR reloading method described above, a program execution does not progress beyond the code segment boundary. The CSR value at reset is 00H.

When an interrupt is generated after the program memory space is extended to 128K bytes (MSM66591) or 192K bytes (ML66592), the current CSR value, along with the PC, is automatically saved onto the stack. Executing the RTI instruction returns the saved value to CSR. (See Section 3.1.1, "Memory Space Expansion.")

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[2] Table Segment Register (TSR)

TSR specifies the segment (in the program memory space) to which the table data belongs. TSR is an 8-bit register which is assigned to the SFR area.

TSR can be read/written by the program. Data in the table segment can be accessed using the ROM reference instructions (LC, LCB, CMPC, and CMPCB). By executing the ROM window function, RAM addressing can be used for this table segment.

In MSM66591, only bit 0 of TSR is valid. If a read instruction is executed, "0s" are read from bits 1 to 7. Since in the MSM66591 TSR has only one valid bit while on the emulator for the MSM66591 TSR has two valid bits, be sure to write "0s" to bits 1 to 7 when writing to TSR.

In ML66592, only bits 0 and 1 of TSR are valid. If a read instruction is executed, "0s" are read from bits 2 to 7. Since in the ML66592 segment 3 is not provided, do not access segment 3. When writing to TSR, be sure to write "0s" to bits 2 to 7.

"0" "0" "0" "0" "0" "0" "0" (MSM66591)

(ML66592)

76543210

TSR

"0" "0" "0" "0" "0" "0"

76543210

TSR

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3.2.6 Special Function Register (SFR)

The SFR area is a 256-byte area of data memory space, 0000H–00FFH, and the expanded SFR area is another 256-byte area of data memory space, 0100H–01FFH.

SFR and expanded SFR are groups of registers that have special functions assigned, such as:

• mode register of various peripheral hardware

• arithmetic register (ACC)

• control registers (PSW, LRBL, LRBH, SSP) Table 3-3 shows the SFR list. The meaning of items in this list are explained below.

• Address [H] An address is expressed in hexadecimal. "✩" in the address column

indicates that there is a missing bit (nonexistent bit) in the register.

• Name Name based on the SFR function.

• Abbreviated Abbreviation of name and data address symbol in assembler.

Name Specifically SSP, LRB, LRBL, LRBH, PSW, PSWL and PSWH

become ASSP, ALRB, ALRBL, ALRBH, APSW, APSWL and APSWH respectively.

• R/W Read (R)/write (W) possibility of SFR

R/W both read and write enable R read only W write only

• 8/16-Bit 8-bit operation/16-bit operation possibility of SFR.

Operation Specify a 16-bit operation for a 16-bit operable register by an even

address. The bit operation to a 16-bit operation-only register is disabled.

8/16 both 8-bit operation and 16-bit operation enable 8 8-bit operation only 16 16-bit operation only

• Reset State Indicates content of each SFR at reset (when RES signal is

input, the BRK instruction is executed, the watchdog timer is overflown, or an operation code trap is generated).

In Table 3-3, addresses where nothing has been assigned are indicated by blank columns. Do not access them.

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[Note]

Do not perform the following operations to SFR: A. A write operation to a read-only SFR B. A read operation to a write-only SFR C. A 16-bit operation to an 8-bit operation-only SFR D. An 8-bit operation to a 16-bit operation-only SFR E. A 1-bit operation to a 16-bit operation-only SFR F. An operation to an address where register, etc. are not assigned G. An operation to the emulator use area

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Table 3-3 SFRs

0000

0011

0001 0002 0003 0004 0005 0006 0007

0008✩

0009 000A

000B✩ 000C✩

000D 000E

000F✩

0010

0012 0013

0014 0015 0016 0017 0018 0019 001A 001B 001C 001D 001E 001F 0020

0021✩

0022 0023 0024

0025✩

0026 0027 0028 0029 002A 002B

"0"

R/W

—

Standby Control Register

Stop Code Acceptor

R/W

—ROM Ready Control Register

—ROM Window Register

Undefined

FFFF

ACC

PSW

LRB

SSP

Accumulator

Program Status Word

Local Register Base

System Stack Pointer

R/W

8/16

SCI1 Status Register 00

SCI1 Transmit/Receive Buffer Register

Undefined

Port 3 Secondary Function Control Register

Port 2 Secondary Function Control Register

Port 11 Data Register

Port 10 Data Register

Port 9 Data Register

Port 8 Data Register

Port 7 Data Register

Port 6 Data Register

Port 5 Data Register

Port 4 Data Register

Port 3 Data Register

Port 2 Data Register

Port 1 Data Register

Port 0 Data Register

S1STAT

S1BUF

P3SF

P2SF

P11

P10

SCI0 Receive Buffer Register 1 Undefined

SCI0 Transmit/Receive Buffer Register 0

Undefined

S0BUF2

S0BUF1

Port 9 Secondary Function Control Register

Port 8 Secondary Function Control Register

P9SF

P8SF

Port 10 Secondary Function Control Register

P12

P10SF

Port 7 Secondary Function Control Register

Port 6 Secondary Function Control Register

P7SF

P6SF

Port 5 Secondary Function Control Register

Port 4 Secondary Function Control Register

P5SF

P4SF

SCI0 Receive Buffer Register 3 Undefined

SCI0 Receive Buffer Register 2 Undefined

S0BUF3

SBYCON

STPACP

ROMRDY

ROMWIN

ACCH

ACCL

PSWH

PSWL

LRBH

LRBL

—

Table Segment Register

00—TSR

R/W

— — —

—

— — — — — — — — — — — — — — — — — — — — — — —

S0BUF0

Port 12 Data Register

R/W

Address [H]

Name

Abbreviated

Name (BYTE)

R/W

8/16-Bit

Operation

Reset

State [H]

Abbreviated

Name (WORD)

Addresses in the address column marked by "✩" indicate that the register has bits missing.

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Table 3-3 SFRs (continued)

0041

0031 0032 0033 0034 0035 0036 0037 0038

0039✩

003A

003B✩

003C

003D✩

003E

003F✩

0040

0042 0043

0044✩

0045 0046 0047 0048 0049

004A✩

004B 004C 004D

004E✩

004F 0050 0051 0052 0053 0054 0055

Stop

TRNSIT

GTINTCON

WDT

IE2L

IE1H

IE1L

General-Purpose 8-Bit Timer Interrupt Control Register

Watchdog Timer

Interrupt Enable Register 2

Interrupt Enable Register 1

R/W

(*1)

00S3STAT0

C0IRQ2L

Interrupt Request Register 2

R/W

IRQ1L

IRQ0H

IRQ0L

Undefined

S4BUF3

S4BUF2

S4BUF0

S3BUF3

S3BUF2

SCI4 Receive Buffer Register 2

SCI4 Transmit/Receive Buffer Register 0

R/W

00 00

01 00 01

IRQ1H

IE0L IE0H

SR3INT

S4STAT0

SR4INT

Interrupt Request Register 1

Interrupt Enable Register 0

SCI3 Status Register 0

SCI4 Status Register 0

Interrupt Request Register 0

SCI4 Receive Buffer Register 3

Undefined

S3BUF1

SCI3 Receive Buffer Register 3

SCI3 Receive Buffer Register 2

SCI3 Receive Buffer Register 1

—

PWC0/

PWC0BF

IE1

—

IRQ1

IRQ0

—

IE0

—

0030

UndefinedS4BUF1SCI4 Receive Buffer Register 1 —

S2STAT0

SR0INT

SCI0 Interrupt Control Register SCI2 Status Register 0 —

—

00S0STAT0SCI0 Status Register 0 —

FFFF—

PWM Counter 0/ PWC0 Buffer Register

FFFF—

SCI3 Transmit/Receive Buffer Register 0

S3BUF0 Undefined— R/W

01SR2INT

SCI2 Interrupt Control Register

—

SCI3 Interrupt Control Register

— — —

R/W

SCI4 Interrupt Control Register

8/16

—

R/W

Transition Detector

PWC1/

PWC1BF

PWM Counter 1/ PWC1 Buffer Register

PWC2/

PWC2BF

PWM Counter 2/ PWC2 Buffer Register

R/W

—

Address [H]

Name

Abbreviated

Name (BYTE)

R/W

8/16-Bit

Operation

Reset

State [H]

Abbreviated

Name (WORD)

Addresses in the address column marked by "✩" indicate that the register has bits missing.

002C 002D 002E 002F

S2BUF0

SCI2 Receive Buffer Register 1 Undefined

SCI2 Transmit/Receive Buffer Register 0

Undefined

S2BUF2

S2BUF1

S2BUF3

— — — —

SCI2 Receive Buffer Register 2 SCI2 Receive Buffer Register 3

R/W

Undefined

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Chapter 3 CPU Architecture

Table 3-3 SFRs (continued)

0061

0060

FFFF—

PWM Counter 8/

PWC8 Buffer Register 0062 0063 0064 0065 0066 0067 0068 0069 006A 006B 006C 006D 006E 006F 0070 0071 0072 0073 0074

0000

0075 0076

0000

0077 0078

0000

0079 007A

0000

007B 007C

0000

007D 007E

0000

007F 0080

0081✩

PWC8/

PWC8BF

FFFF—

0000—

—

0000

PWRUNL

PWMRUN Register PWRUN

PWM Counter 9/

PWC9 Buffer Register

PWC9/

PWC9BF PWM Counter 10/ PWC10 Buffer Register

PWC10/

PWC10BF PWM Counter 11/ PWC11 Buffer Register

PWC11/

PWC11BF PWM Register 0/

PWR0 Buffer Register

PWR0/ PW0BF

PWM Register 1/ PWR1 Buffer Register

PWR1/ PW1BF

PWM Register 2/ PWR2 Buffer Register

PWR2/ PW2BF

PWM Register 3/ PWR3 Buffer Register

PWR3/ PW3BF

PWM Register 4/ PWR4 Buffer Register

PWR4/ PW4BF

PWM Register 5/ PWR5 Buffer Register

PWR5/ PW5BF

PWM Register 6/ PWR6 Buffer Register

PWR6/ PW6BF

PWM Register 7/ PWR7 Buffer Register

PWR7/ PW7BF

PWM Register 8/ PWR8 Buffer Register

PWR8/ PW8BF

PWM Register 9/ PWR9 Buffer Register

PWR9/ PW9BF

PWM Register 10/ PWR10 Buffer Register

PWR10/

PW10BF

PWM Register 11/ PWR11 Buffer Register

PWR11/

PW11BF

PWRUNH

R/W

(*2)

Address [H]

Name

Abbreviated

Name (BYTE)

R/W

8/16-Bit

Operation

Reset

State [H]

Abbreviated

Name (WORD)

Addresses in the address column marked by "✩" indicate that the register has bits missing.

0056 0057 0058 0059 005A 005B 005C 005D 005E

R/W

(*1)

FFFF—

PWC3/

PWC3BF

PWM Counter 3/ PWC3 Buffer Register

PWC4/

PWC4BF

PWM Counter 4/ PWC4 Buffer Register

PWC5/

PWC5BF

PWM Counter 5/ PWC5 Buffer Register

PWC6/

PWC6BF

PWM Counter 6/ PWC6 Buffer Register

PWC7/

PWC7BF

PWM Counter 7/ PWC7 Buffer Register

005F

8/16R/W

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Table 3-3 SFRs (continued)

0091

0090

Undefined—

0092 0093 0094 0095 0096 0097 0098 0099 009A 009B 009C 009D 009E 009F 00A0 00A1 00A2 00A3 00A4

0000

00A5 00A6

Undefined

00A7 00A8

Undefined

00A9 00AA

0000

00AB 00AC

0000

00AD

TMR3

0000— TMR4

0000— TMR5

0000— TMR6

0000— TMR7

0000— TMR8

0000— TMR9

0000— TMR10

— TMR11

— TMR12

— TMR13

— TMR14

— TMR15

— TMR16

— TMR17

0000

R/W

Timer Register 3

Timer Register 4

Timer Register 5

Timer Register 6

Timer Register 7

Timer Register 8

Timer Register 9

Timer Register 10

Timer Register 11

Timer Register 12

Timer Register 13

Timer Register 14

Timer Register 15

Timer Register 16

Timer Register 17

Address [H]

Name

Abbreviated

Name (BYTE)

R/W

8/16-Bit

Operation

Reset

State [H]

Abbreviated

Name (WORD)

Addresses in the address column marked by "✩" indicate that the register has bits missing.

0082

0083✩

0084

0085✩

0086

0087✩

0088

0089✩

008A 008B 008C 008D 008E 008F

PWM Interrupt Register 0 PWINTQ0

PWM Interrupt Register 1 PWINTQ1

PWM Interrupt Enable Register 0

PWINTE0

PWM Interrupt Enable Register 1

PWINTE1

Undefined

—Timer Register 0 TMR0

Undefined

—Timer Register 1 TMR1

Undefined

—Timer Register 2 TMR2

R/W

PWINTQ0L

PWINTQ0H

PWINTQ1L

PWINTQ1H

PWINTE0L

PWINTE0H

PWINTE1L

PWINTE1H

8/16

R/W

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Chapter 3 CPU Architecture

Table 3-3 SFRs (continued)

00C1

0000

00C0

0000

—TMR13 Buffer Register

00C2

—Timer Setting Register

00C3

00C4✩

00C5

00C6✩ F8 00C7✩ 00C8✩

R/W

00C9✩ 00CA✩ 00CB✩ 00CC✩ 00CD✩ 00CE✩ 00CF✩ 00D0✩ 00D1✩

00D2

00D3✩

00D4 00D5 00D6 00D7

—Timer Counter 0

TMR13BF

TMSEL

TM0

RTOCON4RTO Control Register 4 —

TMSEL2Timer Setting Register 2 —

RTOCON5RTO Control Register 5 —

RTOCON6RTO Control Register 6 —

RTOCON7RTO Control Register 7 —

RTOCON8RTO Control Register 8 —

RTOCON9RTO Control Register 9 —

RTOCON10RTO Control Register 10 —

RTOCON11RTO Control Register 11 —

RTOCON12RTO Control Register 12 —

RTOCON13RTO Control Register 13 —

RTOCON16RTO Control Register 16 —

RTOCON17RTO Control Register 17 —

RTO4CON4-Port RTO Control Register —

TM0L

Timer Counter 0 Low-Order 4 Bits

—

0000

—Timer Counter 1 TM1

Address [H]

Name

Abbreviated

Name (BYTE)

R/W

8/16-Bit

Operation

Reset

State [H]

Abbreviated

Name (WORD)

Addresses in the address column marked by "✩" indicate that the register has bits missing.

00AE

0000

00AF 00B0 00B1 00B2 00B3 00B4 00B5 00B6 00B7 00B8 00B9 00BA 00BB 00BC 00BD 00BE 00BF

—TMR4 Buffer Register TMR4BF

0000

— TMR5BF

0000

— TMR6BF

0000

— TMR7BF

0000

— TMR8BF

0000

— TMR9BF

0000

— TMR10BF

0000

— TMR11BF

0000

— TMR12BF

R/W

TMR5 Buffer Register

TMR6 Buffer Register

TMR7 Buffer Register

TMR8 Buffer Register

TMR9 Buffer Register

TMR10 Buffer Register

TMR11 Buffer Register

TMR12 Buffer Register

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Table 3-3 SFRs (continued)

00F1

00F0 Undefined

—A/D Result Register 12

R/W

(*3)

00F2 00F3 00F4 00F5 00F6 00F7 00F8 00F9 00FA 00FB

00FC✩ 00FD✩ 00FE✩

00FF✩

ADCR12

Undefined—A/D Result Register 13

ADCR13

Undefined—A/D Result Register 14

ADCR14

Undefined—A/D Result Register 15

ADCR15

Undefined—A/D Result Register 16

ADCR16

Undefined—A/D Result Register 17

ADCR17

Undefined—A/D Result Register 18

ADCR18

Undefined—A/D Result Register 19

ADCR19

Undefined—A/D Result Register 20

ADCR20

Undefined—A/D Result Register 21

ADCR21

Undefined—A/D Result Register 22

ADCR22

Undefined—A/D Result Register 23

ADCR23

80ADCON1LA/D1 Control Register L

—

80ADCON1HA/D1 Control Register H

—

C0ADINTCON1

A/D Interrupt Control Register 1

—

FCADHSCON

A/D Hard Select Software Control Register

—

R/W

Address [H]

Name

Abbreviated

Name (BYTE)

R/W

8/16-Bit

Operation

Reset

State [H]

Abbreviated

Name (WORD)

Addresses in the address column marked by "✩" indicate that the register has bits missing.

00D8

00D9 00DA 00DB 00DC

00DD✩ 00DE✩ 00DF✩

Undefined

00E0 00E1 00E2 00E3 00E4 00E5 00E6 00E7 00E8

TMR0LTMR0 Low-Order 4 Bits

00E9 00EA 00EB

00EC✩ 00ED✩

R/W

(*3)

00EE✩

—A/D Result Register 0

00EF

—

ADCR0

Undefined

TMCONTimer Control Register EVNTCON2Event Control Register 2 EVNTCONLEvent Control Register L

— — —

EVNTCONHEvent Control Register H —

Undefined

TMR1LTMR1 Low-Order 4 Bits

—

Undefined

TMR2LTMR2 Low-Order 4 Bits

—

Undefined

TMR3LTMR3 Low-Order 4 Bits —

00 88 88 88

R/W

—A/D Result Register 1 ADCR1

Undefined

—A/D Result Register 2 ADCR2

Undefined

—A/D Result Register 3 ADCR3

Undefined

—A/D Result Register 4 ADCR4

Undefined

—A/D Result Register 5 ADCR5

Undefined

—A/D Result Register 6 ADCR6

Undefined

—A/D Result Register 7 ADCR7

Undefined

—A/D Result Register 8 ADCR8

Undefined

—A/D Result Register 9 ADCR9

Undefined

—A/D Result Register 10 ADCR10

Undefined

—A/D Result Register 11 ADCR11

Undefined

ADCON0LA/D0 Control Register L —

ADCON0HA/D0 Control Register H —

ADINTCON0

A/D Interrupt Control Register 0

—

ADHENCON

A/D Hard Select Enable

—

R/W

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Chapter 3 CPU Architecture

*1 Indicates that the R/W operation of the PWM counter/buffer is a special operation.

When a read operation is performed, the value of the PWM counter (PWMCn) is read. When a write operation is performed, data is written to the PCM buffer register (PWCnBF).

*2 Indicates that the R/W operation of the PWM register/buffer is a special operation.

When a read operation is performed, the value of the PWM register (PWRn) is read. When a write operation is performed, data is written to the PWR buffer register (PWnBF).

*3 Indicates that the R/W operation of ADCR is a special operation.

ADCR is divided into the groups of: ADCR0, 2, 4, 6, 8, 10; ADCR1, 3, 5, 7, 9, 11; ADCR12, 14, 16, 18, 20, 22; and ADCR13, 15, 17, 19, 21, 23. Data can be written simultaneously to each of these groups. Writing to ADCR0 simultaneously writes to ADCR0, 2, 4, 6, 8, and 10. Writing to ADCR1 simultaneously writes to ADCR1, 3, 5, 7, 9, and 11. Writing to ADCR12 simultaneously writes to ADCR12, 14, 16, 18, 20, and 22. Writing to ADCR13 simultaneously writes to ADCR13, 15, 17, 19, 21, and 23.

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Expanded SFR Area

0101✩ FCMEMSCONMemory Size Control Register

0100 "0"

MEMSACPMemory Size Acceptor

R/W

0102 0103 0104

0105✩

0106

0107✩

0108

0109✩ C0EXICON

External Interrupt Control Register 010A 010B

010C 010D 010E 010F

F8 or 78PRPHFPeripheral Control Register

—

0110 0111 0112 0113 0114 0115 0116 0117 0118 0119 011A

011C✩

011B

011D

011E✩ 011F✩

0120 0121 0122 0123 0124 0125 0126 0127 0128 0129

012A✩ 012B✩

—

R/W

F0TBCKDVCTBC Clock Dividing Counter F0

TBCKDVR

— —

TBC Clock Dividing Register

R/W

FEWDTCONWatchdog Control Register

— R/W

R/W

00P0IOPort 0 Mode Register

—

00P1IOPort 1 Mode Register

—

00P2IOPort 2 Mode Register

—

00P3IOPort 3 Mode Register

—

00P4IOPort 4 Mode Register

—

00P5IOPort 5 Mode Register

—

00P6IOPort 6 Mode Register

—

00P7IOPort 7 Mode Register

—

00P8IOPort 8 Mode Register

—

00P9IOPort 9 Mode Register

—

00P10IOPort 10 Mode Register

—

00P11IOPort 11 Mode Register

—

00P12IOPort 12 Mode Register

—

R/W

0000

— S0TM

SCI0 Timer

0000

— S1TM

SCI1 Timer

0000

— S2TM

SCI2 Timer

0000

— S3TM

SCI3 Timer

0000

— S4TM

SCI4 Timer

02S0CONSCI0 Timer Control Register — 02S1CONSCI1 Timer Control Register —

Address [H]

Name

Abbreviated

Name (BYTE)

R/W

8/16-Bit

Operation

Reset

State [H]

Abbreviated

Name (WORD)

Addresses in the address column marked by "✩" indicate that the register has bits missing.

R/W

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Expanded SFR Area (continued)

0131✩

0130✩ 8AST0CON

SCI0 Transmit Control Register

0132✩ 0133✩ 0134✩

0135 0136 0137

0138✩ 0139✩ 013A✩ 013B✩ 013C✩

013D 013E 013F

—

0140 0141 0142 0143 0144 0145 0146 0147

0148✩ 0149✩ 014A✩

014C

014B

014D 014E 014F 0150 0151 0152 0153

0154✩

0155 0156 0157

00IP00L

Interrupt Priority Register 00

IP00

00IP00H

C0IP20LInterrupt Priority Register 20 — C0IP21LInterrupt Priority Register 21

—

3C or BCNMICONNMI Control Register

—

8/16

R/W

IRQD0

Interrupt Request Flag

Disable Register 0

88ST1CON

SCI1 Transmit Control Register

—

8AST2CON

SCI2 Transmit Control Register

— R/W

8AST3CON

SCI3 Transmit Control Register

—

8AST4CON

SCI4 Transmit Control Register

—

12SR0CONSCI0 Receive Control Register

—

08SR1CONSCI1 Receive Control Register

—

12SR2CONSCI2 Receive Control Register

—

12SR3CONSCI3 Receive Control Register

—

12SR4CONSCI4 Receive Control Register

—

R/W

00IP01L

Interrupt Priority Register 01

IP01

00IP01H 00IP10L

Interrupt Priority Register 10

IP10

00IP10H 00IP11L

Interrupt Priority Register 11

IP11

00IP11H

00IRQD0L 00IRQD0H

IRQD1

Interrupt Request Flag

Disable Register 1

00IRQD1L 00IRQD1H

8/16

C0IRQD2L

Interrupt Request Flag Disable Register 2

—

R/W

Address [H]

Name

Abbreviated

Name (BYTE)

R/W

8/16-Bit

Operation

Reset

State [H]

Abbreviated

Name (WORD)

Addresses in the address column marked by "✩" indicate that the register has bits missing.

012C✩ 012D✩ 012E✩

012F

02S2CONSCI2 Timer Control Register — 02S3CONSCI3 Timer Control Register — 02S4CONSCI4 Timer Control Register —

R/W

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Expanded SFR Area (continued)

0161

0160 00PWCON0PWM Control Register 0

0162 0163 0164 0165 0166 0167 0168 0169

016A✩

016B 016C 016D 016E 016F

—

0170✩ 0171✩ 0172✩ 0173✩ 0174✩ 0175✩ 0176✩ 0177✩ 0178✩ 0179✩ 017A✩

017C

017B✩

017D

017E✩

017F 0180 0181 0182 0183

— —

R/W

— —

30GTMCON

General-Purpose 8-Bit Timer Control Register

—

00GEVC

General-Purpose 8-Bit Event Counter

—

00GTMC

General-Purpose 8-Bit Timer Counter

—

R/W

00PWCON1PWM Control Register 1 00PWCON2PWM Control Register 2 00PWCON3PWM Control Register 3 00PWCON4PWM Control Register 4 00PWCON5PWM Control Register 5

00GTMR

General-Purpose 8-Bit Timer Register

—

0000—TRNS Control Register

TRNSCON

R/W

C0EVDV0Event Dividing Counter 0

—

C0EVDV1Event Dividing Counter 1

—

C0EVDV2Event Dividing Counter 2

—

C0EVDV3Event Dividing Counter 3

—

C0EVDV14Event Dividing Counter 14

—

C0EVDV15Event Dividing Counter 15

—

C0EVDV0BFEVDV0 Buffer Register

—

C0EVDV1BFEVDV1 Buffer Register

—

C0EVDV2BFEVDV2 Buffer Register

—

C0EVDV3BFEVDV3 Buffer Register

—

C0EVDV14BFEVDV14 Buffer Register

—

C0EVDV15BFEVDV15 Buffer Register

—

0000—Capture Control Register

CAPCON

R/W

F2TMRMODETMR Mode Register

—

Address [H]

Name

Abbreviated

Name (BYTE)

R/W

8/16-Bit

Operation

Reset

State [H]

Abbreviated

Name (WORD)

Addresses in the address column marked by "✩" indicate that the register has bits missing.

0158 0159 015A 015B 015C 015D 015E

0000

— ADHSEL0

A/D Hardware Select Register 0

0000

— ADHSEL1

A/D Hardware Select Register 1

R/W

015F

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Expanded SFR Area (continued)

0191✩

0190✩ 11

S0STAT1SCI0 Status Register 1

R/W

0192✩ 0193✩ 0194✩ 0195✩ 0196✩ 0197✩

0198 0199 019A 019B 019C 019D 019E 019F

—

C1S0STAT2SCI0 Status Register 2

—

11S2STAT1SCI2 Status Register 1

—

C1S2STAT2SCI2 Status Register 2

—

11S3STAT1SCI3 Status Register 1

—

C1S3STAT2SCI3 Status Register 2

—

11S4STAT1SCI4 Status Register 1

—

C1S4STAT2SCI4 Status Register 2

—

Address [H]

Name

Abbreviated

Name (BYTE)

R/W

8/16-Bit

Operation

Reset

State [H]

Abbreviated

Name (WORD)

Addresses in the address column marked by "✩" indicate that the register has bits missing.

0185 0186 0187 0188

0189✩

018A 018B

018C✩

018D 018E 018F

C0SIO5CON1SIO5 Control Register 1

—

00SFADRSerial Address Output Register

—

R/W

UndefinedSFDINSerial Data Input Register

—

UndefinedSFDOUTSerial Data Output Register

—

1FSIO5INTSIO5 Interrupt Control Register

—

R/W

Expansion Port Data Register

F8EXTPCON

Expansion Port Control Register L

—

R/W

00EXTPDL 00—

EXTPD

R/W

8/16

0184✩

10SIO5CON0SIO5 Control Register 0

—

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* 4 The initial values of PRPHF (SFR = 107H) are as follows:

At reset by RES pin: VBFF (bit 6) is "1"; CKOUT2 (bit 2), CKOUT1 (bit 1) and CKOUT0 (bit 0) are "0". At reset by WDT and BRK instructions and operation code trap: VBFF (bit 6) holds the value just before reset; CKOUT2 (bit 2), CKOUT1 (bit 1) and CKOUT0 (bit 0) are "0". In both cases, the OE pin status is read for OERD (bit 7).

* 5 The flash control register area is used exclusively for the MSM66Q591/ML66Q592

(Flash EEPROM version product). For details, refer to the "MSM66Q591 Flash Memory User's Manual" or "ML66Q592 Flash Memory User's Manual".

*6 Do not access the emulator use area.

01F1

01F0

01F2 01F3 01F4 01F5 01F6 01F7 01F8

01F9 01FA 01FB

01FC 01FD

01FE

01FF

Flash Memory Control Register Area (*5)

Emulator Use Area (*6)

Address [H]

Name

Abbreviated

Name (BYTE)

R/W

8/16-Bit

Operation

Reset

State [H]

Abbreviated

Name (WORD)

Addresses in the address column marked by "✩" indicate that the register has bits missing.

Expanded SFR Area (continued)

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Chapter 3 CPU Architecture

3.3 Addressing Mode

The MSM66591/ML66592 have two independent memory spaces: data memory space and program memory space. MSM66591/ML66592 addressing mode is divided into two, corresponding to each space.

Data memory space is referred to as "RAM space," since the space normally consists of random access memory (RAM). Addressing to this space is referred to as "RAM addressing."

Program memory space is referred to as "ROM space," since the space normally consists of read only memory (ROM). Addressing to this space is referred to as "ROM addressing."

ROM addressing is classified into immediate addressing to an instruction code, table addressing to data or ROM space (normally read-only data), and program code addressing to a program in ROM space.

ROM window addressing is unique to MSM66591/ML66592. This involves accessing the table data in ROM space using the above RAM addressing formats. Data in a table segment is read via the window on a data segment opened by a program. See Chapter 5, "Memory Control Functions."

3.3.1 RAM Addressing

RAM addressing modes specify addressing of program variables in RAM space. Addressing modes provided are register addressing, page addressing, direct addressing, pointing register indirect addressing, and special bit area addressing.

Access to the area from 1A00H to FFFFH in the RAM space of MSM66591 and from 2200H to FFFFH in the RAM space of ML66592 is inhibited since it is not located in internal RAM. However, the ROM window setting area (MSM66591: 2000H–FFFFH, ML66592: 3000H–FFFFH) can be accessed only if the ROM window has been set. Any access is inhibited to the area where the ROM window function has not been set.

[1] Register Addressing

A. Accumulator Addressing: A B. Control Register Addressing: PSW, LRB, SSP C. Pointing Register Addressing: X1, X2, DP, USP D. Local Register Addressing: ERn, Rn

A. Accumulator Addressing Word instructions access the accumulator contents (A). Byte instructions access the

low byte of the accumulator (AL). [Word Type]

L A, #1234H ST A, VAR

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[Byte Type]

LB A, #12H STB A, VAR

[Bit Type]

MB C, A.3 JBS A.3, LABEL

B. Control Register Addressing Register contents are accessed.

SSP: system stack pointer LRB: local register base PSW: program status word PSWH: program status word high-order byte PSWL: program status word low-order byte C: carry flag

[Word Type]

FILL SSP MOV LRB, #401H CLR PSW

[Byte Type]

CLRB PSWH INCB PSWL

[Bit Type]

MB C, BITVAR

C. Pointing Register Addressing Pointing register contents are accessed. Pointing registers are provided with eight sets

of registers (PR0–PR7: every 8-byte block in 200H–23FH in data memory), but the set addressed in this mode is specified by the System Control Base (SCB) field in PSW.

X1: index register 1 X2: index register 2 DP: data pointer USP: user stack pointer X1L: index register 1 low-order byte X2L: index register 2 low-order byte

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DPL: data pointer low-order byte DP*: data pointer low-order byte USPL: user stack pointer low-order byte

*This register can be used only for [JRNZ DP, radr] instruction which is provided for compatibility with nX-8/100 to nX-8/400 CPU core.

[Word Type]

L A, X1 ST A, X2 MOV DP, #2000H CLR USP

[Byte Type]

DJNZ X1L, LOOP DJNZ X2L, LOOP DJNZ DPL, LOOP DJNZ USPL, LOOP

JRNZ DP, LOOP D. Local Register Addressing Local register contents are accessed. Local registers are 256 sets of registers (every

8-byte block in 200H–9FFH in data memory), but the set addressed in this mode is specified by the Local Register Base (LCB) low-order byte.

ER0–ER3: expanded local registers

R0–R7: local registers

[Word Type]

L A, ER0

MOV ER2, ER1

CLR ER3 [Byte Type]

LB A, R0

ADDB R1, A

CMPB R2, #12H

INCB R3

ROR R4

MOVB R5, R6 [Bit Type]

SB R0.0

RB R1.7

JBRS R7.3, LABEL

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[2] Page Addressing

A. SFR Page Addressing: sfr Dadr B. FIXED Page Addressing: fix Dadr C. Current Page Addressing: off Dadr

A. SFR Page Addressing SFR page addressing specifies an offset in the SFR page (0–0FFH in data memory)

with one byte of instruction code. Word, byte, or bit data can be accessed at the specified address.

The operand is coded with the "sfr" addressing specifier. The "sfr" can be omitted, but then SFR page addressing will only be used when the assembler recognizes that an address is in the SFR page.

Every microcontroller device has its particular SFR symbols (abbreviated names). Normally these symbols are used for SFR accesses.

If an odd address is specified, then the word data starting at the next lower even address will be accessed (see "Word Operation"). However, there are exceptions depending on the SFR.

RAM

0000H

00xxH

00FFH

SFR Page

[Word Type]

L A, sfr P0

L A, P0

RAM

SFR Page

[Byte Type]

LB A, sfr P0

LB A, P0

0000H

00xxH

00FFH

RAM

SFR Page

[Bit Type]

SB sfr P0_3

SB P0_3

0000H

00xxH

00FFH

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0200H

02xxH

02FFH

FIXED Page

RAM

0200H

02xxH

02FFH

FIXED Page

[Word Type]

L A, fix FIX_VAR

L A, FIX_VAR

0200H

02xxH

02FFH

FIXED Page

SB fix FIX_VAR.3

SB FIX_VAR.3

RAM

[Byte Type]

LB A, fix FIX_VAR

LB A, FIX_VAR

RAM

[Bit Type]

B. FIXED Page Addressing FIXED page addressing specifies an offset in the FIXED page (200H–2FFH in data

memory) with one byte of instruction code. Word, byte, or bit data can be accessed at the specified address.

The operand is coded with the "fix" addressing specifier. The "fix" can be omitted, but then FIXED page addressing will only be used when the assembler recognizes that an address is in the FIXED page.

If an odd address is specified, then the word data starting at the next lower even address will be accessed (see "Word Operation").

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C. Current Page Addressing Current page addressing specifies an offset in the current page (one of 256 pages in

data memory specified by LRBH) with one byte of instruction code (excluding access inhibit area). Word, byte, or bit data can be accessed at the specified address.

The operand is coded with the "off" addressing specifier. The "off" can be replaced by "\", but this will have a slightly different meaning when bit data in the SBA area is accessed (see "sbaoff Badr").

If an odd address is specified, then the word data starting at the next lower even address will be accessed (see "Word Operation").

xx00H

xxxxH

xxFFH

Current page

xx00H

xxxxH

xxFFH

Current page

RAM

xx00H

xxxxH

xxFFH

Current page

[Word Type]

L A, off VAR

L A, \VAR

SB off VAR.3

SB \ VAR.3

RAM

[Byte Type]

LB A, off VAR

LB A, \VAR

RAM

[Bit Type]

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0000H

xxxxH

FFFFH

64K bytes

0000H

xxxxH

FFFFH

64K bytes

RAM

0000H

xxxxH

FFFFH

64K bytes

[Word Type]

L A, dir VAR

L A, VAR

SB dir VAR.3

SB VAR.3

RAM

[Byte Type]

LB A, dir VAR

LB A, VAR

RAM

[Bit Type]

[3] Direct Data Addressing: dir Dadr

Direct page addressing specifies an address in the current physical segment of data memory (address 0–0FFFFH: 64K bytes) with two bytes of instruction code (excluding access inhibit area). Word, byte, or bit data can be accessed at the specified address.

The operand is coded with the "dir" addressing specifier. The "dir" can be omitted, but then if an address in the SFR page or FIXED page is specified then the assembler may interpret it as SFR page addressing or FIXED page addressing.

If an odd address is specified, then the word data starting at the next lower even address will be accessed (see "Word Operation").

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0000H

xxxxH

FFFFH

64K bytes

0000H

xxxxH

FFFFH

64K bytes

RAM

0000H

xxxxH

FFFFH

64K bytes

[Word Type]

L A, [DP]

L A, [X1]

RAM

[Byte Type]

RAM

[Bit Type]

DP or X1

LB A, [DP]

LB A, [X1]

DP or X1

SB [DP].3 RB [X1].3

DP or X1

[4] Pointing Register Indirect Addressing

A.DP/X1 Indirect Addressing: [DP],[X1] B.DP Indirect Addressing with Post-Increment: [DP+] C.DP Indirect Addressing with Post-Decrement: [DP–] D.DP/USP Indirect Addressing with 7-Bit Displacement: n7[DP],n7[USP] E.X1/X2 Indirect Addressing with 16-Bit Base: D16[X1],D16[X2] F. X1 Indirect Addressing with 8-Bit Register Displacement: [X1+R0],[X1+A]

A. DP/X1 Indirect Addressing DP/X1 indirect addressing specifies an address in the current physical segment (ad-

dress 0–0FFFFH: 64K bytes) by the contents of a pointing register (excluding access inhibit area). Word, byte, or bit data can be accessed at the specified address.

[DP]: DP Indirect Addressing [X1]: X1 Indirect Addressing

If an odd address is specified, then the word data starting at the next lower even address will be accessed (see "Word Operation").

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L B A, [DP+]

Incremented by 1 after access

0000H

xxxxH

FFFFH

64K bytes

0000H

xxxxH

FFFFH

64K bytes

RAM

0000H

xxxxH

FFFFH

64K bytes

[Word Type]

L A, [DP+]

RAM

[Byte Type]

RAM

[Bit Type]

SB [DP+].3

Incremented by 2 after access

Incremented by 1 after access

B. DP Indirect Addressing with Post-Increment DP indirect addressing with post-increment specifies an address in the current physical

segment (address 0–0FFFFH: 64K bytes) by the contents of a pointing register (excluding access inhibit area). Word, byte, or bit data can be accessed at the specified address.

After access, the pointing register contents will be incremented. The increment will be 2 for word instructions and 1 for byte and bit instructions. This mode is primarily used to access consecutive array elements.

[DP+]: DP indirect addressing with post-increment

If an odd address is specified, then the word data starting at the next lower even address will be accessed (see "Word Operation").

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L B A, [DP–]

Decremented by 1 after access

0000H

xxxxH

FFFFH

64K bytes

0000H

xxxxH

FFFFH

64K bytes

RAM

0000H

xxxxH

FFFFH

64K bytes

[Word Type]

L A, [DP–]

RAM

[Byte Type]

RAM

[Bit Type]

SB [DP–].3

Decremented by 2 after access

Decremented by 1 after access

C. DP Indirect Addressing with Post-Decrement DP indirect addressing with post-decrement specifies an address in the current physical

segment of data memory (address 0–0FFFFH: 64K bytes) by the contents of a pointing register (excluding access inhibit area). Word, byte, or bit data can be accessed at the specified address.

After access, the pointing register contents will be decremented. The decrement will be 2 for word instructions and 1 for byte and bit instructions. This mode is primarily used to access consecutive array elements.

[DP–]: DP indirect addressing with post-decrement

If an odd address is specified, then the word data starting at the next lower even address will be accessed (see "Word Operation").

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RAM

0000H

xxxxH

FFFFH

64K bytes

L A,12[DP]

L A,12[USP]

[Word Type]

DP or USP

RAM

0000H

xxxxH

FFFFH

64K bytes

LB A,12[DP]

LB A,12[USP]

[ByteType]

DP or USP

RAM

0000H

xxxxH

FFFFH

64K bytes

[Bit Type]

DP or USP

12[DP].3

12[USP].3

D. DP/USP Indirect Addressing with 7-Bit Displacement DP/USP indirect addressing with 7-bit displacement specifies an address in the current

physical segment (address 0–0FFFFH: 64K bytes) using the contents of a pointing register as a base and adding a 7-bit displacement with sign embedded in instruction code (bits 6–0; bit 6 is a signed bit) (excluding access inhibit area). The range –64 to +63 bytes around the pointing register value can be accessed. Word, byte, or bit data can be accessed at the specified address.

numeric_expression

[DP] : DP indirect addressing with 7-bit displacement

numeric_expression

[USP] : USP indirect addressing with 7-bit displacement

The

numeric_expression

is a value in the range –64 to +63. DP and USP can be used

as the pointing register.

If an odd address is specified, then the word data starting at the next lower even address will be accessed (see "Word Operation").

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RAM

0000H

xxxxH

FFFFH

64K bytes

L A,1234H[X1]

ST A,1234H[X2]

[Word Type]

X1 or X2

RAM

0000H

xxxxH

FFFFH

64K bytes

LB A,1234H[X1]

STB A,1234H[X2]

[ByteType]

X1 or X2

RAM

0000H

xxxxH

FFFFH

64K bytes

[Bit Type]

X1 or X2

1234H[X1].3

1234H[X2].3

E. X1/X2 Indirect Addressing with 16-Bit Base X1/X2 indirect addressing with 16-bit base specifies a 2-byte (D16) base embedded in

instruction code and adds it to the contents of an index register (X1 or X2) to obtain an address in the current physical segment (address 0–0FFFFH: 64K bytes). Word (16bit) calculations are used to generate the address, with overflows ignored. Therefore the generated address will be 0–0FFFFH. Word, byte, or bit data can be accessed at the specified address.

address_expression

[X1] : X1 indirect addressing with 16-bit base

address_expression

[X2] : X2 indirect addressing with 16-bit base

The

address_expression

is a value in the range 0–0FFFFH. However, the assembler allows a value in the range of –8000H to +0FFFFH. That is, D16 can also be thought of as a displacement instead of a base address.

If an odd address is specified, then the word data starting at the next lower even address will be accessed (see "Word Operation").

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If an odd address is specified, then the word data starting at the next lower even address will be accessed (see "Word Operation").

RAM

0000H

xxxxH

FFFFH

64K bytes

L A, [X1+A]

L A, [X1+R0]

[Word Type]

RAM

0000H

xxxxH

FFFFH

64K bytes

[ByteType]

RAM

0000H

xxxxH

FFFFH

64K bytes

[Bit Type]

AL or R0

LB A, [X1+A]

LB A, [X1+R0]

AL or R0

SB [X1+A].3

RB [X1+R0].3

F. X1 Indirect Addressing with 8-Bit Register Displacement X1 indirect addressing with 8-bit register displacement specifies an address in the

current physical segment (address 0–0FFFFH: 64K bytes) using the contents of a pointing register as a base and adding the contents of the Accumulator low byte (AL) or Local Register 0 (R0) (excluding access inhibit area). Word (16-bit) calculations are used to generate the address. The 8-bit displacement obtained from the register will be extended without sign, and overflow will be ignored so the generated address will be 0– 0FFFFH. Word, byte, or bit data can be accessed at the specified address.

[X1+A] : X1 indirect addressing with 8-bit register displacement (AL) [X1+R0] : X1 indirect addressing with 8-bit register displacement (R0)

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RAM

Current Page SBA Area

[Bit Type]

SB sbaoff 4C0H.0 RB sbaoff 2E80H JBS sbaoff VAR,LABEL JBR sbaoff 17FFH.3,LABEL

xxC0H

xxxxH

xxFFH

SB 2C0H.0 RB 2E80H JBS VAR,LABEL JBR 17FFH.3,LABEL

RAM

FIXED Page SBA Area

[Bit Type]

SB sbafix 2C0H.0 RB sbafix 1600H JBS sbafix VAR,LABEL JBR sbafix 2EFH.7,LABEL

02C0H

02xxH

02FFH

SB 2C0H.0 RB 1600H JBS VAR,LABEL JBR 2EFH.3,LABEL

[5] Special Bit Area Addressing

A. FIXED Page SBA Area Addressing: sbafix Badr B. Current Page SBA Area Addressing: sbaoff Badr

A. FIXED Page SBA Area Addressing FIXED page SBA area addressing specifies a bit address in the FIXED page’s 512-bit

SBA area (2C0H.0–2FFH.7). Only bit data can be accessed at the specified address. The instructions that can use this addressing are SB, RB, JBS, and JBR.

B. Current Page SBA Area Addressing Current page SBA area addressing specifies a bit address in the current page’s 512-bit

SBA area (xxC0H.0–xxFFH.7) (excluding access inhibit area). Only bit data can be accessed at the specified address.

The instructions that can use this addressing are SB, RB, JBS, and JBR.

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3.3.2 ROM Addressing

ROM addressing specifies addressing of program variables in ROM space. The modes provided are immediate addressing, table data addressing, and program code addressing.

[1] Immediate Addressing

Immediate addressing specifies access of immediate data embedded in instruction code. For words, two bytes (N16) in instruction code will be accessed. For bytes, one byte (N8) in instruction code will be accessed.

Word values are expressions in the range 0–0FFFFH. Byte values are expressions in the range 0–0FFH. However, the assembler permits values in the range covered by both signed and unsigned expressions. For words that range is from –8000H to +0FFFFH, and for bytes it is from –80H to +0FFH.

[Word Type]

L A, #1234H MOV X1, #WORD_ARRAY_BASE

[Byte Type]

LB A, #12H MOVB X1, #BYTE_ARRAY_BASE

[2] Table Data Addressing

Table data addressing specifies access for the 64K bytes in the table segment of ROM space as specified by TSR. This mode can be used with operands of LC, LCB, CMPC, and CMPCB instructions.

A. Direct Table Addressing: Tadr B. RAM Addressing Indirect Table Addressing: [**] C. RAM Addressing Indirect Addressing with 16-Bit Base: T16 [**]

A. Direct Table Addressing Direct table addressing specifies an address (0–0FFFFH: 64K bytes) in the table

segment specified by TSR with two bytes of instruction code. Word or byte data can be accessed at the specified address. This addressing can be used with the four instructions LC, LCB, CMPC, and CMPCB.

[Word Type]

LC A, VAR CMPC A, VAR

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[Byte Type]

LCB A, VAR CMPCB A,

VAR

B. RAM Addressing Indirect Table Addressing RAM addressing indirect table addressing uses the word data specified by RAM

addressing as a pointer to the table segment specified by TSR. Word (16-bit) calculations are used to generate the address, with overflows ignored. Therefore the generated address will be 0–0FFFFH. Table memory can be accessed by using a register or data memory as a pointer into the table memory. This addressing can be used with the four instructions LC, LCB, CMPC, and CMPCB.

[Word Type]

LC A,

[A]

CMPC A, [1234[X1]]

[Byte Type]

LCB A, [ER0] CMPCB A, [VAR]

C. RAM Addressing Indirect Addressing with 16-Bit Base RAM addressing indirect addressing with 16-bit base specifies two bytes (D16) in

instruction code as a base and adds it to the contents of word data specified by RAM addressing to obtain an address (0–0FFFFH: 64K bytes) in the table segment specified by TSR. Word (16-bit) calculations are used to generate the address, with overflows ignored. Therefore the generated address will be 0–0FFFFH. Word or byte data can be accessed at the specified address.

This mode can be used with operands of LC, LCB, CMPC, and CMPCB instructions. [Word Type]

LC A, 2000H[A] CMPC A, 2000H[1234[X1]]

[Byte Type]

LCB A, 2000H[ER0] CMPCB A, 2000H[VAR]

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[3] Program Code Addressing

Program code addressing specifies access of the current program code in ROM space. These modes are used as operands of branch instructions.

A. NEAR Code Addressing: Cadr B. FAR Code Addressing: Fadr C. Relative Code Addressing: radr D. ACAL Code Addressing: Cadr11 E. VCAL Code Addressing: Vadr F. RAM Addressing Indirect Code Addressing: [**]

A. NEAR Code Addressing Near code addressing specifies an address (0–0FFFFH: 64K bytes) in the current code

segment with two bytes of instruction code. This addressing can be used with J and CAL instructions.

[Example of Use]

J 3000H CAL LABEL

B. FAR Code Addressing Far code addressing specifies an address (0:0–1:0FFFFH: 128K bytes) in program

memory space with three bytes of instruction code. This addressing can be used with FJ and FCAL instructions.

[Example of Use]

FJ 1: 3000H FCAL FARLABEL

C. Relative Code Addressing Relative code addressing takes the current program counter (PC) value as a base and

adds it to an 8-bit or sign-extended 7-bit value in instruction code to obtain an address (0–0FFFFH: 64K bytes) in the current code segment. Word (16-bit) calculations are used to generate the address, with overflows ignored. Therefore the generated address will be 0–0FFFFH. This addressing can be used with SJ and conditional branch instructions.

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[Example of Use]

SJ LABEL DJNZ R0,

LABEL

JC LT,

LABEL

D. ACAL Code Addressing ACAL code addressing specifies an address in the ACAL area (1000H–17FFH: 2K

bytes) in the current code segment with 11 bits of instruction code. This addressing can be used only with ACAL instructions.

[Example of Use]

ACAL 1000H ACAL ACALLABEL

E. VCAL Code Addressing VCAL code addressing specifies an entry (word data) in the vector table for VCAL

instructions with 4 bits of instruction code. The vector table is located at even addresses in the range 004AH–0069H in segment 0. This addressing can be used only with VCAL instructions.

[Example of Use]

VACL 4AH VCAL 0: 4AH VCAL VECTOR

F. RAM Addressing Indirect Code Addressing RAM addressing indirect code addressing uses word data specified by RAM addressing

as a pointer to the code segment. Word (16-bit) calculations are used to generate the address, with overflows ignored. Therefore the generated address will be 0–0FFFFH. It allows indirect jumps and calls using a register or data memory as a pointer to code memory. This addressing can be used with J and CAL instructions.

[Example of Use]

J [A] CAL [1234[X1]]

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[4] ROM Window Addressing

ROM window addressing accesses table data in ROM space using RAM addressing. This mode reads data in the table segment specified by TSR using data segment window opened by the program. (See "ROM Window Function.")

Data memory addressing is permitted in the ROM window area, but results are not guaranteed if an instruction that writes to the ROM window is executed.