OKI ML66514 Specifications

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Page 1

FEDL66517-01

This version: Apr. 2001

Semiconductor

Previous versi on: Mar. 2000

ML66517 Family

16-Bit Microcontroller

GENERAL DESCRIPTION

The ML66517 family of highly fu nctional C MOS 16-bit single chip m icrocontrollers utilizes th e nX-8/500S, Ok i's proprietary CPU core.

Each device includes capture input with an internal digital filter, 10-bit A/D converter, a number of timers, and dedicated 3-phase PWM (6 outputs) function capable of generating and controlling of AC/DC motor driving waveforms.

By means of the internal dedicated function for motor control, this general-purpose microcontroller is optimally suited for DC and AC motor control applications for energy saving. And the internal hardware multiplier allows high-speed arithmetic operations to be executed. And also the internal clock multiplication circuit can reduce the source frequency noise so that high-speed operations can be performed.

The flash ROM versions (ML66Q517 and ML66Q515) programmable with a single 5V power supply (4.5 to

5.5V) are also included in the family.

APPLICATIONS

Air conditioner or inverter control Motor control for FA equipment

ORDERING INFORMATION

Order Code or Product Name Package Remark ML66514-xxRB *1 5 V mask ROM version (4.5 to 5.5 V) ML66Q515-NRB *2 ML66517-xxGA *1 5 V mask ROM version (4.5 to 5.5 V) ML66Q517-NGA *2

*1 : The “xx” of “-xx” stands for the code number. *2 : The “N” of “-N” stands for the flash ROM, blank version. When OKI programs and ship the flash ROM, the part number is changed from ”–N” to ”–XX” (code number ) , for example, ML66Q517-999GA.

64-pin plastic SDIP

(SDIP 64-P-750-1.778)

80-pin plastic QFP

(QFP 80-P-1420-0.80-BK)

5 V flash ROM version (4.5 to 5.5 V)

ML66517 flash ROM version (4.5 to 5.5 V)

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Semiconductor

ML66517 Family

FEATURES

Name ML66514 ML66517 Operating temperature –40°C to 85°C Power supply voltage/

Maximum frequency Minimum instruction

execution time Internal ROM size (max. external) 32 KB (64 KB) 64 KB (128 KB) Internal RAM size (max. external) 1 KB (64 KB) 2 KB (64 KB)

46 I/O pins (with pull-up resistors,

I/O ports

Timers

Serial port Synchronous/UART × 2ch A/D converter 10-bit × 4ch 10-bit × 8ch 3-phase PWM (AC/DC motor control) External interrupt Non-Maskable × 1ch;

Interrupt priority 3 levels

Flash ROM version

programmable at the bit level),

4 input pins

16-bit auto-reload timer (also functions as a event input/timer out) × 1ch

8-bit auto reload timer × 2ch

(also functions as serial communication baud rate generators)

8-bit auto reload timer × 1ch (also functions as a watchdog timer)

8-bit PWM × 2ch (can also be

used as 16-bit PWM × 1ch)

Maskable × 2ch

External bus interface (Multiplexed address and data buses)

ML66Q515

(ROM = 64 KB, RAM = 2 KB)

= 4.5 to 5.5 V/f = 25 MHz

80 nsec @25 MHz

56 I/O pins (with pull-up resistors,

programmable at the bit level),

8 input pins

16-bit free-running counter × 1ch

Compare output/capture input × 2ch

8-bit auto reload timer × 4ch (can a lso

be used as 16-bit auto reload timer ×

1ch and 8-bit auto reload tim er × 2ch)

Capture input × 2ch

8-bit auto reload timer × 2ch

8-bit PWM × 4ch (can al so be u sed as

16-bit PWM × 2ch)

Available

Non-Maskable × 1ch;

Maskable × 4ch

Multiplication calculatorOthers

Clock multiplication circuit (x2, x4)

ML66Q517

FEDL66517-01

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FEDL66517-01

Semiconductor

ML66517 Family

SPECIAL FEATURES

1. High-performance CPU

The family includes the high-performance CPU, powerful bit manipulation instruction set, full symmetrical addressing mode, and ROM WINDOW function, and also provides the best optimized C compiler support.

2. 3-phase PWM circuit for generating motor drive waveforms

The device includes a 16-bit three-phase PWM (six outputs) circuit designed specifically for generating AC three-phase motor or DC three-phase brushless motor drive waveforms. PWM and level outputs can be switched by compare and match circuitry and software, and the compare and match circuitry can switch the outputs in real time. The device has circuitry to fix the three-phase outputs at an inactive level by inputting malfunction signals from a motor at the specific pin.

3. Capture inputs with digital filters

The device has two channels of capt ure inputs with 3/4 digital filters. T he device is best suited to event inter val measurement, pulse width measurement, etc. in a high noise environment such as motor control. An optimum filter can be selected according to noise width since a sampling interval of an input signal can be selected. A digital filter OFF mode can also be selected.

4. High-speed multiplier

The device includes a dedicated high-speed multiplier. The calculation time, 16 bits × 16 bits = 32 bits, is 200 ns (f = 25 MHz).

5. Clock multiplication circuit

The device includes a clock multiplication circuit in which the clock can be selected as a source clock (PLL OFF), 2 × clock, or 4 × clock. Therefore, the use of a low frequency oscillator (external clock) allows the device to internally operate at a high speed, which achieves noise reduction and lower power consumption.

6. Flash memory version programmable wit h a single power supply

In addition to the mask ROM versions, the family includes the vers ions (ML 66Q517 and ML 66Q515) w ith 64 KB flash memory that can be programmed with a single 5 V supply (4.5 to 5.5 V).

7. A high-precision A/D converter

The device has a high precision 10-bit A/D converter with eight channels. An independent result register for each channel provides easy accessibility by software. The A/D converter is activated in a channel select mode, and automatic conversion is also implemented in a scan mode which sc ans from any d esignated channel to the la st channel (ch 7).

8. Programmable pull-up resistors

Building the pull-up resistors into the chip contributes to overall design compactness. Making them programmable on a per-bit basis allows co mplete flexibility in circuit board layout and system design. T hese programmable pull-up resistors are available for all I/O pins not already assigned specific functions (such as the oscillator connection pins).

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(U)

Semiconductor

FEDL66517-01

ML66517 Family

PWM output switching every 60°°°° of motor turn using the compare-out timer

PWM-U

PWM-UB

PWM-V

PWM-VB

PWM-W

PWM-WB

Compare register

value setting

CAP input CAP input CAP input CAP input CAP input

CAP input

Compare-match

generation

CAP input

PWM Output Timing (DC Motor Control)

Period register

setting value

16-bit counter value

0000H

PWM-UB

PWM-U

Underflow counts up the counter

Set by 8-bit dead-time timer

(Only U and U output signals are indicated above)

PWM Output Timing (AC Motor Control)

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Semiconductor

BLOCK DIAGRAM

FEDL66517-01

ML66517 Family

TM0OUT

TM0EVT

TM1OUT

TM1EVT

TM2OUT

TM2EVT

CLKOUT

RXD1

TXD1

RXC1

TXC1

RXD6

TXD6

RXC6

TXC6

TM5EVT

PWM0OUT

PWM2OUT

PWM1OUT

PWM3OUT

16-bit Timer0

8-bit Timer1

8-bit Timer2

Peripheral

SIO1

(UART/SYNC)

8-bit Timer4/BRG

SIO6

(UART/SYNC)

8-bit Timer3/BRG

8-bit Timer5

8-bit PWM0

8-bit PWM1

ALU

ALU Control

ACC

Memory Control

Pointing Registers

Local Registers

RAM 2K

CPU Core

Control Registers

SSP

LRB

ROM

64K

System Control

PSW

CSRTSR

Instruction

Decoder

OSC0

OSC1

CLKSEL0

CLKSEL1

RES

PSEN

ALE

INACT PWMU

PWMUB

PWMV

PWMVB

PWMW

PWMWB

CAPF0 CAPF1

CPCMF0 CPCMF1

REF

AGND

AI0 to AI7

NMI

EXINT0

EXINT3

8-bit Timer9

3-phase

PWM

CMP

CAP

CAP/CMP

16-bit FRC

10-bit A/D Converter

Interrupt

TBC

8-bit Timer6/WDT

ML66517/ML66Q517 Block Diagram

AD0 to AD7

Bus Port Control

A8 to A16

P0 P1 P2 P3 P5 P6 P7 P8 P10

Port Control

P11 P12

P15 P16 P17

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Semiconductor

FEDL66517-01

ML66517 Family

TM0OUT

TM0EVT

CLKOUT

RXD1

TXD1

RXC1

TXC1

RXD6

TXD6

RXC6

TXC6

PWM0OUT

PWM1OUT

INACT

PWMU

PWMUB

PWMV

PWMVB

PWMW

PWMWB

16-bit Timer0

Peripheral

SIO1

(UART/SYNC)

8-bit Timer4/BRG

SIO6

(UART/SYNC)

8-bit Timer3/BRG

8-bit Timer5

8-bit PWM0

8-bit PWM1

8-bit Timer9

3-phase

PWM

ALU

ALU Control

ACC

Memory Control

Pointing Registers

Local Registers

RAM

1K/2K

CPU Core

Control Registers

SSP

LRB

32K/64K

ROM

System

Control

PSW

Instruction

Decoder

OSC0

OSC1

CLKSEL0

CLKSEL1

RES

PSEN

ALE

AD0 to AD7

Bus Port Control

A8 to A15

CMP

CAPF0 CAPF1

CPCMF0 CPCMF1

REF

AGND

AI4 to AI7

NMI

EXINT0

EXINT1

*1 ML66Q515 has 2KB RAM, ML66514 has 1KB RAM *2 ML66Q515 has 64KB ROM, ML66514 has 32KB ROM

CAP

CAP/CMP

16-bit FRC

10-bit A/D

Converter

Interrupt

ML66Q515/ML66514 Block Diagram

TBC

8-bit Timer6/WDT

P0 P1 P3 P5 P6 P7 P8 P11

Port Control

P12 P15 P16 P17

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Semiconductor

PIN CONFIGURATION (TOP VIEW)

RXC6/P15-2

TXC6/P15-3

RXD1/P8-0

TXD1/P8-1

RXC1/P8-2

TXC1/P8-3 PWM2OUT/P8-6 PWM3OUT/P8-7 PWM0OUT/P7-6 PWM1OUT/P7-7

GND

PWMU/P16-0

PWMUB/P16-1

PWMV/P16-2

PWMVB/P16-3

PWMW/P16-4

PWMWB/P16-5

INACT/P16-6

NMI CAPF0/P17-0 CAPF1/P17-1

CPCMF0/P17-2 CPCMF1/P17-3

EXINT0/P6-0 EXINT1/P6-1

GND

RXD6/P15-0

TXD6/P15-1

AGND

AI5/P12-5

AI6/P12-6

AI7/P12-7

AI2/P12-2

AI3/P12-3

AI4/P12-4

REF

AI0/P12-0

AI1/P12-1

65707580

40353025

FEDL66517-01

ML66517 Family

P2-0/A16 P1-7/A15 P1-6/A14 P1-5/A13 P1-4/A12 P1-3/A11 P1-2/A10 P1-1/A9 P1-0/A8 GND P3-3/WR P3-2/RD P3-1/PSEN P3-0/ALE P0-7/AD7 P0-6/AD6 P0-5/AD5 P0-4/AD4 P0-3/AD3 P0-2/AD2 P0-1/AD1 P0-0/AD0 EA RES

OSC1

OSC0

P6-3/EXINT3

P6-2/EXINT2

P6-6/TM2EVT

P6-4/TM1EVT

P6-5/TM1OUT

P5-7/TM0EVT

P5-6/TM0OUT

P6-7/TM2OUT

P10-7/TM5EVT

P11-2/CLKOUT

GND

80-Pin Plastic QFP

ML66517/ML66Q517 Pin Config ur atio n

CLKSEL0

CLKSEL1

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Semiconductor

FEDL66517-01

ML66517 Family

PSEN/P3-1

RD/P3-2

WR/P3-3

GND

A8/P1-0

A9/P1-1 A10/P1-2 A11/P1-3 A12/P1-4 A13/P1-5 A14/P1-6 A15/P1-7

REF

AI4/P12-4 AI5/P12-5 AI6/P12-6 AI7/P12-7

AGND

GND

RXD6/P15-0

TXD6/P15-1

RXC6/P15-2

TXC6/P15-3

RXD1/P8-0

TXD1/P8-1

RXC1/P8-2

TXC1/P8-3 PWM0OUT/P7-6 PWM1OUT/P7-7

PWMU/P16-0

PWMUB/P16-1

P3-0/ALE P0-7/AD7 P0-6/AD6

P0-5/AD5 P0-4/AD4 P0-3/AD3 P0-2/AD2 P0-1/AD1 P0-0/AD0 EA RES CLKSEL1 CLKSEL0 V

OSC1 OSC0

GND P11-2/CLKOUT

P5-7/TM0EVT P5-6/TM0OUT

P6-1/EXINT1 P6-0/EXINT0 P17-3/CPCMF1 P17-2/CPCMF0 P17-1/CAPF1 P17-0/CAPF0 NMI P16-6/INACT

P16-5/PWMWB P16-4/PWMW P16-3/PWMVB P16-2/PWMV

64-Pin Plastic SDIP

ML66Q515/ML66514 Pin Config ur atio n

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Semiconductor

RXD1/P8-0

TXD1/P8-1

RXC1/P8-2

TXC1/P8-3 PWM0OUT/P7-6 PWM1OUT/P7-7

PWMU/P16-0

PWMUB/P16-1

PWMV/P16-2

PWMVB/P16-3

PWMW/P16-4

PWMWB/P16-5

INACT/P16-6

CAPF0/P17-0 CAPF1/P17-1

NMI

TXD6/P15-1

TXC6/P15-3

17 30

RXD6/P15-0

RXC6/P15-2

AGND

GND

AI7/P12-7

AI4/P12-4

AI5/P12-5

AI6/P12-6

REF

A15/P1-7

A12/P1-4

A14/P1-6

A13/P1-5

496064

FEDL66517-01

ML66517 Family

P1-3/A11 P1-2/A10 P1-1/A9 P1-0/A8 GND P3-3/WR P3-2/RD P3-1/PSEN P3-0/ALE P0-7/AD7 P0-6/AD6 P0-5/AD5 P0-4/AD4 P0-3/AD3 P0-2/AD2 P0-1/AD1

P6-1/EXINT1

P6-0/EXINT0

P17-3/CPCMF1

P17-2/CPCMF0

P5-6/TM0OUT

GND

OSC1

OSC0

P5-7/TM0EVT

P11-2/CLKOUT

RES

CLKSEL1

CLKSEL0

64-Pin Plastic QFP

ML66Q515/ML66514 Pin Config ur atio n

P0-0/AD0

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FEDL66517-01

Semiconductor

ML66517 Family

PIN DESCRIPTIONS

In the Type column, “I” indicates an input pin, “O” indicates an output pin, and “I/O” indicates an I/O pin.

ML66517/ML66Q517 Pin Desc rip tio ns

Description

Function Symbol

P0_0/AD0 to P0_7/AD7

P1_0/A8 to P1_7/A15

P2_0/A16 I/O

P3_0/ALE O

P3_1/PSEN O

P3_2/RD O

Port

P3_3/WR

P5_6/TM0OUT P5_7/TM0EVT

P6_0/EXINT0 I P6_1/EXINT1 I P6_2/EXINT2 I P6_3/EXINT3 I P6_4/TM1EVT I P6_5/TM1OUT O P6_6/TM2EVT I P6_7/TM2OUT P7_6/PWM0OUT O

P7_7/PWM1OUT

Type

I/O

Primary function

8-bit I/O port Pull-up resistors can be specified for each individual bit

1-bit I/O port Pull-up resistors can be specified for each individual bit

4-bit I/O port 10 mA sink capability Pull-up resistors can be specified for each individual bit

2-bit I/O port Pull-up resistors can be specified for each individual bit

8-bit I/O port Pull-up resistors can be specified for each individual bit

2-bit I/O port Pull-up resistors can be specified for each individual bit

Type

I/O

O O

Secondary function

External memory access Address output/data I/O port

External memory access Address output port

External memory access Address latch enable signal output pin

Exte r nal pr ogram memory access Read strobe output pin

External data memory access Read strobe output pin

External data memory access Write strobe output pin

Timer 0 timer output pin Timer 0 external event input pin

External interrupt 0 input pin External interrupt 1 input pin External interrupt 2 input pin External interrupt 3 input pin Timer 1 external event input pin Timer 1 timer output pin Timer 2 external event input pin Timer 2 timer output pin PWM0 output pin PWM1 output pin

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Semiconductor

Function Symbol

P8_0/RXD1 I P8_1/TXD1 O P8_2/RXC1 I/O P8_3/TXC1 I/O P8_6/PWM2OUT O P8_7PWM3OUT

P10_7/TM5EVT I/O

P11_2/CLKOUT I/O

P12_0/AI0 to P12_7/AI7

P15_0/RXD6 I

Port

P15_1/TXD6 O P15_2/RXC6 I/O P15_3/TXC6 P16_0/PWMU O P16_1/PWMUB O P16_2/PWMV O P16_3/PWMVB O P16_4/PWMW O P16_5/PWMWB O P16_6/INACT P17_0/CAPF0 I P17_1/CAPF1 I

P17_2/CPCMF0 I/O

P17_3/CPCMF1

ML66517/ML66Q517 Pin Descriptions (Continued)

Description

Primary function

Type

6-bit I/O port Pull-up resistors can be specified for each individual bit

I/O

1-bit I/O port Pull-up resistors can be specified

8-bit input port

4-bit I/O port Pull-up resistors can be

I/O

specified for each individual bit

7-bit I/O port Pull-up resistors can be specified for each individual bit

I/O

4-bit I/O port Pull-up resistors can be specified for each individual bit

I/O

Type

I/O

SIO1 receive data input pin SIO1 transmit data output pin SIO1 receive clock I/O pin SIO1 transmit clock I/O pin PWM2 output pin PWM3 output pin Timer 5 external event input pin

Main clock pulse output pin

A/D converter analog input port

SIO6 receive data input pin SIO6 transmit data output pin SIO6 receive clock I/O pin SIO6 transmit clock I/O pin 3-phase PWMU output pin 3-phase PWMUB output pin 3-phase PWMV output pin 3-phase PWMVB output pin 3-phase PWMW output pin 3-phase PWMWB output pin Abnormality detect input pin Capture 0 input pin Capture 1 input pin Capture 0 input/compare 0 output

pin Capture 1 input/compare 1 output

FEDL66517-01

ML66517 Family

Secondary function

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Semiconductor

ML66517/ML66Q517 Pin Descriptions (Continued)

Function Symbol Type Description

Power supply

GND I

REF

AGND I

OSC0 I

Oscillation

OSC1 O

CLKSEL0 I CLKSEL1 I

Reset RES I Reset inpu t pin

NMI I Non-maskable interrupt input pin

Others

EA I

Power supply pin

Connect all V

pins to the power supply.*

GND pin Connect all GND pins to GND.*

Analog reference voltage pin (Connect to the V

converter is not used.) Analog GND pin (Connect to the GND pin when A/D converter is not

used.) Main clock oscillation input pin

Connect to a crystal or ceram ic os cil lat or. O r, in put an external clock. Main clock oscillation output pin

Connect to a crystal or ceramic oscillator. The clock output is opposite in phase to OSC0. Leave this pin unconnected when an external clo ck is use d .

Clock multiplication factor select pin Clock multiplication factor is selected from source oscillation (PLL OFF), source oscillation × 2, or source oscillation × 4

External program memory access input pin If the EA pin is enabled (low level), the internal program me mory is masked and the CPU executes the pr ogram code in external pro gram memory all address space.

FEDL66517-01

ML66517 Family

pin when A/D

* Each of the family devices has unique pattern routes for the internal power and ground. Connect the

power supply voltag e to all V one or more V

or GND pins to which the power supply voltage or the ground potential is not

pins and the groun d poten tia l to a ll GND pins . If a de vice m ay have

connected, it can not be guaranteed for normal operation.

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Semiconductor

Function Symbol

P0_0/AD0 to P0_7/AD7

P1_0/A8 to P1_7/A15

P3_0/ALE O

P3_1/PSEN O

P3_2/RD O

P3_3/WR P5_6/TM0OUT O

P5_7/TM0EVT

Port

P6_0/EXINT0 I P6_1/EXINT1 P7_6/PWM0OUT O P7_7/PWM1OUT P8_0/RXD1 I

P8_1/TXD1 O P8_2/RXC1 I/O P8_3/TXC1

P11_2/CLKOUT I/O

P12_4/AI4 to P12_7/AI7

P15_0/RXD6 I P15_1/TXD6 O P15_2/RXC6 I/O P15_3/TXC6

ML66Q515/ML66514 Pin Desc rip tio ns

Description

Type

I/O

Primary function

8-bit I/O port Pull-up resistors can be specified for each individual bit

4-bit I/O port 10mA sink capability Pull-up resistors can be specified for each individual bit

2-bit I/O port Pull-up resistors can be specified for each individual bit

4-bit I/O port Pull-up resistors can be specified for each individual bit

1-bit I/O port Pull-up resistors can be specified

4-bit input port

4-bit I/O port Pull-up resistors can be specified for each individual bit

Type

I/O

ML66517 Family

Secondary function

External memory access Address output/Data I/O port

External memory access Address output port

External memory access Address latch enable signal output pin

External program memory access Read strobe output pin

External data memory access Read strobe output pin

External data memory access Write strobe output pin

Timer 0 timer output pin Timer 0 external event input pin

External interrupt 0 input pin External interrupt 1 input pin

PWM0 output pin PWM1 output pin

SIO1 receive data input pin SIO1 transmit data output pin SIO1 receive clock I/O pin SIO1 transmit clock I/O pin Main clock pulse output pin

A/D converter analog input port

SIO6 receive data input pin SIO6 transmit data output pin SIO6 receive clock I/O pin SIO6 transmit clock I/O pin

FEDL66517-01

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Semiconductor

Function Symbol

P16_0/PWMU O 3-phase PWMU output pin P16_1/PWMUB O 3-phase PWMUB output pin P16_2/PWMV O 3-phase PWMV output pin P16_3/PWMVB O 3-phase PWMVB output pin P16_4/PWMW O 3-phase PWMW output pin P16_5/PWMWB O 3-phase PWMWB output pin

Port

P16_6/INACT P17_0/CAPF0 I Capture 0 input pin P17_1/CAPF1 I Capture 1 input pin

P17_2/CPCMF0 I/O

P17_3/CPCMF1

ML66Q515/ML66514 Pin Descriptions (Continued)

Description

Type

I/O

Primary function

7-bit I/O port Pull-up resistors can be specified for each individual bit

4-bit I/O port Pull-up resistors can be specified for each individual bit

Type

I Abnormality detect input pin

Capture 0 input/compare 0 output pin

Capture 1 input/compare 1

I/O

output pin

FEDL66517-01

ML66517 Family

Secondary function

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Semiconductor

ML66Q515/ML66514 Pin Descriptions (Continued)

Function Symbol Type Description

GND I

Power supply

REF

AGND I

OSC0 I

Oscillation

OSC1 O

CLKSEL0 I CLKSEL1 I

Reset RES I Reset inpu t pin

NMI I Non-maskable interrupt input pin

Others

EA I

Power supply pin

Connect all V

pins to the power supply.*

GND pin Connect all GND pins to GND.*

Analog reference voltage pin (Connect to the V

converter is not used.) Analog GND pin (Conne ct t o the GND pin w hen A/D convert er i s not

used.) Main clock oscillation input pin

Connect to a crystal or ceramic oscillator. Or, input an external clock.

Main clock oscillation output pin Connect to a crystal or ceramic oscillator. The clock output is opposite in phase to OSC0. Leave this pin unconnected when an external clo ck is use d .

Clock multiplication factor select pin Clock multiplication factor is selected from source oscillation (PLL OFF), source oscillation × 2, or source oscillation × 4

External program memory access input pin If the EA pin is enabled (low level), the internal program me mory is masked and the CPU executes the program code in external program memory all address space.

FEDL66517-01

ML66517 Family

pin when A/D

* Each of the family devices has unique pattern routes for the internal power and ground. Connect the

power supply voltag e to all V one or more V

or GND pins to which the power supply voltage or the ground potential is not

pins and the groun d poten tia l to a ll GND pins . If a de vice m ay have

connected, it can not be guaranteed for normal operation.

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Semiconductor

ABSOLUTE MAXIMUM RATINGS

Parameter Symbol Condition Rating Unit Digital power supply voltage V Input voltage V Output voltage V Analog reference voltage V Analog input voltage V

REF

GND = AGND = 0 V

Ta = 25°C

Ta = 85°C

per package

Storage temperature T

STG

RECOMMENDED OPERATING CONDITIONS

FEDL66517-01

ML66517 Family

–0.3 to +7.0 V –0.3 to VDD +0.3 V –0.3 to VDD +0.3 V –0.3 to VDD +0.3 V

–0.3 to V

REF

80-pin QFP 600 64-pin QFP 520Power dissipation P

64-pin SDIP 1280

— –50 to +150 °C

Parameter Symbol Condition Rating Unit Digital power supply voltage V Analog reference voltage V Analog input voltage V Memory hold voltage V

Internal operating frequency f

REF

DDH

OSC

≤ 25 MHz 4.5 to 5.5 V

OSC

—V

– 0.3 to V

— AGND to V

= 0 Hz 2.0 to 5.5 V

OSC

PLL (multiplier) OFF 2 to 25

PLL (multiplier) ON 20 to 25

REF

Ambient temperature Ta — –40 to +85 °C

MOS load 20 —

P3 6

Fan out N

TTL load

P0, P16 2

P1, P2, P5 to P8,

P10, P11, P15, P17

INTERNAL FLASH ROM PROGRAMMING CONDITIONS

Parameter Symbol Condition Rating Unit

Supply Voltage V Ambient Temperature Ta

During Programming +0 to +50 Endurance CEP — 100 Cycles Blocks size — — 128 bytes

— 4.5 to 5.5 V

During Read –40 to +85

°C

V V

MHz

—

16/29

Page 17

FEDL66517-01

Semiconductor

ML66517 Family

ALLOWABLE OUTPUT CURRENT

(1) ML66517/ML66Q517 (80-pin QFP)

(VDD = 4.5 to 5.5 V, Ta = –40 to +85°C)

Parameter Pin Symbol Min. Typ. Max. Unit “H” output pin (1 pin) All output pins I “H” output pins

(sum total) “L” output pin (1 pin)

Sum total of all output pins ∑

P3 — — 10

Other ports

IOH

Sum total of P0, P3 60 Sum total of P1, P2

“L” output pins (sum total)

Sum total of P7, P8, P15

Sum total of P5, P6, P10,

∑

IOL

P11, P16, P17

Sum total of all output pins

Note: Each of the family devices has unique pattern routes for the internal power and ground. Connect

the power supply voltage to all V

have one or mor e V

or GND pins to whic h the po wer s uppl y voltage or the gro und pot entia l is

pins and the ground potential to all GND pins. If a device may

not connected, it can not be guaranteed for normal operation.

——–2 — — –50

——5

——

100

(2) ML66Q515/ML66514 (64-pin QFP/SDIP)

(VDD = 4.5 to 5.5 V, Ta = –40 to +85°C)

Parameter Pin Symbol Min. Typ. Max. Unit “H” output pin (1 pin) All output pins I “H” output pins

(sum total) “L” output pin (1 pin)

Sum total of all output pins ∑

P3 — — 10

Other ports

Sum total of P0, P3 50

“L” output pins (sum total)

Sum total of P5 to P8,

P11, P15, P17

Sum total of all output pins

IOH

∑

IOL

——–2 — — –20

——5

——

Note: Each of the family devices has unique pattern routes for the internal power and ground. Connect

the power supply voltage to all V

have one or mor e V

or GND pins to whic h the po wer s uppl y voltage or the gro und pot entia l is

pins and the ground potential to all GND pins. If a device may

not connected, it can not be guaranteed for normal operation.

17/29

Page 18

FEDL66517-01

Semiconductor

ML66517 Family

ELECTRICAL CHARACTERISTICS

DC Characteristics

(VDD = 4.5 to 5.5 V, Ta = –40 to +80°C)

Parameter Symbol Condition Min. Typ. Max. Unit “H” input voltage *1 0.44 V “H” input voltage *2 to *8 “L” input voltage *1 –0.3 — 0.16 V “L” input voltage *2 to *8

“H” output voltage *1, *4, *5 “H” output voltage *2 “L” output voltage *1, *5 “L” output voltage *4 “L” output voltage *2

— —

IO = –400 µA V IO = –2.0 mA V IO = –200 µA V IO = –2.0 mA V

0.80 V –0.3 — 0.2 V

– 0.4 — – 0.6 — — – 0.4 — —

– 0.6 — — IO = 3.2 mA — — 0.4 I

= 5.0 mA — — 0.8

IO = 3.2 mA — — 0.4

IO = 10.0 mA — — 1.0

IO = 1.6 mA — — 0.4 IO = 5.0 mA — — 0.8

Input leakage current*3, *7 — — 1/–1 Input current *6 — — 1/–250

IH/IIL

Input current *8 Output leakage current

*1, *2, *4, *5 Pull-up resistance R Input capacitance C Output capacitance C

Analog reference supply current I

REF

pull

VI =VDD/0 V

— — 15/–15

VO =VDD/0 V — —

VI = 0 V 25 50 100

f = 1 MHz, Ta = 25°C

—5—

—7— During A/D operation — — 4 mA When A/D is stopped — — 10 µA

*1:Applicable to P0 *2:Applicable to P1, P2, P6, P7, P8, P10, P11, P15, P17 *3:Applicable to P12 *4:Applicable to P3 *5:Applicable to P16

*6:Applicable to RES *7:Applicable to EA, NMI, CLKSEL0, CLKSEL1

*8:Applicable to OSC0

—V —V

+ 0.3 + 0.3

± 10

µA

µA kΩ pF

Supply current

Mode CPU operation mode *1 I HALT mode *2 I

STOP mode *3 I

[Note]

Ports used as inputs are at VDD or 0 V. Other ports are unloaded. *1. CPU and all the peripheral functions (timer, PWM, A/D, etc.) are activated. *2. CPU is stopped, and all the peripheral functions (timer, PWM, A/D, etc.) are activated. *3. CPU and all the peripheral functions are deactivated.

Symbol Condition Min. Typ. Max. Unit

DDH

DDS

f=25 MHz f=25 MHz

ML66Q517/Q515

ML66517/514 — 1 50

—4060mA —3040mA —20900

µA

18/29

Page 19

Semiconductor

AC Characteristics

(1) External program memory control

Parameter Symbol Condition Min. Max. Unit Cycle time t Clock pulse width (HIGH level) t Clock pulse width (LOW level) t ALE pulse width t

PSEN pulse width t PSEN pulse delay time t

Low address setup time t Low address hold time t High address setup time t High address hold time t Instruction setup time t Instruction hold time t

cyc

φWH

φWL

PAD

ALS

ALH

AHS

AHH

(VDD = 4.5 to 5.5 V, Ta = –40 to +85°C)

= 25 MHz 40 —

OSC

13 —

13 — 2tφ – 10 — 2tφ – 18 —

tφ – 5 —

CL = 50 pF

2tφ – 15 —

tφ – 13 —

3tφ – 30 —

–8 —

30 —

–8 tφ – 3

FEDL66517-01

ML66517 Family

Note: tφ = t

cyc

CPUCLK

ALE

PSEN

AD0 to AD7

A8 to A16

cyc

φWH

φWL

PAD

PC0 to 7 INST0 to 7

ALS

AHS

ALH

PC8 to 16

Bus timing during no wait cycle time

AHH

19/29

Page 20

Semiconductor

(2) External data memory control

Parameter Symbol Condition Min. Max. Unit Cycle time t Clock pulse width (HIGH level) t Clock pulse width (LOW level) t ALE pulse width t

RD pulse width t WR pulse width t RD pulse delay time t WR pulse delay time t

Low address setup time t Low address hold time t High address setup time t High address hold time t Read data setup time t Read data hold time t Write data setup time t Write data hold time t

CPUCLK

cyc

φWH

φWL

RAD

WAD

ALS

ALH

AHS

AHH

FEDL66517-01

ML66517 Family

(VDD = 4.5 to 5.5 V, Ta = –40 to +85°C)

= 25 MHz 40 —

OSC

13 —

13 — 2tφ – 10 — 2tφ – 18 — 2tφ – 18 —

tφ – 5 — tφ – 5 —

CL = 50 pF

2tφ – 15 —

tφ – 13 —

3tφ – 30 —

tφ – 3 —

30 —

0tφ – 3

2tφ – 30 —

tφ – 3 —

Note: tφ = t

cyc

ALE

AD0 to AD7

A8 to A15

AD0 to AD7

A8 to A15

φWL

φWH

RAD

RAP0 to 7

ALS

AHS

RAP0 to 7 DOUT0 to 7

ALS

AHS

ALH

RAP8 to 15

WAD

ALH

RAP8 to 15

DIN0 to 7

AHH

Bus timing during no wait cycle time

20/29

Page 21

Semiconductor

(3) Serial port control

Master mode (Clock synchronous serial port)

Parameter Symbol Condition Min. Max. Unit Cycle time t Serial clock cycle time t Output data setup time t Output data hold time t Input data setup time t Input data hold time t

cyc

SCKC

STMXS

STMXH

SRMXS

SRMXH

(VDD = 4.5 to 5.5 V, Ta = –40 to +85°C)

= 25 MHz 40 —

OSC

4 t

cyc

2tφ – 5 —

CL = 50 pF

5tφ – 10 —

13 —

0—

FEDL66517-01

ML66517 Family

—

Note: tφ = t

cyc

CPUCLK

TXC/RXC

SDOUT (TXD)

SDIN (RXD)

SRMXS

SRMXH

STMXH

SCKC

STMXS

21/29

Page 22

Semiconductor

Slave mode (Clock synchronous serial port)

Parameter Symbol Condition Min. Max. Unit Cycle time t Serial clock cycle time t Output data setup time t Output data hold time t Input data setup time t Input data hold time t

cyc

CPUCLK

cyc

SCKC

STMXS

STMXH

SRMXS

SRMXH

(VDD = 4.5 to 5.5 V, Ta = –40 to +85°C)

= 25 MHz 40 —

OSC

4 t

cyc

2tφ – 15 —

CL = 50 pF

4tφ – 10 —

13 —

3—

FEDL66517-01

ML66517 Family

—

Note: tφ = t

cyc

TXC/RXC

SDOUT (TXD)

STMXH

SDIN (RXD)

SRMXS

SRMXH

Measurement points for AC timing (the serial port)

0 V

0.8V

0.2V

Measurement points for AC timing (except the serial port)

0.8V

0.2V

SCKC

STMXS

0 V

2.0 V

0.8 V

2.0 V

0.8 V

22/29

Page 23

Semiconductor

A/D Converter Characteristics

FEDL66517-01

ML66517 Family

(Ta = –40 to +85°C, VDD = V

= 4.5 to 5.5 V, AGND = GND = 0 V)

REF

Parameter Symbol Condition Min. Typ. Max. Unit Resolution n — 10 — Bit Linearity error E Differential linearity error E Zero scale error E Full-scale error E

Cross talk E

Conversion time t

CONV

Reference

Refer to measurement

circuit 1

Analog input source

impedance R

CONV

≤ 5 kΩ

= 10.7 µs

Refer to measurement

circuit 2

Set according to

ADTM set data

REF

——±3 ——±2 ——+3 ——–3

LSB

——±1

10.7 — — µs/ch

+5 V

voltage

0.1

–

47 µF

AI0 to AI7*

GND

0.1µF47 µF

0 VAGND

Analog input

– +

Analog input

5 kΩ

RI (impedance of analog input source) ≤5 kΩ

≅ 0.1 µF

Measurement Circuit 1

Cross talk is the difference

AI0

between the A/D conversion results when the same analog input is applied to AI0 through AI7 and the A/D conversion results of the circuit to the left.

*AI4 to AI7 for the ML66Q515/ML66514

0.1 µF

REF

AI1

AI7*

or AGND

Measurement Circuit 2

*AI4 to AI7 for the ML66Q515/ML66514

23/29

Page 24

FEDL66517-01

Semiconductor

ML66517 Family

Definition of Terminology

1. Resolution Resolution is the value of minimum discernible analog input. With 10 bits, since 2

= 1024, resolution of (V

– AGND) ÷ 1024 is possible.

REF

2. Linearity error Linearity error is the difference between ideal conversion characteristics and actual conversion characteristics of a 10-bit A/D converter (not including quantization error). Ideal conversion characteristics can be obtained by dividing the voltage between V

and AGND into 1024

REF

equal steps.

3. Differential linearity error Differential linearity error indicates the smoothness of conversion characteristics. Ideally, the rang e of analog input voltage that corresponds to 1 converted bit of digital output is 1LSB = (V

– AGND) ÷ 1024.

REF

Differential error is the difference between this ideal bit size and bit size of an arbitrary point in the con version range.

4. Zero scale error Zero scale error is the difference between ideal conversion characteristics and actual conversion characteristics at the point where the digital output changes from 000H to 001H.

5. Full-scale error Full-scale error is the difference between ideal conversion characteristics and actual conversion characteristics at the point where the digital output changes from 3FEH to 3FFH.

24/29

Page 25

FEDL66517-01

Semiconductor

ML66517 Family

PACKAGE DIMENSIONS

(Unit: mm)

QFP80-P-1420-0.80-BK

Mirror finish

Package material Epoxy resin Lead frame material 42 alloy

Pin treatment Package weight (g) 1.27 TYP. Rev. No./Last Revised 4/Nov. 28, 1996

Solder plating (≥5µm)

Notes for Mounting the Surface Mount Type Packages The surface mount type packages are very susceptible to heat in reflow mounting and humidity

absorbed in storage. Therefore, before you perf orm r eflow mounting, contac t Oki’s res ponsible sal es person on t he product name, package name, pin n umber, package code and desired m ounting conditions (reflow method, temperature and times).

25/29

Page 26

FEDL66517-01

Semiconductor

(Unit: mm)

SDIP64-P-750-1.778

ML66517 Family

Package material Epoxy resin Lead frame material Cu alloy Pin treatment Package weight (g) 8.70 TYP. Rev. No./Last Revised 2/Dec. 11, 1996

Solder plating (≥5µm)

26/29

Page 27

FEDL66517-01

Semiconductor

(Unit: mm)

QFP64-P1414-0.80-BK

ML66517 Family

Epoxy resin 42 alloy Solder plating (≥5µm)

0.87 TYP. 5/Sept.21,1999

Package material Lead frame material Pin treatment Package weight (g) Rev. No./Last Revised

Notes for Mounting the Surface Mount Type Packages The surface mount type packages are very susceptible to heat in reflow mounting and humidity

27/29

Page 28

Semiconductor

REVISION HISTORY

Date Changes compared to previous version Mar. 2000 Apr. 2001 - Modified the contents on P-1.

- Added the contents in table on P-2.

- Modified the contents in Fig. on P-9.

- Added the contents of P3_2 and P3_3 in table on P-10 and P-13.

- Modified the contents of P5_6 and P5_7 in table on P-13.

- Added the contents of V

- Modified the contents of “H” output pin (1pin) in table on P-17.

- Added the contents in Fig. and table on P-23.

and AGND in table on P-12 and P-15.

REF

FEDL66517-01

ML66517 Family

28/29

Page 29

FEDL66517-01

Semiconductor

ML66517 Family

NOTICE

1. The information contained herein can change without notice owing to produ ct an d/or techn i cal improv em ents. Before using the product, please make sure that the information being referred to is up-to-date.

2. The outline of action and examples for application circuits described herein have been chosen as an explanation for the standard action and performance of the product. When planning to use the product, please ensure that the external conditions are reflected in the actual circuit, assembly, and program designs.

3. When designing your product, please use our product below the specified maximum ratings and within the specified operating ranges including, but not limited to, operating voltage, power dissipation, and operating temperature.

4. Oki assumes no responsibility or liability whatsoever for any failure or unus ual or unexpected operation resulting from misuse, neglect, improper installation, repair, alteration or accident, improper handling, or unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified maximum ratings or operation outside the specified operating range.

5. Neither indemnity against nor license of a third party’s industrial and intellectual property right, etc. is granted by us in connection with the use of the product and/or the information and drawings contained herein. No responsibility is assumed by us for any infringement of a third party’s right which may result fro m the use thereof.

6. The products listed in this document are intended for use in general electronics equipment for commercial applications (e.g., office automation, communication equipment, measurement equipment, consumer electronics, etc.). These products are not authorized for use in any system or application that requires special or enhanced quality and reliability characteristics nor in any s ystem or application where the failure of such system or application may result in the loss or damage of property, or death or injury to humans. Such applications include, but are not limited to, traffic and automotive equipment, safety devices, aerospace equipment, nuclear power control, medical equipment, and life-support systems.

7. Certain products in this document may need government approval before they can be exported to particular countries. The purchaser as su m es the res pon s i bility of determining the legali ty of export of these products and will take appropriate and necessary steps at their own expense for these.

8. No part of the contents contained herein may be reprinted or reproduced without our prior permission.

29/29