Page 1
FEDL63187B-06
This version: Sep. 2001
1
Semiconductor
Previous versi on: Mar. 2000
ML63187B/63189B
4-Bit Microcontroller with Built-in1024-Dot Matrix LCD Drivers and Melody Circuit,
Operating at 0.9 V (Min.)
GENERAL DESCRIPTION
The ML63187B and ML63189B are CMOS 4-bit microcontroller with built-in 1024-dot matrix LCD drivers and
operates at 0.9 V (min.). The ML63187B and 63189B are suitable for applications such as games, toys, watches,
etc. which are provided with an LCD display.
The ML63187B and ML63189B are M6318x series mask ROM-version product of OLMS-63K family, which
employs Oki’s original CPU core nX-4/250.
FEATURES
• Rich instruction set
408 instructions
Transfer, rotate, increment/decrement, arithmetic operations, comparison, logic operations, mask
operations, bit operations, ROM table reference, stack operations, flag operations, branch, conditional
branch, call/return, control
• Rich selection of addressing modes
Indirect addressing of four data memory types, with current bank register, extra bank register, HL register
and XY register
Data memory bank internal direct addressing mode
• Processing speed
Two clocks per machine cycle, with most instructions executed in one machine cycle
Minimum instruction execution time : 61 µs (@32.768 kHz system clock)
1 µs (@2 MHz system clock)
• Clock generati o n cir cui t
Low-speed clock : Crystal oscillation or RC oscillation selected with mask option
(30 to 80 kHz)
High-speed clock : Ceramic oscillation or RC oscillation selected with software
(2 MHz max.)
• Pro g ram me mo ry spa ce
• ML63187B : 16 K words
• ML63189B : 32 K words
Basic instruction length is 16 bits/1 word
• Data memory space
• ML63187B : 1024 nibbles
• ML63189B : 1536 nibbles
• Stack level
Call stack level : 16 levels
Register stack level : 16 levels
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FEDL63187B-06
Semiconductor
1
ML63187B/63189B
• I/O ports
Input ports: Selectable as input with pull-up resistor/input with pull-down resistor/high-impedance
input
Input-output ports: Selectable as input with pull-up resistor/input with pull-down resistor/high-impedance
input
Selectable as P-channel open drain output/N-channel open drain output/CMOS
output/high-impedance output
Can be interfaced with external periph erals that use a different power supply than this device uses. V
power supply pin for ports.
Number of ports:
ML63187B
Input-output port : 2 ports × 4 bits
ML63189B
Input port : 1 port × 4 bits
Input-output port : 4 ports × 4 bits
• Melody output
Melody frequency : 529 to 2979 Hz
Tone length : 63 types
Tempo : 15 types
Melody data : Resides in the program memory
Buzzer driver signal output : 4 kHz
DD
is the
• LCD driver
Number of segments : 1024 Max. (64 SEG × 16 COM)
Duty : 1/1 to 1/16 duty
Bias : Selectable as 1/4 or 1/5 bias
regulator circuit built-in
Frame frequency : 64 Hz (at 1/16 duty) , 128 Hz (at 1/8 duty ) , 256 Hz (at 1/4 duty) ,
512Hz (at 1/2 duty) , 1024 Hz (at 1/1 duty )
Contrast : A maximum of 16 levels adjustable
Display modes : Selectable s all-ON mode/all-OFF mode/power down mode/normal
display mode adjustable contrast.
• System reset function
•
System reset by RESET pin (Built-in 2 kHz RESET sampling circuit can be selected by mask option)
•
System reset by power-on det ection (When not using 2 kHz RESET sampling c i rcuit)
•
System reset by detection that low-speed clock has stopped oscillation
• Battery check
Low-voltage supply check
The value of the judgment voltage is s elected by the software by setting the LD1 an d LD0 bits of BLDCON.
LD1 LD0 Judgment Voltage (V) Remarks
0 0 1.05 ± 0.10 Ta = 25°C
0 1 1.20 ± 0.10 Ta = 25°C
1 0 1.80 ± 0.10 Ta = 25°C
1 1 2.40 ± 0.10 Ta = 25°C
• Power supply backup
Backup circuit (voltage multiplier) enables operation at 0.9 V minimum
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Semiconductor
1
• Timers and counter
8-bit timer × 4
Selectable as auto-reload mode/capture mode/clock frequency measurement mode
Watchdog timer × 1
100 Hz timer × 1
Measurable in steps of 1/100 sec.
15-bit time base counter × 1
1, 2, 4, 8, 16, 32, 64, and 128 Hz signals can be read
• Shift register
Shift clock : 1 × or 1/2 × system clock, timer 1 overflow, external clock
Data length : 8 bits
• Interrupt sources
ML63187B
External interrupt : 2
Internal interrupt : 12 (watchdog timer interrupt is a nonmaskable interrupt)
ML63189B
External interrupt : 3
Internal interrupt : 12 (watchdog timer interrupt is a nonmaskable interrupt)
FEDL63187B-06
ML63187B/63189B
• Operating temperature
–20 to +70°C
• Operating vo lta ge
When backup used : 0.9 to 2.7 V
(Operati ng frequency: 30 to 80 kHz)
1.2 to 2.7 V
(Operating frequency: 300 to 500 kHz)
1.5 to 2.7 V
(Operating frequency: 200 kHz to 1 MHz)
When backup not used : 1.8 to 5.5 V
(Operating frequency: 200 kHz to 2 MHz)
• Package:
Chip (ML63187B: 111 pads , ML63189B: 123 pads): (Product name:ML63187B-xxxWA,
ML63189B-xxxWA)
128-pin plastic QFP (QFP128-P-1420-0.50-K) : (Product name:ML63187B-xxxGA,
ML63189B-xxxGA)
xxx indicates a code number.
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FEDL63187B-06
Semiconductor
1
ML63187B/63189B
MASK OPTION
In the ML63187B and ML63189B use the mask option to specify the following functions:
•
Low-Speeed clock oscillation circuit
Specify the crystal oscillation circuit or the RC oscillation circuit for the lo w-speed clock oscillation
circuit.
•
Reset signal sampling
Specify whether or not the reset signal will be sampled at 2 kHz.
When specifying “will carry out 2 kHz sampling,” hold the RESET pin at a “H” level for 1 ms or more.
To use the mask option, assign mask option data in the application program in accordan ce with the formats below.
The mask option area for each device is an application program execution disabled area.
Mask Option Data Assignment Format
Function Mask option area bit data Option to be selected
Low-speed clock oscillation circ ui t
(crystal oscillation circui t/RC osci llat ion circuit)
Reset signal sampling
(will/will not carry out 2 kHz sampling)
ML63187B:3FE0H bit 0
ML63189B:7FE0H bit 1
0 Crystal oscillation circuit
1 RC oscillation circuit
0 Will carry out 2 kHz sampling
1 Will not carry out 2 kHz sampling
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FEDL63187B-06
Semiconductor
1
ML63187B/63189B
BLOCK DIAGRAM (ML63187B)
An asterisk (*) indicates the port secondary function. indicates that the power is supplied to the circuits
corresponding to the signal names inside from V
(power supply for interface).
DDI
RESET
TST1
TST2
XT0
XT1
OSC0
OSC1
TIMING
CONTROL
SP
RSP
STACK
CAL : 16-level
REG : 16-level
RST
TST
OSC
CPU CORE
CBR
EBR
L
H
YX
ALU
INSTRUCTION
DECODER
INT
4
INT
1
INT
1
nX-4/250
100 HzTC
RA
A
CGZ
MIE
IR
RAM
1024N
INT187
TBC
BLD
WDT
PC
BUS
CONTROL
ROM
16 KW
INT
4
TIMER
8 bit × 4
INT
1
SFT
DATA BUS
INT
1
MELODY
TM0CAP/TM1CAP*
TM0OVF/TM1OVF*
T02CK*
T13CK*
SCLK*
SIN*
SOUT*
MD
MDB
V
V
CB1
CB2
V
V
V
V
V
C1
C2
V
DDH
DD1
DD2
DD3
DD4
DD5
DDL
DD
BACK
UP
BIAS
INT
2
I/O
PORT
LCD
&
DSPR
PB.0-PB.3
PE.0-PE.3
COM1-16
SEG0-63
V
DD1
V
SS
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FEDL63187B-06
Semiconductor
1
ML63187B/63189B
BLOCK DIAGRAM (ML63189B)
An asterisk (*) indicates the port secondary function. indicates that the power is supplied to the circuits
corresponding to the signal names inside from V
(power supply for interface).
DDI
RESET
TST1
TST2
XT0
XT1
OSC0
OSC1
TIMING
CONTROL
SP
RSP
STACK
CAL : 16-level
REG : 16-level
RST
TST
OSC
CPU CORE
CBR
EBR
L
H
YX
ALU
INSTRUCTION
DECODER
INT
4
INT
1
INT
1
nX-4/250
100 HzTC
CG
RAM
1536N
INT189
TBC
BLD
WDT
RA
A
MIE
IR
PC
Z
BUS
CONTROL
DATA BUS
INT
INT
4
INT
1
INT
1
1
ROM
32 KW
TIMER
8 bit × 4
SFT
MELODY
INPUT
PORT
TM0CAP/TM1CAP*
TM0OVF/TM1OVF*
T02CK*
T13CK*
SCLK*
SIN*
SOUT*
MD
MDB
P0.0-P0.3
V
V
CB1
CB2
V
V
V
V
V
C1
C2
V
DDH
DD1
DD2
DD3
DD4
DD5
DDL
DD
BACK
UP
BIAS
INT
2
I/O
PORT
LCD
&
DSPR
P9.0-P9.3
PA.0-PA.3
PB.0-PB.3
PE.0-PE.3
COM1-16
SEG0-63
V
DDI
V
SS
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Semiconductor
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PIN CONFIGURATION (TOP VIEW) (ML63187B)
SEG24
SEG25
SEG26
SEG27
SEG28
SEG29
SEG30
SEG31
SEG32
SEG33
SEG34
SEG35
SEG36
SEG37
115
116
117
118
119
120
121
122
123
124
125
126
127
(NC)
(NC)
(NC)
(NC)
SEG38
SEG39
SEG40
SEG41
SEG42
SEG43
SEG44
SEG45
SEG46
SEG47
SEG48
SEG49
SEG50
SEG51
SEG52
SEG53
SEG54
SEG55
SEG56
SEG57
SEG58
SEG59
SEG60
SEG61
SEG62
SEG63
COM9
COM10
COM1 1
COM12
(NC)
(NC)
(NC)
(NC)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
128
39
40
41
42
43
44
45
46
47
48
49
50
51
52
114
53
FEDL63187B-06
ML63187B/63189B
SEG12
SEG13
SEG14
SEG15
SEG16
SEG17
SEG18
SEG19
SEG20
SEG21
SEG22
SEG23
103
104
105
106
107
108
109
110
111
112
113
54
55
56
57
58
59
60
61
62
63
102
101
100
64
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
(NC)
(NC)
(NC)
(NC)
SEG11
SEG10
SEG9
SEG8
SEG7
SEG6
SEG5
SEG4
SEG3
SEG2
SEG1
SEG0
COM8
COM7
COM6
COM5
COM4
COM3
COM2
COM1
PB.3
PB.2
PB.1
PB.0
PE.3
PE.2
PE.1
PE.0
V
DDI
(NC)
(NC)
(NC)
(NC)
(NC)
SS
DD1
V
V
COM16
COM15
COM14
COM13
DD2
V
DD3
V
DD4
V
DD5
V
C1
C2
DDH
V
DD
DDL
V
CB2
CB1
V
OSC0
OSC1
XT0
XT1
RESET
TST2
TST1
MD
MDB
128-Pin Plastic QFP
Note: Pins marked as (NC) are no-connection pins which are left open.
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Semiconductor
1
PAD CONFIGURATION (ML63187B)
Pad Layout
FEDL63187B-06
ML63187B/63189B
83
V
DDI
PE.0 84
PE.1 85
PE.2 86
PE.3 87
PB.0 88
PB.1 89
PB.2 90
PB.3 91
COM1 92
COM2 93
COM3 94
COM4 95
COM5 96
COM6 97
COM7 98
COM8 99
SEG0 100
SEG1 101
SEG2 102
SEG3 103
SEG4 104
SEG5 105
SEG6 106
SEG7 107
SEG8 108
SEG9 109
SEG10 110
S EG11 111
DDL
DD
78 XT0
77 XT1
79 TST1
80 TST2
81 MD
82 MDB
73 V
72 V
74 OSC1
75 OSC0
76 RESET
70 CB1
71 CB2
DDH
67 C1
68 C2
69 V
DD5
66 V
DD3
DD4
63 V
64 V
65 V
DD1
DD2
62 V
SS
60 COM16
61 V
57 COM13
58 COM14
59 COM15
56 COM12
55 COM11
54 COM10
53 COM9
52 SEG63
51 SEG62
50 SEG61
49 SEG60
48 SEG59
47 SEG58
46 SEG57
Y
45 SEG56
44 SEG55
43 SEG54
42 SEG53
41 SEG52
40 SEG51
(0,0)
X
39 SEG50
ML63187
38 SEG49
37 SEG48
36 SEG47
35 SEG46
34 SEG45
33 SEG44
32 SEG43
31 SEG42
30 SEG41
29 SEG40
28 SEG39
27 SEG38
SEG17 6
SEG19 8
SEG18 7
SEG20 9
SEG33 22
SEG32 21
SEG31 20
SEG36 25
SEG35 24
SEG34 23
SEG37 26
SEG14 3
SEG13 2
SEG12 1
SEG16 5
SEG15 4
SEG30 19
SEG29 18
SEG28 17
SEG27 16
SEG26 15
SEG25 14
SEG24 13
SEG23 12
SEG22 11
SEG21 10
Chip size : 4.238 mm × 4.914 mm
Chip thickness : 350 µm (280 µm: available as required)
Coordinate origin : center of chip
Pad hole size : 100 µm × 100 µm
Pad size : 110 µm × 110 µm
Minimum pad pitch : 140 µm
Note: The chip substrate voltage is VSS.
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Page 9
FEDL63187B-06
Semiconductor
1
ML63187B/63189B
Pad Coordinates (ML63187B)
Center of chip: X = 0, Y = 0
Pad No. Pad Name X (µm) Y (µm) Pad No.Pad Name X (µm) Y (µm) Pad No. Pad Name X (µm) Y (µm)
1 SEG12 –1755 –2311 42 SEG53 1969 70 83 V
DDI
2 SEG13 –1615 –2311 43 SEG54 1969 211 84 PE.0 –1969 1755
3 SEG14 –1474 –2311 44 SEG55 1969 351 85 PE.1 –1969 1615
4 SEG15 –1334 –2311 45 SEG56 1969 491 86 PE.2 –1969 1474
5 SEG16 –1193 –2311 46 SEG57 1969 632 87 PE.3 –1969 1334
6 SEG17 –1053 –2311 47 SEG58 1969 772 88 PB.0 –1969 1193
7 SEG18 –913 –2311 48 SEG59 1969 913 89 PB.1 –1969 1053
8 SEG19 –772 –2311 49 SEG60 1969 1053 90 PB.2 –1969 913
9 SEG20 –632 –2311 50 SEG61 1969 1193 91 PB.3 –1969 772
10 SEG21 491 –2311 51 SEG62 1969 1334 92 COM1 –1969 632
11 SEG22 –351 –2311 52 SEG63 1969 l 474 93 COM2 –1969 491
12 SEG23 –211 –2311 53 COM9 1969 1615 94 COM3 –1969 351
13 SEG24 –70 –2311 54 COM10 1969 1755 95 COM4 –1969 211
14 SEG25 70 –2311 55 COM11 1969 1895 96 COM5 –1969 70
15 SEG26 211 –2311 56 COM12 1969 2036 97 COM6 –1969 –70
16 SEG27 351 –2311 57 COM13 1755 2311 98 COM7 –1969 –211
17 SEG28 491 –2311 58 COM14 1615 2311 99 COM8 –1969 –351
18 SEG29 632 –2311 59 COM15 1474 2311 100 SEG0 –1969 –491
19 SEG30 772 –2311 60 COM16 1334 2311 101 SEG1 –1969 –632
20 SEG31 913 –2311 61 V
21 SEG32 1053 –2311 62 V
22 SEG33 1193 –2311 63 V
23 SEG34 1334 –2311 64 V
24 SEG35 1474 –2311 65 V
25 SEG36 1615 –2311 66 V
SS
DD1
DD2
DD3
DD4
DD5
1193 2311 102 SEG2 –1969 –772
1053 2311 103 SEG3 –1969 –913
913 2311 104 SEG4 –1969 –1053
772 2311 105 SEG5 –1969 –1193
632 2311 106 SEG6 –1969 –1334
491 2311 107 SEG7 –1969 –1474
26 SEG37 1755 –2311 67 C1 351 2311 108 SEG8 –1969 –1615
27 SEG38 1969 –2036 68 C2 211 2311 109 SEG9 –1969 –1755
28 SEG39 1969 –1895 69 V
DDH
70 2311 110 SEG10 –1969 –1895
29 SEG40 1969 –1755 70 CB1 –70 2311 111 SEG11 –1969 –2036
30 SEG41 1969 –1615 71 CB2 –211 2311
31 SEG42 1969 –1474 72 V
32 SEG43 1969 –1334 73 V
DD
DDL
–351 2311
–491 2311
33 SEG44 1969 –1193 74 OSC1 –632 2311
34 SEG45 1969 –1053 75 OSC0 –772 2311
35 SEG46 1969 –913 76 RESET –913 2311
36 SEG47 1969 –772 77 XT1 –1053 2311
37 SEG48 1969 –632 78 XT0 –1193 2311
38 SEG49 1969 491 79 TST1 –1334 2311
39 SEG50 1969 –351 80 TST2 –1474 2311
40 SEG51 1969 –211 81 MD –1615 2311
41 SEG52 1969 –70 82 MDB –1755 2311
–1969 1895
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Page 10
Semiconductor
1
PIN CONFIGURATION (TOP VIEW) (ML63189B)
SEG17
SEG18
SEG19
SEG20
SEG21
SEG22
SEG23
SEG24
SEG25
SEG26
SEG27
SEG28
SEG29
116
117
118
119
120
121
122
123
124
125
126
127
(NC)
SEG30
SEG31
SEG32
SEG33
SEG34
SEG35
SEG36
SEG37
SEG38
SEG39
SEG40
SEG41
SEG42
SEG43
SEG44
SEG45
SEG46
SEG47
SEG48
SEG49
SEG50
SEG51
SEG52
SEG53
SEG54
SEG55
SEG56
SEG57
SEG58
SEG59
SEG60
SEG61
SEG62
SEG63
COM9
COM10
(NC)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
128
39
40
41
42
43
44
45
46
47
48
49
50
51
SEG16
52
FEDL63187B-06
ML63187B/63189B
SEG10
SEG11
SEG12
SEG13
SEG14
SEG15
109
110
111
112
113
114
115
58
57
56
55
54
53
SEG9
59
108
SEG8
60
SEG7
107
61
106
SEG6
105
62
SEG5
104
63
SEG4
103
102
101
100
64
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
(NC)
SEG3
SEG2
SEG1
SEG0
COM8
COM7
COM6
COM5
COM4
COM3
COM2
COM1
P0.3
P0.2
P0.1
P0.0
P9.3
P9.2
P9.1
P9.0
PA.3
PA.2
PA.1
PA.0
PB.3
PB.2
PB.1
PB.0
PE.3
PE.2
PE.1
PE.0
V
DDI
(NC)
MDB
MD
(NC)
C1
C2
DDH
V
CB1
DD2VDD1
V
VSSCOM16
COM15
COM14
COM13
COM12
COM1 1
V
V
DD5VDD4
DD3
DDL
VDDCB2
OSC1
V
OSC0
XT1
RESET
XT0
TST2
TST1
128-Pin Plastic QFP
Note: Pins marked as (NC) are no-connection pins which are left open.
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Page 11
Semiconductor
1
PAD CONFIGURATION (ML63189B)
Pad Layout
DDL
83 V
84 OSC1
85 OSC0
86 RESET
87 XT1
88 XT0
89 TST1
90 TST2
91 MD
92 MDB
DD
80 CB1
81 CB2
82 V
DDH
77 C1
78 C2
79 V
DD4
DD5
74 V
75 V
76 V
DD2
DD3
73 V
DD1
SS
70 COM16
71 V
72 V
FEDL63187B-06
ML63187B/63189B
65 COM11
66 COM12
67 COM13
68 COM14
69 COM15
64 COM10
63 COM9
V
93
DDI
PE.0 94
PE.1 95
PE.2 96
PE.3 97
PB.0 98
PB.1 99
PB.2 100
PB.3 101
PA.0 102
PA.1 103
PA.2 104
PA.3 105
P9.0 106
P9.1 107
P9.2 108
P9.3 109
P0.0 110
P0.1 111
P0.2 112
P0.3 113
COM1 114
COM2 115
COM3 116
COM4 117
COM5 118
COM6 119
COM7 120
COM8 121
SEG0 122
SEG1 123
(0,0)
62 SEG63
61 SEG62
60 SEG61
ML63189B
59 SEG60
58 SEG59
57 SEG58
56 SEG57
55 SEG56
54 SEG55
53 SEG54
52 SEG53
51 SEG52
Y
50 SEG51
49 SEG50
48 SEG49
X
47 SEG48
46 SEG47
45 SEG46
44 SEG45
43 SEG44
42 SEG43
41 SEG42
40 SEG41
39 SEG40
38 SEG39
37 SEG38
36 SEG37
35 SEG36
34 SEG35
33 SEG34
32 SEG33
31 SEG32
SEG2 1
SEG8 7
SEG7 6
SEG5 4
SEG3 2
SEG4 3
SEG6 5
SEG9 8
SEG12 11
SEG11 10
SEG10 9
SEG14 13
SEG13 12
SEG15 14
SEG18 17
SEG17 16
SEG16 15
SEG21 20
SEG20 19
SEG19 18
SEG24 23
SEG23 22
SEG22 21
SEG27 26
SEG26 25
SEG25 24
SEG28 27
Chip size : 4.81 mm × 5.20 mm
Chip thickness : 350 µm (280 µm: available as required)
Coordinate origin : center of chip
Pad hole size : 100 µm × 100 µm
Pad size : 110 µm × 110 µm
Minimum pad pitch : 140 µm
Note: The chip substrate voltage is VSS.
SEG30 29
SEG29 28
SEG31 30
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Page 12
FEDL63187B-06
Semiconductor
1
ML63187B/63189B
Pad Coordinates (ML63189B)
Center of chip: X = 0, Y = 0
Pad No. Pad Name X (µm) Y (µm) Pad No. Pad Name X (µm) Y (µm) Pad No. Pad Name X (µm) Y (µm)
1 SEG2 –2259 –2438 42 SEG43 2259 –632 83 V
DDL
2 SEG3 –1895 –2438 43 SEG44 2259 –491 84 OSC1 –913 2438
3 SEG4 –1755 –2438 44 SEG45 2259 –351 85 OSC0 –1053 2438
4 SEG5 –1615 –2438 45 SEG46 2259 –211 86 RESET –1193 2438
5 SEG6 –1474 –2438 46 SEG47 2259 –70 87 XT1 –1334 2438
6 SEG7 –1334 –2438 47 SEG48 2259 70 88 XT0 –1474 2438
7 SEG8 –1193 –2438 48 SEG49 2259 211 89 TST1 –1615 2438
8 SEG9 –1053 –2438 49 SEG50 2259 351 90 TST2 –1755 2438
9 SEG10 –913 –2438 50 SEG51 2259 491 91 MD –1895 2438
10 SEG11 –772 –2438 51 SEG52 2259 632 92 MDB –2259 2438
11 SEG12 –632 –2438 52 SEG53 2259 772 93 V
DDI
12 SEG13 –491 –2438 53 SEG54 2259 913 94 PE.0 –2259 1895
13 SEG14 –351 –2438 54 SEG55 2259 1053 95 PE.1 –2259 1755
14 SEG15 –211 –2438 55 SEG56 2259 1193 96 PE.2 –2259 1615
15 SEG16 –70 –2438 56 SEG57 2259 1334 97 PE.3 –2259 1474
16 SEG17 70 –2438 57 SEG58 2259 1474 98 PB.0 – 2259 1334
17 SEG18 211 –2438 58 SEG59 2259 1615 99 PB.1 –2259 1193
18 SEG19 351 –2438 59 SEG60 2259 1755 100 PB.2 –2259 1053
19 SEG20 491 –2438 60 SEG61 2259 1895 101 PB.3 –2259 913
20 SEG21 632 –2438 61 SEG62 2259 2036 102 PA.0 –2259 772
21 SEG22 772 –2438 62 SEG63 2259 2176 103 PA.1 –2259 632
22 SEG23 913 –2438 63 COM9 2259 2438 104 PA.2 –2259 491
23 SEG24 1053 –2438 64 COM10 1895 2438 105 PA.3 –2259 351
24 SEG25 1193 –2438 65 COM11 1755 2438 106 P9.0 –2259 211
25 SEG26 1334 –2438 66 COM12 1615 2438 107 P9.1 –2259 70
26 SEG27 1474 –2438 67 COM13 1474 2438 108 P9.2 –2259 –70
27 SEG28 1615 –2438 68 COM14 1334 2438 109 P9.3 –2259 –211
28 SEG29 1755 –2438 69 COM15 1193 2438 110 P0.0 –2259 –351
29 SEG30 1895 –2438 70 COM16 1053 2438 111 P0.1 –2259 –491
30 SEG31 2259 –2438 71 V
31 SEG32 2259 –2176 72 V
32 SEG33 2259 –2036 73 V
33 SEG34 2259 –1895 74 V
34 SEG35 2259 –1755 75 V
35 SEG36 2259 –1615 76 V
SS
DD1
DD2
DD3
DD4
DD5
913 2438 112 P0.2 –2259 –632
772 2438 113 P0.3 –2259 –772
632 2438 114 COM1 –2259 –913
491 2438 115 COM2 –2259 –1053
351 2438 116 COM3 –2259 –1193
211 2438 117 COM4 –2259 –1334
36 SEG37 2259 –1474 77 C1 70 2438 118 COM5 –2259 –1474
37 SEG38 2259 –1334 78 C2 –70 2438 119 COM6 –2259 –1615
38 SEG39 2259 –1193 79 V
DDH
–211 2438 120 COM7 –2259 –1755
39 SEG40 2259 –1053 80 CB1 –351 2438 121 COM8 –2259 –1895
40 SEG41 2259 –913 81 CB2 –491 2438 122 SEG0 –2259 –2036
41 SEG42 2259 –772 82 V
DD
–632 2438 123 SEG1 –2259 –2176
–772 2438
–2259 2132
12/36
Page 13
FEDL63187B-06
Semiconductor
1
ML63187B/63189B
PIN DESCRIPTIONS
The basic functions of each pin of the ML63187B, ML63189B are described in Table 1.
A symbol with a slash (/) denotes a pin that has a secondary function.
Refer to Table 2 for secondary functions.
For type, “—” denotes a power supply pin, “I” an input pin, “O” an output pin, and “I/O” an input-output pin.
Table 1 Pin Descriptions (Basic Functions)
Function Symbol
V
DD
V
SS
V
DD1
V
DD2
V
DD3
V
DD4
V
DD5
C1 49 51 67 77 —
C2 50 52 68 78 —
Power
Supply
V
DDI
V
DDL
V
DDH
CB1 52 54 70 80 —
CB2 53 55 71 81 —
XT0 60 62 78 88 I
Osci-
llation
XT1 59 61 77 87 O
OSC0 57 59 75 85 I
OSC1 56 58 74 84 O
Pin No. Pad No.
ML63187B ML63189B ML63187B ML63189B
Type Description
54 56 72 82 — Positive power supply
43 45 61 71 — Negative power supply
44 46 62 72
45 47 63 73
46 48 64 74
47 49 65 75
Power supply pins for LCD bias (internally
generated)
Capacitors (0.1 µF) should be connected
—
between these pins and V
48 50 66 76
Capacitor connection pins for LCD bias
generation
A capacitor (0.1 µF) should be connected
between C1 and C2.
Positive power supply pin for external interface
70 69 83 93
—
(power supply for input, and input-o utpu t port s)
Positive power supply pin for internal logic
55 57 73 83 —
(internally generated)
A capacitor (0.1 µF) should be connected
between this pin and V
Voltage multiplier pin for power supply backup
(internally generated)
51 53 69 79
—
A capacitor (1.0 µF) should be connected
between this pin and VSS.
Pins to connect a capacitor for voltage
multiplier
A capacitor (1.0 µF) should be connected
between CB1 and CB2.
Low-speed clock oscillation pin s
An option for using crystal oscillation or RC
oscillation is chosen by the mask option.
If the crystal oscillation is chosen, a crystal
should be connected between XT0 and XT1,
and capacitor (C
between XT0 and V
If the RC oscillation is chosen, external
oscillation resistor (R
between XT0 and XT1.
High-speed clock oscillation pins
A ceramic resonator and capacitors (C
or external oscillation resistor (R
connected to these pins.
.
SS
.
SS
) should be connected
G
.
SS
) should be connected
OSL
) should be
OSH
, CL1 )
L0
13/36
Page 14
1
Semiconductor
FEDL63187B-06
ML63187B/63189B
Table 1 Pin Descriptions (Basic Functions) (continued)
Function Symbol
TST1 61 63 79 89 I
Test
TST2 62 64 80 90 I
Reset
Melody
Port
RESET 58 60 76 86 I
MD 63 66 81 91 O
MDB 64678292O
P0.0/INT5 86 110
P0.1/INT5 87 111
P0.2/INT5 88 112
P0.3/INT5
P9.0 82 106
P9.1 83 107
P9.2 84 108
P9.3
PA.0
PA.1 79 103
PA.2 80 104
PA.3
PB.0/INT0/
TM0CAP/
TM0OVF
PB.1/INT0/
TM1CAP/
TM1OVF
PB.2/INT0/
T02CK
PB.3/INT0/
T13CK
PE.0/SIN
PE.1/SOUT 72 71 85 95
PE.2/SCLK 73 72 86 96
PE.3/INT2
Pin No. Pad No.
ML63187B ML63189B ML63187B ML63189B
—
89
—
85
78 102
—
81
75 74 88 98
76 75 89 99
77 76 90 100
78 77 91 101
71 70 84 94
74 73 87 97
—
113
—
109
—
105
Type Description
Input pins for testing
A pull-down resistor is interna lly co nne cte d to
these pins.
The user cannot use these pins.
Reset input pin
Setting this pin to “H” Ievel puts this device
into a reset state.
Then, setting this pin to “L” Ievel starts
executing an instru cti on fr om address 00 00H.
A pull-down resistor is interna lly co nne cte d to
this pin.
An option of using RESET sampling circuit or
not is chosen by the mask option.
When using RESET sampling circuit, the
system reset mode is entered by holding the
RESET pin at a “H” Ievel for 1 ms or more.
Melody output pin (non-inverted output)
Melody output pin (inverted output)
4-bit input ports
Pull-up resistor input, pu ll-down resi stor inpu t,
or high-impedance input is selectable for
I
each bit.
Applied to the ML63189B only.
4-bit input-output ports
In input mode, pull-up resistor input, pull-
I/O
down resistor input, or high-impedance input
is selectable for each bit.
In output mode, P-channel open dra in o utp ut,
N-channel open drain output, CMOS output,
or high-impedance output is selectable for
I/O
each bit.
P9.0 to P9.3 and PA.0 to PA.3 are applied to
the ML63189B only.
I/O
I/O
14/36
Page 15
1
Semiconductor
FEDL63187B-06
ML63187B/63189B
Table 1 Pin Descriptions (Basic Functions) (continued)
Function Symbol
COM1 79 90 92 114
COM2 80 91 93 115
COM3 81 92 94 116
COM4 82 93 95 117
COM5 83 94 96 118
COM6 84 95 97 119
COM7 85 96 98 120
COM8 86 97 99 121
COM9 31 36 53 63
COM1032375464
COM1133395565
COM1234405666
COM13
COM14
COM15
COM1642446070
SEG0 87 98 100 122
SEG1
SEG2
SEG3
LCD
SEG4
SEG5 92 104 105 4
SEG6 93 105 106 5
SEG7
SEG8
SEG9
SEG10
SEG11 98 110 111 10
SEG12 103 111 1 11
SEG13
SEG14
SEG15
SEG16
SEG17 108 116 6 16
SEG18 109 117 7 17
SEG19
SEG20
SEG21
SEG22
SEG23 114 122 12 22
SEG24 115 123 13 23
Pin No. Pad No.
ML63187B ML63189B ML63187B ML63189B
39 41 57 67
40 42 58 68
41 43 59 69
88 99 101 123
89 100 102 1
90 101 103 2
91 103 104 3
94 106 107 6
95 107 108 7
96 108 109 8
97 109 110 9
104 112 2 12
105 113 3 13
106 114 4 14
107 115 5 15
110 118 8 18
111 119 9 19
112 120 10 20
113 121 11 21
Type Description
LCD common signal output pins
O
LCD segment signal output pins
O
15/36
Page 16
1
Semiconductor
FEDL63187B-06
ML63187B/63189B
Table 1 Pin Descriptions (Basic Functions) (continued)
Function Symbol
SEG25 116 124 14 24
SEG26
SEG27
SEG28 119 127 17 27
SEG29 120 128 18 28
SEG30 121 2 19 29
SEG31 122 3 20 30
SEG32 123 4 21 31
SEG33 124 5 22 32
SEG34 125 6 23 33
SEG35 126 7 24 34
SEG36 127 8 25 35
SEG37
SEG38
SEG39
SEG40
SEG41 8 13 30 40
SEG42 9 14 31 41
SEG43
LCD
SEG44
SEG45
SEG46
SEG4714193646
SEG4815203747
SEG49
SEG50
SEG51
SEG52
SEG5320254252
SEG5421264353
SEG55
SEG56
SEG57
SEG58
SEG5926314858
SEG6027324959
SEG61
SEG62
SEG63
Pin No. Pad No.
ML63187B ML63189B ML63187B ML63189B
117
118
128 9 26 36
5 102737
6 112838
7 122939
10 15 32 42
11 16 33 43
12 17 34 44
13 18 35 45
16 21 38 48
17 22 39 49
18 23 40 50
19 24 41 51
22 27 44 54
23 28 45 55
24 29 46 56
25 30 47 57
28 33 50 60
29 34 51 61
30 35 52 62
125 15 25
126 16 26
Type Description
LCD segment signal output pins
O
16/36
Page 17
Semiconductor
1
Table 2 shows the secondary functions of each pin of the ML63187B, ML63189B.
Table 2 Pin Descriptions (Secondary Functions)
FEDL63187B-06
ML63187B/63189B
Function Symbol
PB.0/INT0 75 74 88 98
PB.1/INT0
PB.2/INT0
PB.3/INT0 78 77 91 101
External
Interrupt
Capture
PE.3/INT2 74 73 87 97 I
P0.0/INT5 86 110
P0.1/INT5 87 111
P0.2/INT5 88 112
P0.3/INT5
PB.0/TM0CAP 75 74 88 98 I Timer 0 capture input pin
PB.1/TM1CAP
PB.0/TM0OVF 75 74 88 98 O Timer 0 overflow flag output pin
Pin No. Pad No.
ML63187B ML63189B ML63187B ML63189B
76
77
—
76
75 89 99
76 90 100
—
89
75 89 99 I Timer 1 capture input pin
113
Type Description
External 0 interrupt input pins
The change of input signal level causes an
interrupt to occur.
I
The Port B Interrupt Enable register
(PBIE) enables or disables an interrupt for
each bit.
External 2 interrupt input pin
The change of input signal level causes an
interrupt to occur.
External 5 interrupt input pins
The change of input signal level causes an
interrupt to occur.
I
The Port 0 Interrupt Enable register (P0IE)
enable or disable an interrupt for each bit.
Applied to the ML63189B only.
Timer
Shift
Register
PB.1/TM1OVF 76 75 89
PB.2/T02CK 77 76 90 100 I
PB.3/T13CK 78 77 91 101 I
PE.0/SIN 71 70 84 94 I
PE.1/SOUT 72 71 85 95 O
PE.2/SCLK 73 72 86 96 I/O
99 O Timer 1 overflow flag output pin
External clock input pin for timer 0 and
timer 2
External clock input pin for timer 1 and
timer 3
Shift register receive data input pin
Shift register transmit data output pin
Shift register clock input-output pin
Clock output when this device i s used as a
master processor.
17/36
Page 18
Semiconductor
1
ABSOLUTE MAXIMUM RATINGS
Parameter Symbol Condition Rating Unit
Power Supply Voltage 1 V
Power Supply Voltage 2 V
Power Supply Voltage 3 V
Power Supply Voltage 4 V
Power Supply Voltage 5 V
Power Supply Voltage 6 V
Power Supply Voltage 7 V
Power Supply Voltage 8 V
Power Supply Voltage 9 V
Input Voltage 1 V
Input Voltage 2 V
Output Voltage 1 V
Output Voltage 2 V
Output Voltage 3 V
Output Voltage 4 V
Output Voltage 5 V
Output Voltage 6 V
Output Voltage 7 V
Output Voltage 8 V
Storage Temperature T
DD1
DD2
DD3
DD4
DD5
DD
DDI
DDH
DDL
IN1
IN2
OUT1
OUT2
OUT3
OUT4
OUT5
OUT6
OUT7
OUT8
STG
Ta = 25°C –0.3 to +1.6 V
Ta = 25°C –0.3 to +2.9 V
Ta = 25°C –0.3 to +4.2 V
Ta = 25°C –0.3 to +5.5 V
Ta = 25°C –0.3 to +6.8 V
Ta = 25°C –0.3 to +6.0 V
Ta = 25°C –0.3 to +6.0 V
Ta = 25°C –0.3 to +6.0 V
Ta = 25°C –0.3 to +6.0 V
VDD Input, Ta = 25°C –0.3 to V
V
Input, Ta = 25°C –0.3 to V
DDI
V
Output, Ta = 25°C –0.3 to V
DD1
V
Output, Ta = 25°C –0.3 to V
DD2
V
Output, Ta = 25°C –0.3 to V
DD3
V
Output, Ta = 25°C –0.3 to V
DD4
V
Output, Ta = 25°C –0.3 to V
DD5
VDD Output, Ta = 25°C –0.3 to V
V
Output, Ta = 25°C –0.3 to V
DDI
V
Output, Ta = 25°C –0.3 to V
DDH
DD
DDI
DD1
DD2
DD3
DD4
DD5
DD
DDI
DDH
— –55 to +150 °C
FEDL63187B-06
ML63187B/63189B
(VSS = 0 V)
+0.3 V
+0.3 V
+0.3 V
+0.3 V
+0.3 V
+0.3 V
+0.3 V
+0.3 V
+0.3 V
+0.3 V
18/36
Page 19
Semiconductor
1
RECOMMENDED OPERATING CONDITIONS
• When backup is used
Parameter Symbol Condition Range Unit
Operating Temperature T
Operating Voltage
Crystal Oscillation Frequency f
Low-Speed RC Oscillation
Frequency
High-speed RC Oscillation
Frequency
V
V
f
ROSL
f
ROSH
CM
DD
DDI
XT
op
CG = 5 to 25 pF 32.768 to 76.8 kHz
R
R
R
V
DD
V
DD
V
DD
V
DD
V
= 1.2 to 2.7 V
DD
ML63187B/63189B
— –20 to +70 °C
— 0.9 to 2.7 V
— 0.9 to 5.5 V
= 1.0 MΩ 36 ±30%
OSL
= 1.1 MΩ 33 ±30%
OSL
= 1.2 MΩ 30 ±30%
OSL
= 0.9 to 1.2 V Not applied
= 1.2 to 2.7 V 300k to 500kCeramic Oscillation Frequency f
= 1.5 to 2.7 V 200k to 1M
= 0.9 to 1.2 V Not applied
R
= 400 kΩ 200k ±30%
OSH
R
= 100 kΩ 700k ±30%
OSH
R
= 75 kΩ 1M ±30%
OSH
FEDL63187B-06
(VSS = 0 V)
kHz
Hz
Hz
• When backup is not used
Parameter Symbol Condition Range Unit
Operating Temperature T
Operating Voltage
Crystal Oscillation Frequency f
Low-Speed RC Oscillation
Frequency
Ceramic Oscillation Frequency f
High-speed RC Oscillation
Frequency
V
V
f
ROSL
f
ROSH
XT
CM
DD
DDI
(VSS = 0 V)
op
— –20 to +70 °C
— 1.8 to 5.5
— 1.8 to 5.5
V
CG = 5 to 25 pF 32.768 to 76.8 kHz
R
= 1.0 MΩ 36 ±30%
OSL
R
R
V
DD
= 1.8 to 5.5 V
DD
V
= 1.8 to 3.5 V, R
DD
= 1.1 MΩ 33 ±30%
OSL
= 1.2 MΩ 30 ±30%
OSL
= 1.8 to 5.5 V 200k to 2M Hz
R
= 100 kΩ 700k ±30%
OSH
R
= 75 kΩ 1M ±30%V
OSH
R
= 51 kΩ 1.35M ±30%
OSH
= 30 kΩ 2M ±30%
OSH
kHz
Hz
19/36
Page 20
Semiconductor
[
]
[
]
1
• Typical characteristics of low-speed RC oscillatio n
When backup is used/backup is not used (V
1000
kHz
ROSL
f
100
10
100 1000 10000
DD
= V
= 1.5 V/VDD = V
DDI
= 3.0 V)
DDI
Reference data
R
[kΩ]
OSL
FEDL63187B-06
ML63187B/63189B
• Typical characteristics of high-speed RC oscillation
= V
When backup is used (V
10000
kHz
ROSH
f
1000
100
DD
10 100 1000
= 1.5 V)
DDI
Reference data
R
[kΩ]
OSH
20/36
Page 21
Semiconductor
[
]
1
• Typical characteristics of high-speed RC oscillation
= V
When backup is not used (V
10000
kHz
ROSH
f
1000
DD
= 3.0 V)
DDI
FEDL63187B-06
ML63187B/63189B
Reference data
100
10 100 1000
R
[kΩ]
OSH
21/36
Page 22
Semiconductor
1
ELECTRICAL CHARACTERISTICS
DC Characteristics (1)
Parameter Symbol Condition Min. Typ. Max. Unit
V
Voltage V
DD2
V
Voltage Temperature
DD2
Deviation
V
Voltage V
DD1
V
Voltage V
DD3
V
Voltage V
DD4
V
Voltage V
DD5
V
Voltage (Backup used) V
DDH
V
Voltage V
DDL
Crystal Oscillation Start
Voltage
Crystal Oscillation Hold
Voltage
Crystal Oscillation Stop
Detect Time
External Crystal Oscillator
Capacitance
Internal Crystal Oscillator
Capacitance
External Ceramic Oscillator
Capacitance
Internal RC Oscillator
Capacitance
POR Voltage V
Non-POR Voltage V
BLD Judgment Voltage V
BLD Judgment Voltage
Temperature Deviation
(VDD = V
DD2
∆V
DD2
DD1
DD3
DD4
DD5
DDH
DDL
V
STA
V
HOLD
T
STOP
C
G
C
D
C
L0,1
C
OS
POR1
POR2
BLDC
∆V
BLDC
= 0.9 to 5.5 V, VSS = 0 V, Ta = –20 to +70°C unless otherwise specified)
DDI
1/5 bias, 1/4 bias (Ta = 25°C) 1.7 1.8 1.9 V
1/5 bias, 1/4 bias
1/4 bias (connect V
High-speed clock oscillation
High-speed clock oscillation
(Ceramic oscillation, 1 MHz)
High-speed clock oscillation
High-speed clock oscillation
(V
Oscillation start time:
within 5 seconds
Backup not used 1.7 — — V
(Murata MFG.-make) used
LD1 = 1, LD0 = 1, Ta = 25°C 2.30 2.40 2.50
LD1 = 1, LD0 = 0, Ta = 25°C 1.70 1.80 1.90
LD1 = 0, LD0 = 1, Ta = 25°C 1.10 1.20 1.30
LD1 = 0, LD0 = 0, Ta = 25°C 0.95 1.05 1.15
V
= 2.40 V (LD1 = 1, LD0 = 1) — –3.5 —
BLDC
V
= 1.80 V (LD1 = 1, LD0 = 0) — –2.3 —
BLDC
V
= 1.20 V (LD1 = 0, LD0 = 1) — –1.6 —
BLDC
V
= 1.05 V (LD1 = 0, LD0 = 0) — –1.2 —
BLDC
FEDL63187B-06
ML63187B/63189B
Measuring
Circuit
——–4—
1/5 bias
1/5 bias
1/4 bias
1/5 bias
1/4 bias
stopped
DD3
and V
Typ. – 0.1 1/2 × V
Typ. – 0.3 3/2 × V
Typ. – 0.2
)
DD2
Typ. – 0.4 2 × V
Typ. – 0.3 3/2 × V
Typ. – 0.5 5/2 × V
Typ. – 0.4 2 × V
2.8 — 3.0 V
V
DD2
DD2
DD2
DD2
DD2
DD2
DD2
Typ. + 0.1
Typ. + 0.3
Typ. + 0.2
Typ. + 0.4
Typ. + 0.3
Typ. + 0.5
Typ. + 0.4
VDD = 1.5 V
2.0 — 2.7 V
V
= 1.5 V
DD
stopped
= 1.2 to 5.5 V)
DD
1.0 1.5 2.0 V
1.2 — 5.5 V
1.2 — — V
Backup 0.9 — — V
— 0.1 — 5.0 ms
—5—25pF
—202530pF
CSA2.00MG
—30—pF
V
= 3.0 V
DD
— 8 12 16 pF
V
= 1.5 V 0 — 0.4 V
DD
V
= 3.0 V 0 — 0.7 V
DD
V
= 1.5 V 1.2 — 1.5 V
DD
V
= 3.0 V 2.0 — 3.0 V
DD
mV/°C
V
V
V
V
1
V
—
mV/°C
22/36
Page 23
1
Semiconductor
FEDL63187B-06
ML63187B/63189B
Notes:1. “T
occurs.
2. “POR” denotes Power On Reset.
3. “V
4. “V
to V
” indicates that if the c rystal oscillat or stops over th e value of T
STOP
” indicates that POR occurs when VDD falls from VDD to V
POR1
” indicates that POR does not occur when VDD falls from VDD to V
POR2
.
DD
, the system reset
STOP
and again rises up to VDD.
POR1
and again rises up
POR2
23/36
Page 24
Semiconductor
1
ML63187B/63189B
DC Characteristics (2)
• When backup is used
(32.768 kHz crystal is used for the low-speed clock, VDD = V
LCD contrast (DSPCNT) = 0H, Ta = –20 to +70°C unless otherwise specified)
Parameter Symbol Condition Min. Typ. Max. Unit
Supply Current 1 I
DD1
CPU is in HALT state.
(High-speed clock
oscillation stopped)
Ta = –20 to +50°C — 5 6.5
Ta = –20 to +70°C — 5 10
CPU is in HALT state.
Ta = –20 to +50°C — 4 5
Ta = –20 to +70°C — 4 8
Supply Current 2 I
DD2
LCD is in Power Down
mood.
(High-speed clock
oscillation stopped)
Supply Current 3 I
DD3
CPU is in operation at
low-speed oscillation.
(High-speed clock
oscillation stopped)
Ta = –20 to +50°C — 16 18
Ta = –20 to +70°C — 16 20
CPU is in operation at high-speed oscillation
Supply Current 4 I
Supply Current 5 I
DD4
DD5
(approx. 700 kHz RC oscillation,
R
= 100 kΩ )
OSH
CPU is in operation at high-speed oscillation
(Ceramic oscillation, 1 MHz)
= 1.5 V, VSS = 0 V, 1/5 bia s,
DDI
— 800 1000 µA
— 700 850 µA
FEDL63187B-06
Measuring
Circuit
µA
µA
1
µA
• When backup is not used
(32.768 kHz crystal is used for the low-speed clock, VDD = V
LCD contrast (DSPCNT) = 0H, Ta = –20 to +70°C unless otherwise specified)
Parameter Symbol Condition Min. Typ. Max. Unit
Supply Current 1 I
DD1
CPU is in HALT state.
(High-speed clock
oscillation stopped)
Ta = –20 to +50°C — 2.2 3
Ta = –20 to +70°C — 2.2 5
CPU is in HALT state.
Ta = –20 to +50°C — 1.8 2.5
Ta = –20 to +70°C — 1.8 4
Supply Current 2 I
DD2
LCD is in Power Down
mood.
(High-speed clock
oscillation stopped)
Supply Current 3 I
DD3
CPU is in operation at
low-speed oscillation.
(High-speed clock
oscillation stopped)
Ta = –20 to +50°C — 7.5 9
Ta = –20 to +70°C — 7.5 12
CPU is in operation at high-speed oscillation
Supply Current 4 I
Supply Current 5 I
DD4
DD5
(approx. 700 kHz RC oscillation,
R
= 100 kΩ )
OSH
CPU is in operation at high-speed oscillation
(Ceramic oscillation, 2 MHz)
= 3.0 V, VSS = 0 V, 1/5 bia s,
DDI
— 550 700 µA
— 850 1000 µA
Measuring
Circuit
µA
µA
1
µA
24/36
Page 25
Semiconductor
1
DC Characteristics (3)
FEDL63187B-06
ML63187B/63189B
(VDD = V
DDI
= V
= 3.0 V, V
DDH
V
= 1.1 V, V
DD1
= 5.5 V, Ta = –20 to +70°C unless otherwise specified)
DD5
= 2.2 V, V
DD2
= 3.3 V, V
DD3
Parameter Symbol Condition Min. Typ. Max. Unit
V
Output Current 1
(P9.0 to P9.3)*
(PA.0 to PA.3)*
(PB.0 to PB.3)
(PE.0 to PE.3)
Output Current 2
(MD, MDB)
I
I
OH1
OL1
OH2
V
OH1
V
OL1
V
OH2
= V
DDI
= 0.5 V
= V
DD
– 0.5 V
– 0.7 V
DDI
V
DDI
V
DDI
V
DDI
V
DDI
V
DDI
= 1.5 V
= 3.0 V
= 5.0 V
= 1.5 V
= 3.0 V
= 5.0 V
–2.5 –1.4 –0.4 mA
–6.0 –3.5 –1.0 mA
–8.5 –5.0 –1.5 mA
0.4 1.4 2.5 m A
1.0 3.0 6.0 m A
1.5 3.7 8.5 m A
VDD = 1.5 V –4.0 –2.0 –0.5 mA
VDD = 3.0 V –11.0 –6.0 –2.0 mAI
V
= V
DD
= 5.0 V –14.0 –9.0 –4.0 mA
DDH
VDD = 1.5 V 0.5 2.0 4.0 mA
VDD = 3.0 V 2.0 5.5 11.0 mA
V
= V
DD
Ievel) — — –4 µA
DD5
DD4
DD4
DD3
DD3
DD2
DD2
DD1
DD1
Ievel) 4 — — µA
SS
VDD = V
V
= V
DD
VDD = V
V
= V
DD
VDD = V
V
= V
DD
VDD = V
V
= V
DD
= 5.0 V 4.0 7.0 14.0 mA
DDH
Ievel) 4 — — µA
Ievel) — — –4 µA
Ievel) 4 — — µA
Ievel) — — –4 µA
Ievel) 4 — — µA
Ievel) — — –4 µA
Ievel) 4 — — µA
Ievel) — — –4 µA
= 3.0 V –2.5 –1.3 –0.25 mA
DDH
= 5.0 V –3.5 –1.7 –0.5 mA
DDH
= 3.0 V 0.25 1.5 2.5 mA
DDH
= 5.0 V 0.5 1.8 3.5 mA
DDH
= 3.0 V –500 –250 –100 µA
DDH
= 5.0 V –800 –350 –200 µA
DDH
= 3.0 V 200 500 800 µA
DDH
= 5.0 V 400 700 1000 µA
DDH
Output Current 3
(SEG0 to
SEG63)
(COM1 to
COM16)
Output Current 4
(OSC1)
I
I
OH3
I
OHM3
I
OHM3S
I
OMH3
I
OMH3S
I
OML3
I
OML3SVOML3S
I
OLM3
I
OLM3SVOLM3S
I
I
OH4R
I
OL4R
I
OH4C
I
OL4C
V
OL2
OL3
OL2
V
OH3
V
OHM3
V
OHM3S
V
OMH3
V
OMH3S
V
OML3
V
OLM3
V
OL3
V
OH4R
(RC oscillation)
V
OL4R
(RC oscillation)
V
OH4C
(ceramic oscillation)
V
OL4C
(ceramic oscillation)
= 0.7 V
= V
– 0.2 V (V
DD5
= V
+ 0.2 V (V
DD4
= V
– 0.2 V (V
DD4
= V
+ 0.2 V (V
DD3
= V
– 0.2 V (V
DD3
= V
+ 0.2 V (V
DD2
= V
– 0.2 V (V
DD2
= V
+ 0.2 V (V
DD1
= V
– 0.2 V (V
DD1
= VSS + 0.2 V (V
= V
– 0.5 V
DDH
= 0.5 V
= V
– 0.5 V
DDH
= 0.5 V
Output Leakage
Current
I
OOH
VOH = V
DDI
——0.3µA
(P9.0 to P9.3)*
(PA.0 to PA.3)*
(PB.0 to PB.3)
I
OOL
VOL = V
SS
–0.3 — — µA
(PE.0 to PE.3)
*: Applied to the ML63189B only.
= 4.4 V,
DD4
Mea-
suring
Circuit
2
25/36
Page 26
Semiconductor
1
DC Characteristics (4)
FEDL63187B-06
ML63187B/63189B
(VDD = V
DDI
= V
= 3.0 V, V
DDH
V
= 1.1 V, V
DD1
= 5.5 V, Ta = –20 to +70°C unless otherwise specified)
DD5
= 2.2 V, V
DD2
= 3.3 V, V
DD3
Parameter Symbol Condition Min. Typ. Max. Unit
V
Input Current 1
(P0.0 to P0.3)*
(P9.0 to P9.3)*
(PA.0 to PA.3)*
(PB.0 to PB.3)
(PE.0 to PE.3)
Input Current 2
(OSC0)
Input Current 3
(RESET)
Input Current 4
(TST1, TST2)
I
I
I
I
I
I
I
IH1
IL1
IH1Z
IL1Z
I
IL2
IH2R
IL2R
IH2C
IL2C
IH3
I
IL3
IH4
I
IL4
V
= V
OH1
DDI
(when pulled up)
V
= V
IL1
SS
(when pulled up)
V
= V
IH1
V
IL1
V
IL2
(in a high impedance state) 0 — 1 µA
DDI
= VSS (in a high impedance state) –1 — 0 µA
= V
SS
(when pulled up)
V
= V
IH2R
V
IL2R
V
IH2C
(RC oscillation) 0 — 1 µA
DDH
= VSS (RC oscillation) –1 — 0 µA
= V
DDH
(ceramic oscill ation )
V
= V
IL2C
SS
(ceramic oscill ation )
V
= V
IH3
DD
V
= V
IL3
SS
V
= V
IH4
DD
V
= V
IL4
SS
= 1.5 V 2 20 45 µA
DDI
V
= 3.0 V 30 120 260 µAI
DDI
= 5.0 V 70 350 650 µA
V
DDI
V
= 1.5 V –45 –20 –2 µA
DDI
V
= 3.0 V –260 –120 –30 µAI
DDI
= 5.0 V –650 –350 –70 µA
V
DDI
VDD = V
V
DD
VDD = V
VDD = V
VDD = V
VDD = V
= 3.0 V –350 –170 –30 µA
DDH
= V
= 5.0 V –750 –450 –200 µA
DDH
= 3.0 V 0.5 1.8 4.0 µA
DDH
= 5.0 V 3 6 10 µA
DDH
= 3.0 V –4.0 –1.8 –0.5 µA
DDH
= 5.0 V –10 –6 –3 µA
DDH
VDD = 1.5 V 10 180 350 µA
VDD = 3.0 V 150 1100 2400 µAI
VDD = V
= 5.0 V 0.5 2.7 5.0 mA
DDH
–1 — 0 µA
VDD = 1.5 V 50 750 1500 µA
VDD = 3.0 V 0.5 3.0 5.5 mA
VDD = V
= 5.0 V 2.0 6.5 11.0 mA
DDH
–1 — 0 µA
*: Applied to the ML63189B only.
= 4.4 V,
DD4
Mea-
suring
Circuit
3
26/36
Page 27
Semiconductor
1
DC Characteristics (5)
FEDL63187B-06
ML63187B/63189B
(VDD = V
DDI
= V
= 3.0 V, V
DDH
V
= 1.1 V, V
DD1
= 5.5 V, Ta = –20 to +70°C unless otherwise specified)
DD5
= 2.2 V, V
DD2
Parameter Symbol Condition Min. Typ. Max. Unit
V
Input Voltage 1
(P0.0 to P0.3)*
(P9.0 to P9.3)*
(PA.0 to PA.3)*
(PB.0 to PB.3)
(PE.0 to PE.3)
Input Voltage 2
(OSC0)
Input Voltage 3
(RESET, TST1, TST2)
IH1
V
IL1
V
IH2
V
IL2
IH3
= 1.5 V 1.2 — 1.5 V
DDI
V
= 3.0 V 2.4 — 3.0 VV
DDI
V
= 5.0 V 4.0 — 5.0 V
DDI
V
= 1.5 V 0 — 0.3 V
DDI
V
= 3.0 V 0 — 0.6 V
DDI
V
= 5.0 V 0 — 1.0 V
DDI
VDD = V
VDD = V
VDD = V
VDD = V
= 3.0 V 2.4 — 3.0 V
DDH
= 5.0 V 4.0 — 5.0 V
DDH
= 3.0 V 0 — 0.6 V
DDH
= 5.0 V 0 — 1.0 V
DDH
VDD = 1.5 V 1.35 — 1.5 V
VDD = 3.0 V 2.4 — 3.0 VV
VDD = 5.0 V 4.0 — 5.0 V
VDD = 1.5 V 0 — 0.15 V
V
IL3
VDD = 3.0 V 0 — 0.6 V
VDD = 5.0 V 0 — 1.0 V
Hysteresis Width 1
(P0.0 to P0.3)*
(P9.0 to P9.3)*
(PA.0 to PA.3)*
∆ V
T1
V
= 1.5 V 0.05 0.1 0.3 V
DDI
V
= 3.0 V 0.2 0.5 1.0 V
DDI
(PB.0 to PB.3)
V
= 5.0 V 0.25 1.0 1.5 V
(PE.0 to PE.3)
DDI
= 3.3 V, V
DD3
= 4.4 V,
DD4
Measuring
Circuit
4
Hysteresis Width 2
(RESET, TST1, TST2)
Input Pin Capacitance
(P0.0 to P0.3)*
(P9.0 to P9.3)*
(PA.0 to PA.3)*
(PB.0 to PB.3)
(PE.0 to PE.3)
∆ V
C
V
= 1.5 V 0.05 0.1 0.3 V
DDI
V
= 3.0 V 0.2 0.5 1.0 V
T2
IN
DDI
V
= 5.0 V 0.25 1.0 1.5 V
DDI
———5pF1
*: Applied to the ML63189B only.
27/36
Page 28
Semiconductor
1
Measuring circuit 1
FEDL63187B-06
ML63187B/63189B
Cb12
C12
1
*1
2
CB1
CB2
C1
C2
OSC0
OSC1
V
V
SS
DD
A
C
a,Cb,Cc,Cd,Ce,Cl,C12
Ch,Cb
C
G
C
L0
C
L1
Ceramic Resonator
*1 RC Oscillator
R
OSH
V
V
DDI
DD1
Ca Cc
12
1
2
DD2
V
DD3
V
Cb
V V
V
0.1 µF
:
1 µF
:
15 pF
:
30 pF
:
30 pF
:
CSA2.00MG (2 MHz)
:
CSB1000J (1 MHz)
(Murata MFG-.make)
V
DD4
V
Cd
Ce
V
*2 RC Oscillator
DD5
V V
3
4
Ch
XT0
3
*2
XT1
V
DDH
V
DDL
4
Cl
V
R
OSL
Ceramic Oscillator
C
L0
C
L1
1
Ceramic Resonator
2
Crystal Oscillator
C
G
3
Crystal
4
28/36
Page 29
Semiconductor
1
Measuring circuit 2
FEDL63187B-06
ML63187B/63189B
V
IH
*2
V
lL
Measuring circuit 3
V
IH
*4
INPUT OUTPUT
V
VDDV
SS
DDlVDD1VDD2VDD3VDD4VDD5VDDH
V
DDL
*2 Input logic circuit to determine the specified measuring conditions.
*3 Measured at the specified output pins.
INPUT OUTPUT
*3
A
Waveform
Monitoring
V
IL
*4 Measured at the specified input pins.
Measuring circuit 4
A
*4
V
SS
VDDV
DDlVDD1VDD2VDD3VDD4VDD5VDDH
V
DDL
INPUT OUTPUT
VSSVDDV
DDlVDD1VDD2VDD3VDD4VDD5VDDH
V
DDL
29/36
Page 30
Semiconductor
)
)
(
)
1
AC Characteristics (Serial Interface, Shift Register)
(VDD = 0.9 to 5.5 V, V
Parameter Symbol Condition Min. Typ. Max. Unit
SCLK Input Fall Time t
SCLK Input Rise Time t
SCLK Input “L” Level
Pulse Width
SCLK Input “H” Level
Pulse Width
SCLK Input Cycle Time t
SCLK Output Cycle Time
SOUT Output Delay Time t
SIN Input Setup Time t
SIN Input Hold Time t
= 1.8 to 5.5 V, VSS = 0 V, V
DDH
f
r
t
CWL
t
CWH
CYC
t
CYC1(O)
t
CYC2(O)
CPU in operation state at 32.768 kHz — 30.5 — µs
DDR
DS
DH
Output load capacitance 10 pF — — 0.4 µs
CPU in operation at 2 MHz
V
DD
FEDL63187B-06
ML63187B/63189B
= 5.0 V, Ta = –20 to +70°C unless otherwise specified)
DDI
———1.0µs
———1.0µs
—0.8——µs
—0.8——µs
V
= 5 V to V
DDI
= V
DDH
DD
= 1.8 to 3.5 V
—0.5——µs
—0.8——µs
1.8 — — µs
—0.5—µs
AC characteristics timing
(“H” level = 4.0 V, “L” level = 1.0 V)
PE.2
SCLK
t
DDR
SOUT (PE.1
SIN (PE.0
t
CYC
5 V (V
t
r
t
CWH t
t
t
DDR
f
CWL
0 V (V
5 V (V
t
DS
t
DH
t
DS
0 V (V
5 V (V
0 V (V
DDI
SS
DDI
SS
DDl
SS
)
)
)
)
)
)
30/36
Page 31
Semiconductor
1
APPLICATION CIRCUITS (ML63187B)
LCD
Crystal
32.768 kHz
C
G
5 to
25 pF
1.0 µF
C
h
1.5 V
1.0 µF
C
v
C
l
C
e
C
d
C
c
C
b
C
a
1.0 µF
C
b12
0.1 µF
0.1 µF
0.1 µF
0.1 µF
0.1 µF
0.1 µF
C
0.1 µF
12
Push SW
Buzzer
XT0
XT1
V
DDH
V
DD
CB1
CB2
V
DDL
V
DD5
V
DD4
V
DD3
V
DD2
V
DD1
C1
C2
RESET
TST1
TST2
MD
COM1-16
ML63187B
SEG0-63
OSC0
OSC1
PE.3
PE.2
PE.1
PE.0
PB.3
PB.2
PB.1
PB.0
V
DDl
FEDL63187B-06
ML63187B/63189B
• Crystal oscillation is selected as low-speed
oscillation by mask option.
• RC oscillation is selected as high-speed
oscillation by software.
• Ports are powered from external memory
power source.
is an IC power supply bypass capacitor.
• C
V
• Values of C
, and CG, are for reference only.
C
h
, Cb, Cc, Cd, Ce, Cl, C
a
R
OSH
b12
, C12,
V
DD
Note: V
MDB
V
SS
is the power supply pin for the input-output ports.
DDI
Be sure to connect the V
pin either to the positive power supply pin (VDD) of this device
DDI
or to the positive power supply pin of the external memory.
Application Circuit Example with Power Supply Backup
31/36
Page 32
1
C
Semiconductor
32.768 kHz
G
5 to 25 pF
V
DD
5.0 V
C
v
C
l
C
e
C
d
C
c
C
v
C
a
C
12
Buzzer
Crystal
0.1 µF
Open
0.1 µF
0.1 µF
0.1 µF
0.1 µF
0.1 µF
0.1 µF
0.1 µF
Push SW
XT0
XT1
V
DDH
V
DD
CB1
CB2
V
DDL
V
DD5
V
DD4
V
DD3
V
DD2
V
DD1
C1
C2
RESET
TST1
TST2
MD
LCD
COM1-16
ML63187B
SEG0-63
• Crystal oscillation is selected as low-speed
oscillation by mask option.
• Ceramic oscillation is selected as high-speed
oscillation by software.
• Ports, external memory, and IC share their
power supply.
is an IC power supply bypass capacitor.
• C
v
• Values of C
C
, and CL1 are for reference only.
L0
, Cb, Cc, Cd, Ce, Cl, C12, CG,
a
CL0 30 pF
OSC0
Ceramic
Resonator
(Example: 1 MHz)
OSC1
C
PE.3
PE.2
PE.1
PE.0
PB.3
PB.2
PB.1
PB.0
V
DDl
L1
30 pF
FEDL63187B-06
ML63187B/63189B
V
DD
Note: V
MDB
V
SS
is the power supply pin for the input-output ports.
DDI
Be sure to connect the V
pin either to the positive power supply pin (VDD) of this device
DDI
or to the positive power supply pin of the external memory.
Application Circuit Example with No Power Supply Backup
32/36
Page 33
Semiconductor
1
APPLICATION CIRCUITS (ML63189B)
LCD
Crystal
32.768 kHz
C
G
5 to
25 pF
1.0 µF
C
h
1.5 V
1.0 µF
C
v
C
1.0 µF
b12
C
C
C
C
C
C
C
0.1 µF
l
0.1 µF
e
0.1 µF
d
0.1 µF
c
0.1 µF
b
0.1 µF
a
0.1 µF
12
Push SW
Buzzer
XT0
XT1
V
DDH
V
DD
CB1
CB2
V
DDL
V
DD5
V
DD4
V
DD3
V
DD2
V
DD1
C1
C2
RESET
TST1
TST2
MD
COM1-16
ML63189B
SEG0-63
• Crystal oscillation is selected as low-speed
oscillation by mask option.
• RC oscillation is selected as high-speed
oscillation by software.
• Ports are powered from external memory
power source.
is an IC power supply bypass capacitor.
• C
v
• Values of C
, and CG, are for reference only.
C
h
, Cb, Cc, Cd, Ce, Cl, C
a
OSC0
R
OSH
OSC1
PE.3
PE.2
PE.1
PE.0
PB.3
PB.2
PB.1
PB.0
PA.3
PA.2
PA.1
PA.0
P9.3
P9.2
P9.1
P9.0
P0.3
P0.2
P0.1
P0.0
V
DDI
FEDL63187B-06
ML63187B/63189B
, C12,
b12
V
DD
Note: V
MDB
V
SS
is the power supply pin for the input and input-output ports.
DDI
Be sure to connect the V
pin either to the positive power supply pin (VDD) of this device
DDI
or to the positive power supply pin of the external memory.
Application Circuit Example with Power Supply Backup
33/36
Page 34
1
C
Semiconductor
32.768 kHz
G
5 to 25 pF
V
DD
5.0 V
0.1 µF
C
v
C
l
C
e
C
d
C
c
C
b
C
a
C
12
Buzzer
Crystal
Open
0.1 µF
0.1 µF
0.1 µF
0.1 µF
0.1 µF
0.1 µF
0.1 µF
Push SW
XT0
XT1
V
DDH
V
DD
CB1
CB2
V
DDL
V
DD5
V
DD4
V
DD3
V
DD2
V
DD1
C1
C2
RESET
TST1
TST2
MD
LCD
COM1-16
ML63189B
SEG0-63
• Crystal oscillation is selected as low-speed
oscillation by mask option.
• Ceramic oscillation is selected as high-speed
oscillation by software.
• Ports, external memory, and IC share their
power supply.
• Cv is an IC power supply bypass capacitor.
• Values of C
, and CL1 are for reference only.
C
L0
, Cb, Cc, Cd, Ce, Cl, C12, CG,
a
CL0 30 pF
OSC0
Ceramic
Resonator
(Example: 1 MHz)
OSC1
C
PE.3
PE.2
PE.1
PE.0
PB.3
PB.2
PB.1
PB.0
PA.3
PA.2
PA.1
PA.0
P9.3
P9.2
P9.1
P9.0
P0.3
P0.2
P0.1
P0.0
V
DDl
L1
30 pF
FEDL63187B-06
ML63187B/63189B
V
DD
Note: V
MDB
V
SS
is the power supply pin for the input and input-output ports.
DDI
Be sure to connect the V
pin either to the positive power supply pin (VDD) of this device
DDI
or to the positive power supply pin of the external memory.
Application Circuit Example with No Power Supply Backup
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Page 35
Semiconductor
QFP128-P-1420-0.50-K
Mirror finish
Package material Epoxy resin
Lead frame material 42 alloy
Pin treatment
Solder plating (≥5µm)
Package weight (g) 1.19 TYP.
5
Rev. No./Last Revised 4/Nov. 28, 1996
1
PACKAGE DIMENSIONS
FEDL63187B-06
ML63187B/63189B
(Unit: mm)
Notes for Mounting the Surface Mount Type Package
The surface mount type packages are very susceptible to heat in reflow mounting and humidity
absorbed in storage.
Therefore, before you perfor m reflow m ounting, c ontac t Ok i’s res ponsibl e s ales per son f or the produ ct
name, package name, pin n umber, package code and desired m ounting conditions (reflow method,
temperature and times).
35/36
Page 36
FEDL63187B-06
Semiconductor
1
ML63187B/63189B
NOTICE
1. The information contained herein can change without notice owing to product and/or technical improv ements.
Before using the product, please make sure that the information being referred to is up-to-date.
2. The outline of action and examples for application circuits described herein have been chosen as an
explanation for the standard action an d performan ce of the product. Wh en planning to use t he product, pleas e
ensure that the external conditions are reflected in the actual circuit, assembly, and program designs.
3. When designing your product, please use our product below the specified maximum ratings and within the
specified operating ranges including, but not limited to, operating voltage, power dissipation, and operating
temperature.
4. Oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation
resulting from misuse, neglect, improper installation, repair, alteration or accident, improper handling, or
unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the s pecified
maximum ratings or operation outside the specified operating range.
5. Neither indemnity against nor license of a third party’s industrial and intellectual property right, etc. is
granted by us in connection with the use of the product and/ or the information and draw ings contained h erein.
No responsibility is assumed by us for any infringement of a third party’s right which may result from the use
thereof.
6. The products listed in this document are intended for use in general electronics equipment for commercial
applications (e.g., office automation, communication equipment, measurement equipment, consumer
electronics, etc.). These products are not authorized for u s e in any system or application that requ ires s pecial
or enhanced quality and reliability characteristics nor in any system or applicatio n where the failure of s uch
system or application may result in the loss or damage of property, or death or injury to humans.
Such applications include, but are not limited to, traf fic and automotive equ ipment, safety devi ces, aerospace
equipment, nuclear power control, medical equipment, and life-support systems.
7. Certain products in this document may need government approval before they can be exported to particular
countries. The purchaser assumes the responsibility of determining the legality of export of these products
and will take appropriate and necessary steps at their own expense for these.
8. No part of the contents contained herein may be reprinted or reproduced without our prior permission.
Copyright 2001 Oki Electric Industry Co., Ltd.
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