OKI ml631 Specifications

FEDL63193-04

1

Semiconductor

This version: Sep. 2001

Previous versi on: Mar. 2000

ML63193

4-Bit Microcontroller with Built-in 1024-Dot Matrix LCD Driver and Melody Circuit.

GENERAL DESCRIPTION

The ML63193 is CMOS 4-bit microcontroller with built-in 1024-dot matrix LCD drivers (64 SEG. × 16 COM.),
and operates at 0.9 V (Min). The ML 63193 is s u i tabl e for appli cati ons as g ames, t oys , w atc hes, rem ote controller,
etc. Which are provided with a LCD display.
The ML63193 is an M6318x series mask ROM-version product of OLMS-63K family, which employs Oki’s
original CPU core nX-4/250.

FEATURES

• Extensive instruction set
408 instructions:

Transfer, rotate, increment/decrement, arithmetic operations, compare, logic operations, mask operations,
bit operations, ROM table reference, stack operations, flag operations, jump, conditional branch, call/return,
control

• Wide variety of addressing modes
Indirect addressing mode for 4 types of data memory with current bank register, extra bank register,
HL register and XY register
Data memory bank internal direct addressing mode

• Processing speed
2 clocks per machine cycle, with most instructions executed in 1 machine cycle
Minimum instruction execution time : 61 µs (@ 32.768 kHz system clock)

: 1 µs (@ 2 MHz system clock)

• Clock generation circuit
Low-speed clock : Crystal oscillation or RC oscillation selected with mask option

(30 kHz to 80 kHz)

High-speed clock : Ceramic oscillation or RC oscillation selected with software

(2 MHz max)

• Pro g r am memory space
64 K words
Basic instruction length is 16 bits/1word.

• Data memory space
2048 nibbles

• Stack level
Call stack level : 16 levels
Register stack level : 16 levels

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• I/O Ports
Input ports:

Selectable as input pull-up resistor/input pull-down resistor/high impedance input.

I/O ports:

Selectable as input pull-up resistor/input pull-down resistor/high impedance input.
Selectable as P-channel open drain output/N-channel open drain output/high-impedance output/

CMOS output.
Can be interfaced with external peripherals that use a different power supply than this device uses.V
power supply pin for ports.
Number of ports:

Input port : 1 port × 4 bits

Input-output port : 5 ports × 4 bits

• Melody output
Melody frequency : 529 Hz to 2979 Hz
Tone length : 63 varieties
Tempo : 15 varieties
Melody data : Stored in program memory
Buzzer driver signal output : 4 kHz

FEDL63193-04

ML63193

is the

DDI

• LCD dri ve r
Number of segments : 1024 Max. (64 SEG. × 16 COM.)

Duty : Selectable as 1/1 to 1/16 duty
Bias : Selectable as 1/4 or 1/5 bias (regulator built-in)
Frame frequency : ex. 64 Hz (at 1/16 duty), 128 Hz (at 1/8 duty), 256 Hz (at 1/4 duty),

512 Hz (at 1/2 duty), 1024 Hz (at 1/1 duty)
Contrast : 16 levels adjustable
Display modes : Selectable as all-ON mode/all-OFF mode/power down mode/

normal display mode

• Multiplier/divider circuit

Multiplier : (8 bits)×(8 bits) → Product (16 bits)
Divider : (16 bits)/(8 bits) → Quotient (16 bits), Remainder (8 bits)

• System reset function
System reset through RESET pin (selectable as built-in 2 kHz RESET-Sampling circuit by mask option)
System reset by power-on detection (When not using 2 kHz RESET-Sampli ng circuit)
System reset by low-speed oscillation halt

• Battery check
Low-voltage suppl y check
The value of the judgment voltage is selected by the software (by setting the LD1 and LD0 bits of BLDCON).

LD1 LD0 Judgment Voltage (V) Remarks

0 0 1.05 ± 0.10 Ta = 25°C
0 1 1.20 ± 0.10 Ta = 25°C
1 0 1.80 ± 0.10 Ta = 25°C
1 1 2.40 ± 0.10 Ta = 25°C

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• Timers and Counter
8-bit timer : 4

Selectable as auto-reload mode/capture mode/
clock frequency measurement mod e
Watchdog timer : 1
100 Hz timer : 1

Measurable in steps of 1/100 sec.
15-bit time-base counter : 1

1, 2, 4, 8, 16, 32, 64, and 128 Hz signals can be read

• Serial port
Mode : Selectable as UART mode, synchronous mode
UART communication speed : 1200 bps, 2400 bps, 4800 bps, 9600 bps
Clock frequency in synchronous mode: Internal clock mode (32.768 kHz), External clock frequency
Data length : 5 to 8 bits

• Shift register
Shift clock : 1× or 1/2 × system clock, timer 1 overflow, external clock
Data length : 8 bits

FEDL63193-04

ML63193

• Interrupt factors
External interrupt : 4
Internal interrupt : 14 (watchdog timer interrupt is a nonmaskable interrupt)

• Operating temperature : –20 to +70 °C

• Power supply backup

Backup circuit (voltage multiplier) enables operation at 0.9 V minimum.

• Power supply voltage
When backup used : 0.9 V to 2.7 V (Operating frequency: 30 k to 80 kHz)

1.2 V to 2.7 V (Operating frequency: 300 k to 500 kHz)

1.5 V to 2.7 V (Operating frequency: 200 k to 1 MHz)

When backup not used : 1.8 V to 5.5 V (Operating frequency: 200 k to 2 MHz)

• Package:
Chip (128 pads) : (Product name: ML63193-xxxWA)
144-pin plastic LQFP (LQFP144-P-2020-0.50-K) : (Product name: ML63193-xxxTC)

xxx indicates a code number.

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FEDL63193-04

Semiconductor

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ML63193

MASK OPTION

In the ML63193 uses the mask option to specify the following functions:

•

Low-Speeed clock oscillation circuit

Specify the crystal oscillation circuit or the RC oscillation circuit for the lo w-speed clock oscillation
circuit.

•

Reset signal sampling

Specify whether or not the reset signal will be sampled at 2 kHz.
When specifying “will carry out 2 kHz sampling,” hold the RESET pin at a “H” level for 1 ms or more.

To use the mask option, assign mask option data in the application program in accordan ce with the formats below.
The mask option area is an application program execution disabled area.

Mask Option Data Assignment Format

Function Mask option area bit data Option to be selected
Low-speed clock oscillation circ ui t
(crystal oscillation circui t/RC osci llat ion circuit)
Reset signal sampling
(will/will not carry out 2 kHz sampling)

bit 0

0FFE0H

bit 1

0 Crystal oscillation circuit
1 RC oscillation circuit
0 Will carry out 2 kHz sampling
1 Will not carry out 2 kHz sampling

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FEDL63193-04

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BLOCK DIAGRAM

Asterisks (*) indicate the secondary function of each port. Signal names enclosed by chain lines ( )
Indicate interface signals of the V

CPU core nX-4/250

DDI

power supply system.

ML63193

TIMING

CON­TROL

SP

RSP

STACK
CAL.S:16-level
REG.S:16-level

RESET

TST1

TST2

XT0
XT1

OSC0
OSC1

V

DDH

DD

V
CB1
CB2

CBR
EBR

ALU

INSTRUCTION

DECODER

RST

TST

OSC

BACK

UP

L

H
X

RA

Y

A
G Z

C

MIE

PC

BUS
CON­TROL

ROM

64KW

IR

INT

TM0CAP/TM1CAP*
TM0OVF/TM1OVF*
T02CK*
T13CK*

RXC*
TXC*
RXD*
TXD*

SCLK*
SIN*
SOUT*

MD
MDB

P0.0 - P0.3

P9.0 - P9.3

INT

INT

4

1

RAM

2048N

INT193

MULDIV

TBC

BLD

100HzTC

4

INT

2

INT

1

INT

1

INT

DATA BUS

1

TIMER

8bit (4ch)

SIO

SFT

MELODY

INPUT

PORT

INT

1

WDT

I/O

PORT

INT

3

PA.0 - PA.3
PB.0 - PB.3

PC.0 - PC.3
PE.0 - PE.3

DD1

V
V

DD2
DD3

V

DD4

V

DD5

V

BIAS

C1

LCD

&

DSPR

COM1 - 16
SEG0 - 63

C2

V

DDL

DDI

V

SS

V

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PIN CONFIGURATION (TOP VIEW)

COM8

SEG0

SEG1

SEG2

SEG3

SEG4

SEG5

SEG6

SEG7

(NC)

999897969594939291908988878685848382818079787776757473

102

101

(NC)

(NC)
SEG8
SEG9

SEG10
SEG11
SEG12
SEG13
SEG14
SEG15
SEG16
SEG17
SEG18
SEG19
SEG20
SEG21
SEG22
SEG23
SEG24
SEG25
SEG26
SEG27
SEG28
SEG29
SEG30
SEG31
SEG32
SEG33
SEG34
SEG35
SEG36
SEG37
SEG38
SEG39

(NC)

(NC)

109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144

105

108

107

106

1234567891011121314151617181920212223242526272829303132333435

104

103

100

COM5

COM6

COM7

COM2

COM3

COM4

P0.3

VSSCOM1

P0.1

P0.2

P9.3

P0.0

P9.1

P9.2

PA.3

P9.0

PA.1

PA.2

PB.3

PA.0

PB.2

PB.1

PB.0

(NC)

(NC)

36

72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37

FEDL63193-04

ML63193

(NC)
(NC)
(NC)
PC.3
PC.2
PC.1
PC.0
PE.3
PE.2
PE.1
PE.0

DDI

V
MDB
MD
TST2
TST1
XT0
XT1
RESET
OSC0
OSC1

DDL

V
V

DD

CB2
CB1

DDH

V
C2
C1

DD5

V
V

DD4

V

DD3

V

DD2

V

DD1

V

SS

(NC)
(NC)

(NC)

(NC)

SEG41

SEG42

SEG40

SEG43

SEG44

SEG45

SEG46

SEG47

SEG49

SEG48

SEG50

SEG51

SEG52

SEG53

SEG54

SEG55

SEG56

SEG57

SEG58

SEG59

SEG60

SEG61

SEG62

COM9

SEG63

COM10

144-Pin Plastic LQFP

(TC: LQFP144-P-2020-0.50-K)

Note: Pins marked as (NC) are no-connection pins which are left open.

COM11

COM12

COM13

COM14

COM15

COM16

(NC)

(NC)

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PAD CONFIGURATION

Pad Layout

FEDL63193-04

ML63193

PB.0 96
PB.1 97
PB.2 98
PB.3
PA.0
PA.1
PA.2
PA.3

P9.0
P9.1
P9.2
P9.3
P0.0
P0.1
P0.2
P0.3

SS

V
COM1
COM2
COM3
COM4
COM5
COM6
COM7
COM8

SEG0
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7

99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128

PC.3

PC.2
94

95

PC.193

92 PC.0

91 PE.3

DDI

90 PE.2

89 PE.1

88 PE.0

87 V

86 MDB

85 MD

84 TST2

83 TST1

82T081T180 RESET

79 OSC0

78 OSC1

DDL

77 V

76 VDD75 CB2

DDH

74 CB1

73 V

72 C2

71 C1

DD5

70 V

ML63193

Y

(0,0)

X

DD4

69 V

DD3

68 V

DD2

67 V

DD1

66 V

SS

65 V

64

COM16

63

COM15

62

COM14

61

COM13

60

COM12

59

COM11

58

COM10

57

COM9

56

SEG63

55

SEG62

54

SEG61

53

SEG60

52

SEG59

51

SEG58

50

SEG57

49

SEG56

48

SEG55

47

SEG54

46

SEG53

45

SEG52

44

SEG51

43

SEG50

42

SEG49

41

SEG48

40

SEG47

39

SEG46

38

SEG45

37

SEG44

36

SEG43

35

SEG42

34

SEG41

33

SEG40

SEG8 1

SEG9 2

SEG10 3

SEG11 4

SEG12 5

SEG13 6

SEG14 7

SEG15 8

Chip size : 5.72 mm × 5.72 mm
Chip thickness : 350 µm (280 µm: available as required)
Coordinate origin : center of chip
Pad hole size : 100 µm × 100 µm
Pad size : 110 µm × 110 µm
Minimum pad pitch : 140 µm

Note: The chip substrate voltage is V

SEG16 9

SS

SEG17 10

.

SEG18 11

SEG19 12

SEG20 13

SEG21 14

SEG22 15

SEG23 16

SEG24 17

SEG25 18

SEG26 19

SEG27 20

SEG28 21

SEG29 22

SEG30 23

SEG31 24

SEG32 25

SEG33 26

SEG34 27

SEG35 28

SEG36 29

SEG37 30

SEG38 31

SEG39 32

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Pad Coordinates

Center of chip: X = 0, Y = 0

Pad No.

Pad

Name

X (µm) Y (µm) Pad No.

1 SEG8 –2204 –2714 44 SEG51 2714 –604
2 SEG9 –2063 –2714 45 SEG52 2714 –464
3 SEG10 –1923 –2714 46 SEG53 2714 –323
4 SEG11 –1783 –2714 47 SEG54 2714 –183
5 SEG12 –1642 –2714 48 SEG55 2714 –43
6 SEG13 –1502 –2714 49 SEG56 2714 98
7 SEG14 –1361 –2714 50 SEG57 2714 238
8 SEG15 –1221 –2714 51 SEG58 2714 379

9 SEG16 –1081 –2714 52 SEG59 2714 519
10 SEG17 –940 –2714 53 SEG60 2714 659
11 SEG18 –800 –2714 54 SEG61 2714 800
12 SEG19 –659 –2714 55 SEG62 2714 940
13 SEG20 –519 –2714 56 SEG63 2714 1081
14 SEG21 –379 –2714 57 COM9 2714 1221
15 SEG22 –238 –2714 58 COM10 2714 1361
16 SEG23 –98 –2714 59 COM11 2714 1502
17 SEG24 43 –2714 60 COM12 2714 1642
18 SEG25 183 –2714 61 COM13 2714 1783
19 SEG26 323 –2714 62 COM14 2714 1923
20 SEG27 464 –2714 63 COM15 2714 2063
21 SEG28 604 –2714 64 COM16 2714 2204
22 SEG29 745 –2714 65

23 SEG30 885 –2714 66
24 SEG31 1025 –2714 67
25 SEG32 1166 –2714 68
26 SEG33 1306 –2714 69 V
27 SEG34 1447 –2714 70 V
28 SEG35 1587 –2714 71
29 SEG36 1727 –2714 72
30 SEG37 1868 –2714 73
31 SEG38 2008 –2714 74 CB1 888 2714

32 SEG39 2149 –2714 75 CB2 748 2714
33 SEG40 2714 –2149 76

34 SEG41 2714 –2008 77
35 SEG42 2714 –1868 78 OSC1 326 2714

36 SEG43 2714 –1727 79 OSC0 186 2714
37 SEG44 2714 –1587 80

38 SEG45 2714 –1447 81
39 SEG46 2714 –1306 82
40 SEG47 2714 –1166 83 TST1 –376 2714
41 SEG48 2714 –1025 84 TST2 –516 2714
42 SEG49 2714 –885 85
43 SEG50 2714 –745 86

Pad

Name

V

SS

V

DD1

V

DD2

V

DD3

DD4

DD5

C1
C2

V

DDH

V

DD

V

DDL

RESET

XT1
XT0

MD

MDB

X (µm) Y (µm)

2152 2714
2011 2714
1871 2714
1730 2714
1590 2714
1450 2714
1309 2714
1169 2714
1028 2714

607 2714
467 2714

46 2714

–95 2714

–235 2714

–656 2714
–797 2714

FEDL63193-04

ML63193

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Center of chip: X = 0, Y = 0

Pad No.

87

Pad

Name

V

DDI

X (µm) Y (µm) Pad No.

–937 2714 108 P0.0 –2714 562

Pad

Name

X (µm) Y (µm)

88 PE.0 –1078 2714 109 P0.1 –2714 421
89 PE.1 –1218 2714 110 P0.2 –2714 281
90 PE.2 –1358 2714 111 P0.3 –2714 140
91 PE.3 –1499 2714 112 V

SS

–2714 0
92 PC.0 –1639 2714 113 COM1 –2714 –140
93 PC.1 –1780 2714 114 COM2 –2714 –281
94 PC.2 –1920 2714 115 COM3 –2714 –421
95 PC.3 –2060 2714 116 COM4 –2714 –562
96 PB.0 –2714 2246 117 COM5 –2714 –702
97 PB.1 –2714 2106 118 COM6 –2714 –842
98 PB.2 –2714 1966 119 COM7 –2714 –983
99 PB.3 –2714 1825 120 COM8 –2714 –1123

100 PA.0 –2714 1685 121 SEG0 –2714 –1264
101 PA.1 –2714 1544 122 SEG1 –2714 –1404
102 PA.2 –2714 1404 123 SEG2 –2714 –1544
103 PA.3 –2714 1264 124 SEG3 –2714 –1685
104 P9.0 –2714 1123 125 SEG4 –2714 –1825
105 P9.1 –2714 983 126 SEG5 –2714 –1966
106 P9.2 –2714 842 127 SEG6 –2714 –2106
107 P9.3 –2714 702 128 SEG7 –2714 –2246

ML63193

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ML63193

PIN DESCRIPTIONS

The basic functions of each pin of the ML63193 are described in Table 1.
A symbol with a slash “/” denotes a pin that has a secondary function. Refer to Table 2 for secondary functions.
For type, “—” denotes a power supply pin, “I” an input pin, “O” an output pin, and “I/O” an input-output pin.

Table 1 Pin Descriptions (Basic Functions)

Function Symbol Pin No. Pad No. Type Description

Power

Supply

Oscillation

V

DD

V

SS

V

DD1

V

DD2

V

DD3

V

DD4

V

DD5

C1 45 71
C2 46 72

V

DDI

V

DDL

V

DDH

CB1 48 74
CB2 49 75

XT0 56 82 I

XT1 55 81 O

OSC0 53 79 I

OSC1 52 78 O

50 76 — Positive power supply pin

39,91 65,112 — Negative power supply pin

40 66
41 67
42 68
43 69

Power supply pins for LCD bias (internally
generated):

Capacitors (0.1 µF) should be connected between

—

these pins and V

.

SS

44 70

Capacitor connection pi ns f or LC D b ias gen eration:
A capacitor (0.1 µF) should be connected between

—

C1 and C2.
Positive power supply pin for external interface

61 87 —

(Power supply for input, and input-output
ports)

Positive power supply pin for internal logic

51 77 —

(internally generated):
A capacitor (0.1 µF) should be connected between
this pin and V

.

SS

Voltage multiplier pin for power supply backup

47 73 —

(internally generated):
A capacitor (1.0 µF) should be connected between
this pin and V

.

SS

Pins to connect a capacitor for voltage multiplier.

—

A capacitor (1.0 µF) should be connected between
CB1 and CB2.

Low-speed clock oscillation pin s:
An option for using crystal oscillation or RC
oscillation is chosen by the mask option.
If the crystal oscillation is chosen, a crystal should
be connected between XT 0 and XT1, and capa citor
(C

) should be connected between XT0 and VSS.

G

If the RC oscillation is chosen, external oscillation
resistor (R

) should be connected between XT0

OSL

and XT1.
High-speed clock oscillation pins:

A ceramic resonator and capacitors (C
external oscillation resistor (R
connected to these pins.

) should be

OSH

, CL1) or

L0

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Table 1 Pin Descriptions (Basic Functions) (continued)

Function Symbol Pin No. Pad No. Type Description

FEDL63193-04

ML63193

TST1 57 83 I

Test

TST2 58 84 I

Reset RESET 54 80 I

Melody

MD 59 85 O Melody output pin (non-inverted output)

MDB 60 86 O Melody output pin (inverted output)

Input pins for testing.
A pull-down resistor is internally connected to these pins.
The user cannot use these pins.

System reset input pin.
Setting this pin to “H“ level puts this device into a
reset state. Then, setting this pin to “ L” level starts
executing an instruction from address 0000H.

An option for using RESET samplin g c irc uit or not using is
chosen by the mask option.

When using RESET sampling circuit, the system reset
mode is entered by holding the RESET pin at a “ H” level
for 1ms or more.
A pull-down resistor is internally connected to this pin.

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Table 1 Pin Descriptions (Basic Functions) (continued)

Function Symbol Pin No. Pad No. Type Description

Port

P0.0/INT5 87 108
P0.1/INT5 88 109
P0.2/INT5 89 110
P0.3/INT5 90 111

P9.0 83 104
P9.1 84 105
P9.2 85 106

P9.3 86 107
PA.0 79 100
PA.1 80 101
PA.2 81 102
PA.3 82 103

PB.0/INT0/

TM0CAP/

TM0OVF

PB.1/INT0/

TM1CAP/

TM1OVF

PB.2/INT0/

T02CK

PB.3/INT0/

T13CK

PC.0/INT1/

RXD

PC.1/INT1/

TXC

PC.2/INT1/

RXC

PC.3/INT1/

TXD

PE.0/SIN 62 88
PE.1/SOUT 63 89
PE.2/SCLK 64 90

PE.3/INT2 65 91

75 96

76 97

77 98

78 99

66 92

67 93

68 94

69 95

4-bit input port:
Pull-up resistor input, pull-down resistor input, or

I

high-impedance input is selectable for each bit.

4-bit input output ports:
In input mode, pull-up resister input, pull-down

I/O

resister input, or hig h-impedanc e input is selec table
for each bit.

In output mode, P-channel open drain output, N­channel open drain output, CMOS output, or high­impedance

I/O

output is selectable for each bit.

I/O

I/O

I/O

FEDL63193-04

ML63193

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Table 1 Pin Descriptions (Basic Functions) (continued)

Function Symbol Pin No. Pad No. Type Description

LCD common signal output pins

O

LCD segment signal output pins

O

LCD

COM1 92 113
COM2 93 114
COM3 94 115
COM4 95 116
COM5 96 117
COM6 97 118
COM7 98 119
COM8 99 120

COM9 27 57
COM10 28 58
COM11 29 59
COM12 30 60
COM13 31 61
COM14 32 62
COM15 33 63
COM16 34 64

SEG0 100 121
SEG1 101 122
SEG2 102 123
SEG3 103 124
SEG4 104 125
SEG5 105 126
SEG6 106 127
SEG7 107 128
SEG8 111 1

SEG9 112 2
SEG10 113 3
SEG11 114 4
SEG12 115 5
SEG13 116 6
SEG14 117 7
SEG15 118 8
SEG16 119 9

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ML63193

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Table 1 Pin Descriptions (Basic Functions) (continued)

Function Symbol Pin No. Pad No. Type Description

LCD segment signal output pins

O

LCD

SEG17 120 10
SEG18 121 11
SEG19 122 12
SEG20 123 13
SEG21 124 14
SEG22 125 15
SEG23 126 16
SEG24 127 17
SEG25 128 18
SEG26 129 19
SEG27 130 20
SEG28 131 21
SEG29 132 22
SEG30 133 23
SEG31 134 24
SEG32 135 25
SEG33 136 26
SEG34 137 27
SEG35 138 28
SEG36 139 29
SEG37 140 30
SEG38 141 31
SEG39 142 32
SEG40 3 33
SEG41 4 34
SEG42 5 35
SEG43 6 36
SEG44 7 37
SEG45 8 38
SEG46 9 39
SEG47 10 40
SEG48 11 41
SEG49 12 42

FEDL63193-04

ML63193

14/37

Semiconductor

1

Table 1 Pin Descriptions (Basic Functions) (continued)

Function Symbol Pin No. Pad No. Type Description

LCD segment signal output pins

O

LCD

SEG50 13 43
SEG51 14 44
SEG52 15 45
SEG53 16 46
SEG54 17 47
SEG55 18 48
SEG56 19 49
SEG57 20 50
SEG58 21 51
SEG59 22 52
SEG60 23 53
SEG61 24 54
SEG62 25 55
SEG63 26 56

FEDL63193-04

ML63193

15/37

Semiconductor

1

Table 2 shows the secondary functions of each pin of the ML63193.

Table 2 Pin Descriptions (Secondary Functions)

Function Symbol Pin No. Pad No. Type Description

External
Interrupt

Capture

Timer

PB.0/INT0 75 96
PB.1/INT0 76 97
PB.2/INT0 77 98

PB.3/INT0 78 99
PC.0/INT1 66 92
PC.1/INT1 67 93
PC.2/INT1 68 94
PC.3/INT1 69 95

PE.3/INT2 65 91 I

P0.0/INT5 87 108

P0.1/INT5 88 109

P0.2/INT5 89 110

P0.3/INT5 90 111

PB.0/

TM0CAP

PB.1/

TM1CAP

PB.0/

TM0OVF

PB.1/

TM1OVF
PB.2/T02CK 77 98 I External clock input pin for timer 0 and timer 2.
PB.3/T13CK 78 99 I External clock input pin for timer 1 and timer 3

75 96 I Timer 0 capture input pin

76 97 I Timer 1 capture input pin

75 96 O Timer 0 overflow flag output pin

76 97 O Timer 1 overflow flag output pin

External 0 interrupt input pins
The change of input sig nal level causes an interrupt
to occur.

I

The Port B Interrupt Enable register (PBIE) enables
or disables an interrupt for each bit.

External 1 interrupt input pins
The change of input sig nal level causes an interrupt
to occur.

I

The Port C Interrupt Enable reg ister (PCIE) enables
or disables an interrupt for each bit.

External 2 interrupt input pin
The change of input sig nal level causes an interrupt
to occur.

External 5 interrupt input pins
The change of input sig nal level causes an interrupt
to occur.

I

The Port 0 Interrupt Enable register (P0IE) enables
or disables an interrupt for each bit.

FEDL63193-04

ML63193

16/37

Semiconductor

1

Table 2 Pin Descriptions (Secondary Functions) (continued)

Function Symbol Pin No. Pad No. Type Description

PC.0/RXD 66 92 I Serial port receive data input pin

Sync serial port clock input-output pin
Transmit clock output w hen t his devi ce is u sed as a

PC.1/TXC 67 93 I/O

Serial Port

PC.2/RXC 68 94 I/O

PC.3/TXD 69 95 O Serial port transmit data output pin

PE.0/SIN 62 88 I Shift register receive data input pin

PE.1/SOUT 63 89 O Shift register transmit data output pin

Shift

Register

PE.2/SCLK 64 90 I/O

master processor.
Transmit clock input when this device is used as a
slave processor.

Sync serial port clock input-output pin
Receive clock output when this device is used as a
master processor.
Receive clock input when this device is used as a
slave processor.

Shift register clock input-output pin.
Clock output when this device is used as a master
processor.
Clock input when this device is used as a slave
processor.

FEDL63193-04

ML63193

17/37

Semiconductor

1

ABSOLUTE MAXIMUM RATINGS

Parameter Symbol Condition Rating Unit
Power supply voltage 1 V
Power supply voltage 2 V
Power supply voltage 3 V
Power supply voltage 4 V
Power supply voltage 5 V
Power supply voltage 6 V
Power supply voltage 7 V
Power supply voltage 8 V
Input voltage 1 V
Input voltage 2 V
Output voltage 1 V
Output voltage 2 V
Output voltage 3 V
Output voltage 4 V
Output voltage 5 V
Output voltage 6 V
Output voltage 7 V
Output voltage 8 V
Storage temperature T

DD1

DD2

DD3

DD4

DD5

DD

DDI

DDH

IN1

IN2

OUT1

OUT2

OUT3

OUT4

OUT5

OUT6

OUT7

OUT8

STG

Ta = 25°C –0.3 to +1.6 V
Ta = 25°C –0.3 to +2.9 V
Ta = 25°C –0.3 to +4.2 V
Ta = 25°C –0.3 to +5.5 V
Ta = 25°C –0.3 to +6.8 V
Ta = 25°C –0.3 to +6.0 V
Ta = 25°C –0.3 to +6.0 V
Ta = 25°C –0.3 to +6.0 V

VDD input, Ta = 25°C –0.3 to V

V

input, Ta = 25°C –0.3 to V

DDI

V

output, Ta = 25°C –0.3 to V

DD1

V

output, Ta = 25°C –0.3 to V

DD2

V

output, Ta = 25°C –0.3 to V

DD3

V

output, Ta = 25°C –0.3 to V

DD4

V

output, Ta = 25°C –0.3 to V

DD5

VDD output, Ta = 25°C –0.3 to V

V

output, Ta = 25°C –0.3 to V

DDI

V

output, Ta = 25°C –0.3 to V

DDH

—

–55 to +150 °C

+ 0.3 V

DD

+ 0.3 V

DDI

+ 0.3 V

DD1

+ 0.3 V

DD2

+ 0.3 V

DD3

+ 0.3 V

DD4

+ 0.3 V

DD5

+ 0.3 V

DD

+ 0.3 V

DDI

+ 0.3 V

DDH

FEDL63193-04

ML63193

(VSS = 0 V)

18/37

Semiconductor

1

RECOMMENDED OPERATING CONDITIONS

• When backup is used

Parameter Symbol Condition Rating Unit

Operating Temperature T
Operating Voltage
Crystal Oscillation

Frequency

Low-speed RC Oscillation
Frequency

Ceramic Oscillation
Frequency

High-speed RC Oscillation
Frequency

V

V

f

f

ROSL

f

f

ROSH

XT

CM

op

DD

DDI

CG = 5 to 25 pF 32.768 to 76.8 kHz

R
R

R
VDD = 0.9 to 1.2 V Not applied
VDD = 1.2 to 2.7 V 300 k to 500 k
VDD = 1.5 to 2.7 V 200 k to 1 M
VDD = 0.9 to 1.2 V Not applied

VDD = 1.2 to 2.7 V

—
—
—

= 1.0 MΩ 36 ± 30%

OSL

= 1.1 MΩ 33 ± 30%

OSL

= 1.2 MΩ 30 ± 30%

OSL

R

= 400 kΩ 200 k ± 30%

OSH

R

= 100 kΩ 700 k ± 30%

OSH

R

= 75 kΩ 1 M ± 30%

OSH

–20 to +70 °C

0.9 to 2.7 V

0.9 to 5.5 V

FEDL63193-04

ML63193

(VSS = 0 V)

kHz

Hz

Hz

• When backup is not used

Parameter Symbol Condition Rating Unit

Operating Temperature T
Operating Voltage

Crystal Oscillation
Frequency

Low-speed RC Oscillation
Frequency

Ceramic Oscillation
Frequency

High-speed RC Oscillation
Frequency

V

V

f

f

ROSL

f

f

ROSH

XT

CM

op

DD

DDI

—
—
—

–20 to +70 °C

1.8 to 5.5 V

1.8 to 5.5 V

CG = 5 to 25 pF 32.768 to 76.8 kHz

R

= 1.0 MΩ 36 ± 30%

OSL

R

= 1.1 MΩ 33 ± 30%

OSL

R

= 1.2 MΩ 30 ± 30%

OSL

VDD = 1.8 to 5.5 V 200 k to 2 M Hz

R

= 100 kΩ 700 k ± 30%

OSH

R

= 75 kΩ 1 M ± 30%VDD = 1.8 to 3.6 V

OSH

R

= 51 kΩ 1.35 M ± 30%

OSH

VDD = 1.8 to 3.5 V, R

= 30 kΩ 2 M ± 30%

OSH

(VSS = 0 V)

kHz

Hz

19/37

Semiconductor

[

]
[

]

1

• Typical characteristics of low-speed RC oscillation

When backup is used/backup is not used (V

1000

kHz

ROSL

f

100

DD

= V

= 1.5 V/VDD = V

DDI

= 3.0 V)

DDI

Reference data

FEDL63193-04

ML63193

10

100 1000 10000

• Typical characteristics of high-speed RC oscillation

= V

When backup is used (V

10000

kHz

ROSH

f

1000

DD

100

10 100 1000

= 1.5 V)

DDI

R

[kΩ]

OSL

Reference data

R

[kΩ]

OSH

20/37

Semiconductor

[

]

1

• Typical characteristics of high-speed RC oscillation

= V

When backup is not used (V

10000

kHz

ROSH

f

1000

DD

= 3.0 V)

DDI

FEDL63193-04

ML63193

Reference data

100

10 100 1000

R

[kΩ]

OSH

21/37

Semiconductor

1

ELECTRICAL CHARACTERISTICS

DC Characteristics (1)

FEDL63193-04

ML63193

(VDD = V

= 0.9 to 5.5 V, VSS = 0 V, Ta = –20 to +70°C unless otherwise specified)

DDI

Parameter Symbol Condition Min. Typ. Max. Unit

V

Voltage V

DD2

V

Voltage

DD2

Temperature

∆V

DD2

DD2

1/5 bias, 1/4 bias

(Ta = 25°C)

— — –4.0 —

1.7 1.8 1.9 V

Deviation
V

Voltage V

DD1

V

Voltage V

DD3

V

Voltage V

DD4

V

Voltage V

DD5

DD1

DD3

DD4

DD5

1/5 bias, 1/4 bias Typ.–0.1 1/2 × V

1/5 bias Typ.–0.3 2/3 × V
1/4 bias

(connect V

DD3

and V

DD2

Typ.–0.2 V

)
1/5 bias Typ.–0.4 2 × V
1/4 bias Typ.–0.3 3/2 × V
1/5 bias Typ.–0.5 5/2 × V
1/4 bias Typ.–0.4 2 × V

DD2

DD2

DD2

DD2

DD2

DD2

DD2

Typ.+0.1
Typ.+0.3

Typ.+0.2
Typ.+0.4

Typ.+0.3
Typ.+0.5
Typ.+0.4

High-speed clock oscillation

V

Voltage

DDH

(Backup used)

V

Voltage V

DDL

stopped

= 1.5 V

V

V

DDH

High-speed clock oscillation

DD

(Ceramic oscillation, 1 MH z)

V

= 1.5 V

DD

High-speed clock oscillation

stopped

High-speed clock oscillation

DDL

(Ceramic oscillation, 1 MH z)

2.8 — 3.0

2.0 — 2.7

1.0 1.5 2.0

1.2 — 5.5

VDD = 1.2 to 5.5 V

Meas-

uring

Circuit

mV/

°C

1

V

Note: 1. “V

register (DSPCNT)

” changes in the r ange from 1.8 to 2.4 V ac cording to the valve of Display Contrast

DD2

22/37

Semiconductor

1

DC Characteristics (2)

FEDL63193-04

ML63193

(VDD = V

= 0.9 to 5.5 V, VSS = 0 V, Ta = –20 to +70°C unless otherwise specified)

DDI

Parameter Symbol Condition Min. Typ. Max. Unit

Crystal Oscillation
Start Voltage

Crystal Oscillation
Hold Voltage

Crystal Oscillation
Stop Detect Time

V

V

T

STA

HOLD

STOP

Oscillation start time:

within 5 seconds

1.2 — —

Backup used 0.9 — —

Backup not used 1.7 — —

— 0.1 — 5.0 ms

External RC
Oscillator

C

G

—5—25

Capacitance
Internal RC

Oscillator

C

D

— 202530

Capacitance
External Ceramic

Oscillator
Capacitance

, C

C

L0

L1

CSA2.00 MG

(Murata MFG.–make) used

VDD = 3.0 V

—30—

Internal RC
Oscillator

C

OS

—81216

Capacitance
POR Voltage V

Non-POR Voltage V

POR1

POR2

VDD = 1.5 V 0 — 0.4
VDD = 3.0 V 0 — 0.7
VDD = 1.5 V 1.2 — 1.5
VDD = 3.0 V 2 — 3

LD1 = 1, LD0 = 1, Ta = 25°C 2.30 2.40 2.50

BLD Judgment
Voltage

V

BLDC

LD1 = 1, LD0 = 0, Ta = 25°C 1.70 1.80 1.90
LD1 = 0, LD0 = 1, Ta = 25°C 1.10 1.20 1.30
LD1 = 0, LD0 = 0, Ta = 25°C 0.95 1.05 1.15

V

= 2.40 V (LD1 = 1, LD0 = 1) — –3.5 —

BLD Judgment
Voltage
Temperature
Deviation

∆V

BLDC

BLDC

V

= 1.80 V (LD1 = 1, LD0 = 0) — –2.3 —

BLDC

V

= 1.20 V (LD1 = 0, LD0 = 1) — –1.6 —

BLDC

V

= 1.05 V (LD1 = 0, LD0 = 0) — –1.2 —

BLDC

Meas-

uring

Circuit

V

pF

1

V

mV/

°C

Notes: 1. “T

occurs.

2. “POR” denotes Power On Reset. (When not using RESET sampling circuit)

3. “V

4. “V

” indicates that if the cr ystal oscil lator stops o ver the value of T

STOP

” indicates that POR occurs when V

POR1

” indicates that POR dose not occur when VDD falls from VDD V

POR2

V

.

DD

falls from VDD to V

DD

, the system reset

STOP

and again rises up to V

POR1

and again rises up to

POR2

DD

23/37

.

Semiconductor

1

DC Characteristics (3)

• When backup is used

FEDL63193-04

ML63193

(Low-speed clock = Crystal oscillation (32.768 kHz), VDD = V

= 1.5 V, VSS = 0 V,

DDI

Display contrast register (DSPCNT) = 0H, Ta = –20 to +70°C unless otherwise specified)

Parameter Symbol Condition Min. Typ. Max. Unit

Supply
Current 1

Supply
Current 2

I

I

DD1

DD2

CPU is in HALT state.

(High-speed clock

oscillation stopped)

CPU is in HALT state.

LCD is in Power Down

mode.

(High-speed clock

Ta = –20 to +50°C— 5.66.5

Ta = –20 to +70°C — 5.6 15.0

Ta = –20 to +50°C— 4.55.0

Ta = –20 to +70°C — 4.5 13.0

oscillation stopped)

Supply
Current 3

Supply
Current 4

Supply
Current 5

I

I

I

DD3

DD4

DD5

CPU is in operation at

low-speed oscillation.

(High-speed clock

oscillation stopped)

CPU is in operation at high-speed oscillation.

(approx. 700 kHz RC oscillation,

R

OSH

CPU is in operation at high-speed oscillation.

(1 MHz Ceramic oscillation)

Ta = –20 to +50°C — 23 26

Ta = –20 to +70°C — 23 30

— 1100 1500

= 100 kΩ)

— 950 1200

Meas-

uring

Circuit

µA1

24/37

Semiconductor

1

DC Characteristics (4)

• When backup is not used

FEDL63193-04

ML63193

(Low-speed clock = Crystal oscillation (32.768 kHz), VDD = V

= 3.0 V, VSS = 0 V,

DDI

Display contrast register (DSPCNT) = 0H, Ta = –20 to +70°C unless otherwise specified)

Parameter Symbol Condition Min. Typ. Max. Unit

Supply
Current 1

Supply
Current 2

I

I

DD1

DD2

CPU is in HALT state.

(High-speed clock

oscillation stopped)

CPU is in HALT state.

LCD is in Power Down

mode.

(High-speed clock

Ta = –20 to +50°C— 2.6 3.5

Ta = –20 to +70°C— 2.6 7.0

Ta = –20 to +50°C— 2.0 2.8

Ta = –20 to +70°C— 2.0 6.0

oscillation stopped)

Supply
Current 3

Supply
Current 4

Supply
Current 5

I

I

I

DD3

DD4

DD5

CPU is in operation at

low-speed oscillation.

(High-speed clock

oscillation stopped)

CPU is in operation at high-speed oscillation.

(approx. 700 kHz RC oscillation,

R

OSH

CPU is in operation at high-speed oscillation.

(2 MHz Ceramic oscillation)

Ta = –20 to +50°C — 12 13

Ta = –20 to +70°C — 12 16

— 1000 1200

= 100 kΩ)

— 1100 1300

Meas-

uring

Circuit

µA1

25/37

Semiconductor

1

DC Characteristics (5)

FEDL63193-04

ML63193

(VDD = V

DDI

= V

= 3.0 V, V

DDH

V

= 1.1 V, V

DD1

= 5.5 V, Ta = –20 to +70°C unless otherwise specified)

DD5

= 2.2 V, V

DD2

= 3.3 V, V

DD3

Parameter Symbol Condition Min. Typ. Max. Unit

V

= 1.5 V –2.5 –1.4 –0.4

Output Current 1
(P9.0 to P9.3)
(PA.0 to PA.3)
(PB.0 to PB.3)

(PC.0 to PC.3)
(PE.0 to PE.3)

Output Current 2
(MD, MDB)

Output Current 3
(SEG0 to SEG63)
(COM1 to COM16)

Output Current 4
(OSC1)

OH1

I

OL1

OH2

I

OL2

I

OH3

I

OHM3

I

OHM3S

I

OMH3

I

OMH3S

I

OML3

I

OML3S

I

OLM3

I

OLM3S

I

OL3

I

OH4R

I

OL4R

I

OH4C

I

OL4C

V

= V

= 0.5 V

OL1

= V

OL2

V

OH3

V

OHM3

V

OHM3S

V

OMH3

V

OMH3S

V

OML3

V

OML3S

V

OLM3

V

OLM3S

V

= V

– 0.5 V

DDI

– 0.7 V

DD

= 0.7 V

= V

= V

= V

= V

= V

= V

= V

= V

= V

= V

OL3

– 0.5 V

DDH

– 0.2 V (V

DD5

+ 0.2 V (V

DD4

DD4

+ 0.2 V (V

DD3

DD3

+ 0.2 V (V

DD2

– 0.2 V (V

DD2

+ 0.2 V (V

DD1

– 0.2 V (V

DD1

+ 0.2 V (VSS level) 4 — —

SS

V

V

OH1

V

OH2

V

OH4R

(RC oscillation)

V

= 0.5 V

OL4R

(RC oscillation)

V

= V

OH4C

DDH

– 0.5 V

(ceramic oscillation)

V

= 0.5 V

OL4c

(ceramic oscillation)

– 0.2 V (V

– 0.2 V (V

DDI

V

= 3.0 V –6.0 –3.5 –1.0I

DDI

V

= 5.0 V –8.5 –5.0 –1.5

DDI

V

= 1.5 V 0.4 1.4 2.5

DDI

V

= 3.0 V 1.0 3.0 6.0

DDI

= 5.0 V 1.5 3.7 8.5

V

DDI

V

= 1.5 V –4.0 –2.0 –0.5

DD

V

= 3.0 V –11.0 –6.0 –2.0I

DD

V

= V

= 5.0 V –14.0 –9.0 –4.0

DD

DDH

V

= 1.5 V 0.5 2.0 4.0

DD

V

= 3.0 V 2.0 5.5 11.0

DD

V

= V

= 5.0 V 4.0 7.0 14.0

DD

DDH

level) – — –4

DD5

level) 4 — —

DD4

level) — — –4

DD4

level) 4 — —

DD3

level) — — –4

DD3

level) 4 — —

DD2

level) — — –4

DD2

level) 4 — —

DD1

level) — — –4

DD1

VDD = V
V

DD

VDD = V
V

DD

VDD = V
V

DD

VDD = V
V

DD

= 3.0 V –2.5 –1.3 –0.25

DDH

= V

= 5.0 V –3.5 –1.7 –0.5

DDH

= 3.0 V 0.25 1.5 2.5

DDH

= V

= 5.0 V 0.5 1.8 3.5

DDH

= 3.0 V –500 –250 –100

DDH

= V

= 5.0 V –800 –350 –200

DDH

= 3.0 V 200 500 800

DDH

= V

= 5.0 V 400 700 1000

DDH

Output Leakage
Current
(P2.0 to P2.3)

I

OOH

VOH = V

DDI

——0.3

(PA.0 to PA.3)
(PB.0 to PB.3)

(PC.0 to PC.3)

I

OOL

VOL = V

SS

–0.3 — —

(PE.0 to PE.3)

DD4

mA

µA

mA

µA

= 4.4 V,

Meas-

uring

Circuit

2

26/37

Semiconductor

1

DC Characteristics (6)

FEDL63193-04

ML63193

(VDD = V

DDI

= V

= 3.0 V, V

DDH

V

= 1.1 V, V

DD1

= 5.5 V, Ta = –20 to +70°C unless otherwise specified)

DD5

= 2.2 V, V

DD2

= 3.3 V, V

DD3

Parameter Symbol Condition Min. Typ. Max. Unit

V

= 1.5 V 2 20 45

DDI

V

= 3.0 V 30 120 260

DDI

V

= 5.0 V 70 350 650

DDI

V

= 1.5 V –45 –20 –2

DDI

V

= 3.0 V –260 –120 –30

DDI

V

= 5.0 V –650 –350 –70

DDI

DDI

SS

VDD = V
VDD = V

VDD = V
V

= V

DD

VDD = V
V

= V

DD

= 3.0 V –350 –170 –30

DDH

= 5.0 V –750 –450 –200

DDH

= 3.0 V 0.5 1.8 4.0

DDH

= 5.0 V 3 6 10

DDH

= 3.0 V –4.0 –1.8 –0.5

DDH

= 5.0 V –10 –6 –3

DDH

0—1

–1 — 0

Input Current 1
(P0.0 to P0.3)
(P9.0 to P9.3)
(PA.0 to PA.3)
(PB.0 to PB.3)
(PC.0 to PC.3)

(PE.0 to PE.3)

Input Current 2
(OSC0)

I

I

I

I
I

I

I

IH1

I

IL1

IH1Z

IL1Z

I

IL2

IH2R

IL2R

IH2C

IL2C

V

= V

IH1

DDI

(when pulled down)

V

= V

IL1

SS

(when pulled up)

V

IH1

(in a high impedance state)

V

IL1

(in a high impedance state)

V

= V

IL2

SS

(when pulled up)

V

= V

IH2R

DDH

V

= VSS (RC oscillation) –1 — 0

IL2R

V

= V

IH2C

DDH

(ceramic oscillation)

V

= V

IL2C

SS

(ceramic oscillation)

= V

= V

(RC oscillation) 0 — 1

VDD = 1.5 V 10 180 350

Input Current 3
(RESET)

I

IH3

I

IL3

V

= V

IH3

DD

V

IL3

VDD = 3.0 V 150 1100 2400

= V

VDD = V

SS

= 5.0 V 0.5 2.7 5.0 mA

DDH

–1 — 0

VDD = 1.5 V 50 750 1500

= V

VDD = 3.0 V 0.5 3.0 5.5I

VDD = V

SS

= 5.0 V 2.0 6.5 11.0

DDH

–1 — 0 µA

Input Current 4
(TST1, TST2)

V

IH4

I

IL4

IH4

= V

DD

V

IL4

DD4

µA

µA

mA

= 4.4 V,

Meas-

uring

Circuit

3

27/37

Semiconductor

1

DC Characteristics (7)

FEDL63193-04

ML63193

(VDD = V

DDI

= V

= 3.0 V, V

DDH

V

= 1.1 V, V

DD1

= 5.5 V, Ta = –20 to +70°C unless otherwise specified)

DD5

= 2.2 V, V

DD2

= 3.3 V, V

DD3

Parameter Symbol Condition Min. Typ. Max. Unit

Input Voltage 1
(P0.0 to P0.3)
(P9.0 to P9.3)
(PA.0 to PA.3)

(PB.0 to PB.3)
(PC.0 to PC.3)
(PE.0 to PE.3)

Input Voltage 2
(OSC0)

Input Voltage 3
(RESET),
(TST1), (TST2)

V

IH1

V

IL1

V

IH2

V

IL2

IH3

V

= 1.5 V 1.2 — 1.5

DDI

V

= 3.0 V 2.4 — 3.0

DDI

V

= 5.0 V 4.0 — 5.0

DDI

V

= 1.5 V 0 — 0.3

DDI

V

= 3.0 V 0 — 0.6

DDI

V

= 5.0 V 0 — 1

DDI

VDD = V
VDD = V
VDD = V
VDD = V

= 3.0 V 2.4 — 3.0

DDH

= 5.0 V 4.0 — 5.0

DDH

= 3.0 V 0 — 0.6

DDH

= 5.0 V 0 — 1

DDH

VDD = 1.5 V 1.35 — 1.5
VDD = 3.0 V 2.4 — 3.0V
VDD = 5.0 V 4.0 — 5.0
VDD = 1.5 V 0 — 0.15

V

IL3

VDD = 3.0 V 0 — 0.6
VDD = 5.0 V 0 — 1

Hysteresis Width 1
(P0.0 to P0.3)

V

= 1.5 V 0.05 0.1 0.3

DDI

(P9.0 to P9.3)
(PA.0 to PA.3)

∆V

V

= 3.0 V 0.2 0.5 1.0

T1

DDI

(PB.0 to PB.3)
(PC.0 to PC.3)
(PE.0 to PE.3)

Hysteresis Width 2
(RESET),
(TST1), (TST2)

∆V

T2

V

= 5.0 V 0.25 1.0 1.5

DDI

V

= 1.5 V 0.05 0.1 0.3

DD

V

= 3.0 V 0.2 0.5 1.0

DD

V

= 5.0 V 0.25 1.0 1.5

DD

Input Pin
Capacitance
(P0.0 to P0.3)
(P9.0 to P9.3)
(PA.0 to PA.3)

C

IN

———5pF1

(PB.0 to PB.3)
(PC.0 to PC.3)
(PE.0 to PE.3)

= 4.4 V,

DD4

Meas-

uring

Circuit

V4

28/37

Semiconductor

1

Measuring circuit 1

FEDL63193-04

ML63193

Cb12

C12

1

*1

2

CB1
CB2

C1
C2

OSC0
OSC1

V

V

SS

DD

A

C
C
C
C
C
Ceramic Resonator : CSA2.00MG (2 MHz)

*1 RC Oscillator

R

OSH

DD1

V

Cb

DD2

V

V

DDI

Ca Cc

V V

, Cb, Cc, Cd, Ce, Cl, C

a

, C

h

b12
G
L0
L1

1
2

V

12

DD3

V

DD4

V

Cd

V

:0.1 µF
:1 µF
: 15 pF
: 30 pF
: 30 pF

CSB1000J (1 MHz)
(Murata MFG.-make)

*2 RC Oscillator

V

Ce

DD5

V V

3
4

Ch

XT0

3

*2

XT1

V

DDH

V

DDL

4

Cl

V

R

OSL

Ceramic Oscillator

C

L0

Ceramic Resonator

C

L1

Crystal Oscillator

C

1

3

G

Crystal

2

4

29/37

Semiconductor

1

Measuring circuit 2

FEDL63193-04

ML63193

IH

V

*3

IL

V

Measuring circuit 3

*5

A

INPUT

VSSV

DDI

DD1

V

V

DD

V

DD2

DD3

V

V

DD5VDDHVDDL

V

DD4

OUTPUT

*3 Input logic circuit to determine the specified measuring conditions.
*4 Measured at the specified output pins.

INPUT OUTPUT

*4

A

Measuring circuit 4

IH

V

*5

IL

V

VSSV

DDI

DD

V

V

DD1

DD2

V

V

DD4

V

V

DD5

DDH

V

DDL

V

DD3

INPUT OUTPUT

DD1

DD2

V

V

DD4

V

V

DD5

DDH

V

DDL

V

SS

V

V

V

V

DDI

DD

DD3

*5 Measured at the specified input pins.

Waveform
Monitoring

30/37

Semiconductor

1

AC Characteristics (Serial Interface, Serial Port)

(1) Synchronous Communication

FEDL63193-04

ML63193

(VDD = 0.9 to 5.5 V, V

= 1.8 to 5.5 V, VSS = 0 V, V

DDH

Parameter Symbol Condition Min. Typ. Max. Unit
TXC/RXC Input Fall Time t
TXC/RXC Input Rise Time t
TXC/RXC Input “L” Level Pul se Width t
TXC/RXC Input “H” Level Pulse Width t
TXC/RXC Input Cycle Time t

TXC/RXC Output Cycle Time t

TXD Output Delay Time t
RXD Input Setup Time t

RXD Input Hold Time t

Synchronous communication timing

TXC (PC.1)/

RXC (PC.2)

f
r

CWL

CWH

CYC

CYC (O)

DDR

DS
DH

t

CYC

= 5.0 V, Ta = –20 to +70°C unless otherwise specified)

DDI

———1.0
———1.0
—0.8——
—0.8——
—2.0——

CPU is in operating at

32.768 kHz

Output load capacitance

10 pF

— 30.5 —

——0.4

—0.5——
—0.8——

(“H” level = 4.0 V, “L” level = 1.0 V)

µs

V

DDI

V

SS

TXD (PC.3)

RXD (PC.0)

t

DDR

t

r

t

CWH

t

DS

t

DH

t

DDR

t

f

t

CWL

V

DDI

V

SS

t

DS

V

DDI

V

SS

31/37

Semiconductor

1

(2) UART Communication

Parameter Symbol Condition Min. Typ. Max. Unit
Transmit Baud Rate T
Receive Baud Rate R

f

: Baud rates (1200, 2400, 4800, 9600 bps)

BRT

BRT

BRT

UART communication timing

TXD (PC.3)

T

= 1/f

BRT

TCR = 1/f

R

= 1/f

BRT

BRT

OSC

BRT

T

R

BRT

BRT

T

– T

BRT

R

× 0.97 R

BRT

FEDL63193-04

ML63193

CR

T

BRT

BRT

(“H” level = 4.0 V, “L” level = 1.0 V)

V
V

DDI

SS

R

T

BRT

BRT

+ T

CR

× 1.03

s

RXD (PC.0)

V

DDI

V

SS

32/37

Semiconductor

1

AC Characteristics (Serial Interface, Shift Register)

FEDL63193-04

ML63193

(VDD = 0.9 to 5.5 V, V

= 1.8 to 5.5 V, V

DDH

Parameter Symbol Condition Min. Typ. Max. Unit
SCLK Input Fall Time t
SCLK Input Rise Time t
SCLK Input “L” Level Pulse Width t
SCLK Input “H” Level Pulse Width t
SCLK Input Cycle Time t

SCLK Output Cycle Time

SOUT Output Delay Time t
SIN Input Setup Time t
SIN Input Hold Time t

AC characteristics timing

SCLK (PE.2)

= 5.0 V, VSS = 0 V, Ta = –20 to +70°C unless otherwise specified)

DDI

f

r
CWL
CWH
CYC

t

CYC1(O)

t

CYC2(O)

DDR

DS

DH

CPU is in operating at

CPU is in operating at 2 MHz

= V

VDD

———1.0
———1.0
—0.8——
—0.8——

1.8 — —

32.768 kHz

= 1.8 to 3.5 V

DDH

— 30.5 —

—0.5—

CL = 10 pF — — 0.4

—0.5——
—0.8——

(“H” level = 4.0 V, “L” level = 1.0 V)

t

CYC

µs

V

DDI

V

SS

SOUT (PE.1)

SIN (PE.0)

t

DDR

t

r

t

CWH

t

DS

t

DH

t

DDR

t

f

t

CWL

V

DDI

V

SS

t

DS

V

DDI

V

SS

33/37

Semiconductor

1

APPLICATION CIRCUITS

Crystal

32.768 kHz

C

G

5 to
25 pF

1.5 V

C

Buzzer

v

C
C
C
C
C
C

1.0 µF
C

l

e

d

c

b

a

C

C

h

b12

12

Push SW

1.0 µF

1.0 µF

0.1 µF

0.1 µF

0.1 µF

0.1 µF

0.1 µF

0.1 µF

0.1 µF

XT0

XT1
V

DDH

V

DD

CB1
CB2

V

DDL

V

DD5

V

DD4

V

DD3

V

DD2

V

DD1

C1

C2
RESET

TST1
TST2
MD

COM1-16

ML63193

LCD

SEG0-63

• Crystal oscillation is selected as low-speed
oscillation by mask option.

• RC oscillation is selected as high-speed
oscillation by software.

• Ports are powered from external memory
power source.

is an IC power supply bypass capacitor.

• C

V

• Values of C

, and CG, are for reference only.

C

h

, Cb, Cc, Cd, Ce, Cl, C

a

OSC0

R

OSH

OSC1

PE.3
PE.2
PE.1
PE.0

PC.3
PC.2
PC.1
PC.0

PB.3
PB.2
PB.1
PB.0

PA.3
PA.2
PA.1
PA.0

P9.3
P9.2
P9.1
P9.0

P0.3
P0.2
P0.1
P0.0

FEDL63193-04

ML63193

, C12,

b12

Note: V

V

MDB
V

SS

is the power supply pin for the input-output ports.

DDI

Be sure to connect the V

pin either to the positive power supply pin (VDD) of this device

DDI

DDI

or to the positive power supply pin of the external memory.

Application Circuit Example with Power Supply Backup

V

DD

34/37

1

Semiconductor

C

G

5 to 25 pF

V

DD

5.0 V

C

v

C

l

C

e

C

d

C

c

C

v

C

a

C

12

Buzzer

Crystal

32.768 kHz

0.1 µF
Open

0.1 µF

0.1 µF

0.1 µF

0.1 µF

0.1 µF

0.1 µF

0.1 µF

Push SW

XT0

XT1
V

DDH

V

DD

CB1
CB2
V

DDL

V

DD5

V

DD4

V

DD3

V

DD2

V

DD1

C1

C2
RESET

TST1
TST2

MD

COM1-16

ML63193

LCD

SEG0-63

• Crystal oscillation is selected as low-speed
oscillation by mask option.

• Ceramic oscillation is selected as high-speed
oscillation by software.

• Ports, external memory, and IC share their

power supply.

is an IC power supply bypass capacitor.

• C

v

• Values of C
C

, and CL1 are for reference only.

L0

, Cb, Cc, Cd, Ce, Cl, C12, CG,

a

CL0 30 pF

OSC0

Ceramic
Resonator
(Example: 1 MHz)

OSC1

C

L1

30 pF

PE.3
PE.2
PE.1
PE.0

PC.3
PC.2
PC.1
PC.0

PB.3
PB.2
PB.1
PB.0

PA.3
PA.2
PA.1
PA.0

P9.3
P9.2
P9.1
P9.0

P0.3
P0.2
P0.1
P0.0

FEDL63193-04

ML63193

Note: V

MDB

V

V

SS

is the power supply pin for the input-output ports.

DDI

Be sure to connect the V

pin either to the positive power supply pin (VDD) of this device

DDI

DDI

or to the positive power supply pin of the external memory.

Application Circuit Example with No Power Supply Backup

V

DD

35/37

Semiconductor

1

PACKAGE DIMENSIONS

LQFP144-P-2020-0.50-K

Mirror finish

FEDL63193-04

ML63193

(Unit : mm)

Package material Epoxy resin
Lead frame material 42 alloy

5

Pin treatment
Package weight (g) 1.37 TYP.
Rev. No./Last Revised 5/Nov. 28, 1996

Solder plating (≥5µm)

Notes for Mounting the Surface Mount Type Package
The surface mount type packages are very susceptible to heat in reflow mounting and humidity

absorbed in storage.
Therefore, before you perfor m reflow m ounting, c ontac t Ok i’s res ponsibl e s ales per son f or the pro duct
name, package name, pin n umber, package code and desired m ounting conditions (reflow method,
temperature and times).

36/37

FEDL63193-04

Semiconductor

1

ML63193

NOTICE

1. The information contained herein can change without notice owing to product and/or technical improv ements.
Before using the product, please make sure that the information being referred to is up-to-date.

2. The outline of action and examples for application circuits described herein have been chosen as an
explanation for the standard action an d performan ce of the product. Wh en planning to use t he product, pleas e
ensure that the external conditions are reflected in the actual circuit, assembly, and program designs.

3. When designing your product, please use our product below the specified maximum ratings and within the
specified operating ranges including, but not limited to, operating voltage, power dissipation, and operating
temperature.

4. Oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation
resulting from misuse, neglect, improper installation, repair, alteration or accident, improper handling, or
unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the s pecified
maximum ratings or operation outside the specified operating range.

5. Neither indemnity against nor license of a third party’s industrial and intellectual property right, etc. is
granted by us in connection with the use of the product and/ or the information and draw ings contained h erein.
No responsibility is assumed by us for any infringement of a third party’s right which may result from the use
thereof.

6. The products listed in this document are intended for use in general electronics equipment for commercial
applications (e.g., office automation, communication equipment, measurement equipment, consumer
electronics, etc.). These products are not authorized for u s e in any system or application that requ ires s pecial
or enhanced quality and reliability characteristics nor in any system or applicatio n where the failure of s uch
system or application may result in the loss or damage of property, or death or injury to humans.
Such applications include, but are not limited to, traf fic and automotive equ ipment, safety devi ces, aerospace
equipment, nuclear power control, medical equipment, and life-support systems.

7. Certain products in this document may need government approval before they can be exported to particular
countries. The purchaser assumes the responsibility of determining the legality of export of these products
and will take appropriate and necessary steps at their own expense for these.

8. No part of the contents contained herein may be reprinted or reproduced without our prior permission.

Copyright 2001 Oki Electric Industry Co., Ltd.

37/37