OKI 6e, 6ex Troubleshooting Manual

OKIPAGE 6e/6ex LED Page Printer

T roubleshooting Manual with Component Parts List

ODA/OEL/INT

Approval

All specifications are subject to change without notice.

*Times, Helvetica and Palatino are trademarks of Linotype AG and/or its subsidiaries. ITC Avant Garde Gothic, ITC Zapf Chancery, ITC Zapf Dingbats and ITC Bookman are registered trademarks of International Typeface Corporation. HP and LaserJet are registered trademarks of Hewlett-Packard Company. Diablo 630 is a registered trademark of Xerox corporation.

CONTENTS

1. OUTLINE

2. TOOLS

3. CIRCUIT DESCRIPTION

4. TROUBLESHOOTING

5. COMPONENT PARTS LIST

6. CIRCUIT DIAGRAM

1. OUTLINE

This manual has been written to provide guidance for troubleshooting of the OKIPAGE 6e Series Printer (primarily for its printed circuit boards), on an assumption that the reader is knowledgeable of the printer. Read the maintenance manual for this printer if necessary.

Notes:

1. The power supply board (OLER/OLHR) containing a high voltage power supply is dangerous. From the viewpoint of the safety standards, the local repairing of a defective board is not allowed. Thus, the objects to be locally repaired as a result of troubleshooting are switches and fuses.

2. Replacement of CPU (MHM2029K) is not recommended. If CPU is found to be defective, board replacement is suggested.

2. TOOLS

For troubleshooting the printer, the tools listed below may be needed in addition to general maintenance tools.

Tool Remarks Extension cord kit P/N: 4YA4121-2028G2 Oscilloscope Frequency response 100 MHz or higher Soldering iron A slender tip type, 15-20 watts

- 1 -

3. CIRCUIT DESCRIPTION

3.1 Outline

The control board controls the reception of data transferred through a host I/F and processes command analysis, bit image development, raster buffer read. It also controls the engine and the operator panel. Its block diagram is shown in Fig. 3-1 through 3-4.

(1) Reception control

The control board has one centronics parallel I/F port. The parallel I/F port can specify the following item when set by the control panel:

I-PRIME: Enabled/Disabled

(2) Command analysis processing

The OKIPAGE 6e series printers have the following emulation modes.

Laser Jet Series IVP : Hewlett Packard OKIPAGE 6e/6ex

An edit task fetches data from the receive buffer, analizes commands, and reconstructs the data in such a way that print data are aligned from up to down and from right to left; then it writes the resultant data into a page buffer with such control data as print position coordinate, font type, etc. added.

(3) Font Processing

When one page editing is finished, a developing task makes an engine start and fetches data from the page buffer synchronizing with a printing operation; then it developes the fetched data to a bit map as referring to data from a character generator, and writes the resultant data into the raster buffer (of band buffer structure).

(4) Raster buffer read.

As controlling the engine operation, an engine task sends data from the raster buffer to the LED head.

- 2 -

1MB Memory Board

(Option)

L5C-

EEPROM

Centronics parallel I/F

Reset

circuit

Program & Font

ROM

4MB Mask ROM

7407

16 bits

DATA

BUS

1 Chip CPU

+8V -8V 0V +5V

+30V

For optional

RAM board

256k x 16 DRAM x 2

CH TR DB

HEAT ON

Resident RAM

(1M Bytes)

Drum motor &

Registration motor

drive circuit

FAN Driver

FAN ALM

High Capacity Second Paper

Feeder (Option)

FAN

LED Head

Drum Motor

Registration Motor

Multi-Purpose

Feeder (Option)

Power Supply Board

Inlet sensor 1

Inlet sensor 2

Paper sensor

Outlet sensor

Paper out sensor

Toner low sensor

Low voltage

generation circuit

transformer

Cover

open

switch

High voltage

Heater drive

circuit

Filter circuit

generation

circuit

LSI

Thermistor

+5V

Charge roller

Transfer roller

Developing

roller

Toner supply

roller

Cleaning

roller

Heater

AC IN

Figure 3-1 OKIPAGE 6e Block Diagram

- 3 -

1MB Memory Board

L6A-

Program & Font

4MB Mask ROM

EEPROM

Centronics parallel I/F

Reset

circuit

ROM

7407

16 bit

32 bit

DATA

BUS

1 Chip CPU

+8V -8V 0V +5V +30V

For optional

RAM board

16 bit

Resident RAM

1M x 16 DRAM

CH TR DB

HEAT ON

(2MB)

Drum motor &

Registration motor

drive circuit

FAN Driver

FAN ALM

High Capacity

Second Paper

Feeder (Option)

Drum Motor

Registration Motor

FAN

LED Head

Multi-Purpose

Feeder (Option)

Power Supply Board

Inlet sensor 1

Inlet sensor 2

Paper sensor

Outlet sensor

Paper out sensor

Toner low sensor

Low voltage

generation circuit

transformer

Cover

open

switch

High voltage

Heater drive

circuit

Filter circuit

generation

circuit

LSI

Thermistor

+5V

Charge roller

Transfer roller

Developping

roller

Toner supply

roller

Cleaning

roller

Heater

AC IN

Figure 3-2 OKIPAGE 6ex Block Diagram

- 4 -

3.2 CPU and Memory

(1) CPU (MHM2029K-002K for OKIPAGE 6e, MHM2029K-004K-29 for OKIPAGE 6ex)

CPU core RISC CPU (MIPS R3000 compatible) CPU clock 24.576 MHz (OSC is 12.288 MHz)

(2) Program ROM

ROM capacity 4MB (32M bit mask ROM) ROM type 32M bits (2M × 16 bits) for OKIPAGE 6e and 32M bits (1M × 32 bits) for

OKIPAGE 6ex

Access time 100 ns for OKIPAGE 6e and 100ns for OKIPAGE 6ex

(3) Resident RAM

RAM capacity 1MB (4M bit D-RAM, 2 pieces) for OKIPAGE 6e and 2MB (16M bit D-RAM,

1 piece) for OKIPAGE 6ex

RAM type 4M bits (256k × 16 bits)

16M bits (1M × 16 bits)

Access time 80 ns

(4) Expansion SIMM

RAM capacity 1/2/4/8/16MB/32MB (32MB for OKIPAGE 6ex only) SIMM RAM type 72 pins Access time 60 ~ 100 ns

The block diagram of CPU and memory circuit is shown in Fig. 3-4 through 3-7.

- 5 -

0 20.3 40.7 61.0 81.3 101.7 122.1 142.4 162.8 183.1 203.5 (ns)

(24.576 MHz) OSC1

Figure 3-4 Block Diagram of CPU & Memory in OKIPAGE 6e/6ex

- 6 -

A00-A25-P

DRAS0-5-N

DCAS0-3-N

RD-N

D00-D31-P

SIMM speed

No SIMM

60 ns 70 ns 80 ns

100 ns

VARID VARID

34.5 (TYP.) 34.5 (TYP.) T3

20.0 (TYP.)

22.0 (TYP.)

TIME

T1 T2 T3 T4

61.0 ns

81.3 ns

162.8 ns

203.5 ns

40.7 ns

101.7 ns

122.1 ns

23.5 (TYP.)

DATA

CPU detects the type of SIMM memory installed on the memory expansion board, and sets the suitable timing as shown in the left handside table. Due to this, T1~T4 values shown above vary depending on the type of SIMM memory being used.

CPU

CS0 CS1 CS2 CS3 CS4

DRAS0 DRAS1 DRAS2 DRAS3 DRAS4 DRAS5

DCAS0 DCAS1

For PS board

A00 to A25

D00 to D15

CS0

DRAS1

DRAS0

RD/WR

Mask ROM

(2M x 16 bits)

DRAM

(256k x 16 bits)

PD01 to PD04

D00 to D03

244

DCAS0/DCAS1

A09 to

A22

244

A09 to A12

PD01 to PD04

244

SIMM 2M byte 4M byte 8M byte

16M byte

512k X 8

bits

SIM RAS0 SIM RAS1 SIM RAS2

D0-D15

D8-D15

D0-D7

Main control board

D0-D15

RWR-N

RDCAS0 RDCAS1

Figure 3-5 Block Diagram of CPU & Memory in OKIPAGE 6e

- 7 -

CPU

CS0 CS1 CS2 CS3 CS4

For PS board

D00 to D31

CS0

DRAS0 DRAS1 DRAS2 DRAS3 DRAS4 DRAS5

DCAS0 DCAS1

PD01 to PD04

D00 to D03

244

A00 to A25

DRAS0

A09 to A20

DCAS0/DCAS1

A09 to

A22

244

RD/WR

A09 to A12

Mask ROM

(1M x 32 bits)

DRAM

(1M x 16 bits)

244

D00 to D31

D00 to D15

SIM RAS0 SIM RAS1 SIM RAS2 SIM RAS3

Main control board

D0-D15

SIMM 2M byte

PD01 to PD04

4M byte 8M byte

16M byte

D0-D15

32M byte

D8-D15

512k X 8

bits

D0-D7

RWR-N

RDCAS0 RDCAS1

Figure 3-6 Block Diagram of CPU & Memory in OKIPAGE 6ex

- 8 -

3.4 Reset Control

When power is turned on, a CLRST-N signal is generated by the rising sequence of +30V power supply.

+30V

(15V)

Power ON

+8V

11 10

+ –

Q1 1

+5V

172

Power OFF

CPU

To Option Board

+30V

Q10 Input

CLRST-N

+5V

+8V

Q10-10 Q10-11

- 9 -

3.5 EEPROM Control

The BR93LC46A on the main control board is an electrical erasable/programmable ROM of 64-bit x 16-bit configuration. Data input to and output from the ROM are bidirectionally transferred in units of 16 bits through a serial I/O port (SSTXD-P) in serial transmission synchronized with a clock signal from the CPU.

DI DO

CPU

SSTXD-P

154

EEPRMCS0-P

150

EEPRMCLK-P

151

The EEPROM operates in the following instruction modes

Instruction

Start bit

Read (READ) 1 10 A5 to A0 Write Enabled (WEN) 1 00 11XXXX Write (WRITE) 1 01 A5 to A0 D15 to D0 Write All Address (WRAL) 1 00 01XXXX D15 to D0 Write Disabled (WDS) 1 00 00XXXX Erase 1 11 A5 to A0 Chip Erasable (ERAL) 1 00 10XXXX

Operation code

Address Data

Write cycle timing (WRITE)

1 2 4 9 10 25

1 0 1 A5 A4 A1 A0 D15 D14 D1 D0

HIGH-Z

Read cycle timing (READ)

DI DO

HIGH-Z

110

4910

A5 A4 A1 A0

D15 D14 D1 D00D15 D14

Min. 450 ns

STATUS

Max. 500 ns

BUSY READY

Max. 10 ms

25 26

- 10 -

The NM93C66N on the PostScript board is an electrical erasable/programmable ROM of 256-bit x 16bit configuration. Data input to and output from the ROM are bidirectionally transferred in units of 16 bits through a serial I/O port (SSTXD-P) in serial transmission synchronized with a clock signal from the CPU.

DI DO

CPU

SSTXD-P

154

EEPRMCS1-P

150

EEPRMCLK-P

151

The EEPROM operates in the following instruction modes

Instruction

Start bit

Read (READ) 1 10 A7 to A0 Write Enabled (WEN) 1 00 11XXXXXX Write (WRITE) 1 01 A7 to A0 D15 to D0 Write All Address (WRAL) 1 00 01XXXXXX D15 to D0 Write Disabled (WDS) 1 00 00XXXXXX Erase 1 11 A7 to A0 Chip Erasable (ERAL) 1 00 10XXXXXX

Operation code

Address Data

Write cycle timing (WRITE)

12 4 1112 27

1 0 1 A7 A6 A1 A0 D15 D14 D1 D0

HIGH-Z

Read cycle timing (READ)

DI DO

HIGH-Z

110

41112

A7 A6 A1 A0

D15 D14 D1 D00D15 D14

Min. 450 ns

STATUS

Max. 500 ns

BUSY READY

Max. 10 ms

27 28

- 11 -

3.6 Centronics Parallel Interface

The CPU sets a BUSY-P signal to ON at the same time when it reads the parallel data (PDATA1P to PDATA 8-P) from the parallel port at the fall of PSTB-N signal. Furthermore, it makes the store processing of received data into a receive buffer terminate within a certain fixed time and outputs an ACK-N signal, setting the BUSY-P signal to OFF.

CN8

CPU

87, 88, 91 to 96

PDATA1-P to PDATA8-P

PSTB-N

PBUSY-P

PACK-N

PPE-P

PSEL-P

PERROR-P

PINIT-N

PSELIN-N

PALITOFD-N

HILEVEL

SP1 +5V

Q20

2 to 9

+5V

DATA8-P

DATA1-P STB-N

BUSY-P

ACK-N PE-P

SEL-P

FAULT-N

IPRIME-N SELIN-N

AUTOFEED-N

PARALLEL DATA (DATA BITs 1 to 8)

DATA STOROBE

BUSY ACKNOWLEDGE

0.5 µs min.

0.5 µs max.

0 min.

0.5 µs to 10 µs

- 12 -

0.5 µs min.

0 min.

3.8 Operator Panel Control

The operator panel consists of the following circuits.

OLCC-2

Main control board

SSTXD-P 154

SSRXD-P

158

CPU

SSCLK-N

153

SSLD-N

152

PANEL

3 4

CN1

BU6152S

LSI

DB4~DB7 RS

R/W E

LED

44780 LCD Control Driver

Zebra Rubber

Flexible

LCD

Cable

1) BU5148S (LSI) This LSI is connected to a clock synchronous serial port of the CPU. It controls switch data input,

LED data output and LCD data input/output according to the commands given by the CPU. The CPU sends the 2-byte (16-bit) command (SSTXD-P) together with the shift clock signal (SSCLKN) to the LSI and then makes a predetermined input/output control if the command decoded by the LSI is found to be a normal command.

On receiving a command sent from the CPU, the LSI, synchronizing with the serial clock of the command, returns a 2-byte command response to the CPU.

SSTXD-P

SSCLK-N

SSRXD-P

SSLD-N

bit 0 bit 7

Command (first)

bit 7bit 0

Command response (first) Command response (second)

Command (second)

- 13 -

3.9 LED Head Control

(1) For OKIPAGE 6e When a paper form is made to arrive at the data write position on print start, the sending of data to

the LED head starts as synchronized with the page synchronous signal/line synchronous signal (CPU internal signal).

Bit image data developed on the raster buffer of a memory are DMA-transferred to the register of a video interface controller (CPU built-in) and then sent to the shift register of the LED head in a serial transmission synchronized with the HDCLK-P signal by the HDDTO-P signal.

When 1-dot line data (2560 bits) is completely shifted, it is latched by means of the HDLD-P signal, causing LEDs to be driven by means of the STB1-N to STB4-N signals in 4-time division.

Main control board

LED Head

CN4

CPU

CN1

HDCLK-P

HDDTO-P

HOLD-P

STB 1-N STB 2-N STB 3-N STB 4-N

+5V

142

143

139

138 137

136 135

Chip 40

64 bit shift REG

LATCH

Bit 2560

Chip 1

1 to 640 bits

641 to 1280 1281 to 1920 1921 to 2560

Bit 1

- 14 -

Page synchronous signal*

Line synchronous signal*

HDDTO-P

HDCLK-P

HDDTO-P

HDCLK-P HDDTO-P

HDLD-P STB1-N

STB2-N

2.19 msec

2560 clock

0.6 µs

STB3-N STB4-N

* CPU internal signal

- 15 -

(2) For OKIPAGE 6ex

An LED correcting head, which is capable of correcting the illumination of the LED for each dot, is being used in this printer. LED illumination correction function of 16 steps is carried out by using an EEPROM which is installed in the LSI that maintains the LED illumination correction values, and an LED correction drivers together as a pair.

The LED correcting head consists of the correction control LSI, LED drivers, and an LED array.

From

CPU

STRB1-N STRB2-N STRB3-N STRB4-N

LOADI

CLOCKI

DATAI0 DATAI1 DATAI2 DATAI3

WAF

EEPROM

Correction

Values

LED Array

LED

LED Driver

LED

LED LED LED

LED Driver

Printing and correction data combined signal line

Correction data signal line

LED

LED Driver

LED

LED Driver

- 16 -

CLOCKI

LOADI

DATAI3-0

STRB1I-N

STRB2I-N

STRB3I-N

STRB4I-N

Normal Mode Printing Timing Chart

First line printing data sent

Second line printing data sent

First line printing

The printing operation is carried out in the following sequence. First, the printing data DATAI3 through DATAI0 are stored, sequentially shifted, in the shift registers of the LED drivers, by the printing data synchronous clock, CLOCKI. Then the printing data stored in shift registers are latched by the high level pulse of LOADI. The latched printing data turns the LEDs on by STRB1I-N through STRB4I-N and actuates printing.

- 17 -

3.10 Motor Control

A registration motor and a drum motor are driven by means of control signals from the CPU and a driver IC.

+30V

DMPH1

DMPH2

DMON1

CPU

RMPH1

RMPH2

RMON

132

131

127

134

133

128

+5V

5 4

+5V

9 8

COMPTH

Q11

+ –

ECN1351

VccH

INA

INB

VrefA

VrefB

INC

RSA

RSD

2 3

5 6

Drum Motor

IND

RSC

RSD

19 18

22 21

VrefC

VrefD

Vcc

+5V

Registration Motor

(1) Drum motor

DMON1-N

DMPH1-P

DMPH2-P

Rotation

Stop

T0 T1 T2 T3

Forward rotation Reverse rotation

Operation at normal speed: T0 to T3 = 1.094 ms

- 18 -

(2) Registration motor

RMON-N

RMPH1-P

RMPH2-P

Rotation Stop Forward rotation Reverse rotation

T0 T1 T2 T3

Hopping drive Resist roller drive

Operation at normal speed: T0 to T3 = 1.094 ms

(3) Drive control

Time T0 to T3 determines the motor speed, while the phase different direction between phase signals DMPH1-P and DMPH2-P (RMPH1-P and RMHPH2-P) determines the rotation direction. DMON1-N and RMON-N signals control a motor coil current. According to the polarity of the phase signal, the coil current flow as follows:

1) +30V → SW → motor coil → SW → resistor → earth, or,

2) +30V → SW → motor coil → SW → resistor → earth The drop voltage across the resistor is input to comparator, where it is compared with a reference

voltage. If an overcurrent flows, a limiter operates to maintain it within a certain fixed current.

- 19 -

3.11 Fuser Temperature Control

For the temperature control by heater control, the variation in the resistance of thethermistor is A/D converted in IC2 and the resultant digital value is read and transferred to the CPU. The CPU turns on or off the HEATON-N signal according to the value of the signal received from IC2 to keep the temperature at a constant level.

Immediately after the power is turned on, the thermistor is checked for short circuit and breakdown. If the thermistor is shorted, the A/D converted value shows an abnormally high temperature, so that the short circuit can be detected. If the breakdown of the thermistor occurs, the A/D converter value shows the normal temperature. In this case, the thermistor breakdown can be detected by the sequence shown at the end of this section. If the heater is overheated, 5V supply is turned off when the resistance of the thermistor is detected to be exceeding the predetermined value.

Thermistor

Heater

CN2

TH1

TH2

Thermistor

Breakdown

Detector

Circuit

PC1

IC2 CPU

Abnormally

High

Temperature

Detection

Circuit

Supply

Interface

Power

ACIN

HEATON-N 116

- 20 -

The temperature control is described below.

Temperature

°C

HEATON-N

ON OFF ON OFF ON

168°C 165°C

* The values V1 and V2 vary according t o setting mode.

(Standard temperature)

When Vt rises to V2 or more, the heater is turned of (by setting HEATON-N signal to LOW). When Vt drops to V1 or less, the heater is turned on (by setting HEATON-N signal to HIGH). In this way, the temperature can be kept within the predetermined range.

- 21 -

For heater breakdown detection, the heater must first be turned on. When a temperature rise which corresponds to the switching on of the heater does not occur, then a heater breakdown is detected. To shorten the breakdown detection time, the following circuit is used. Immediately after the power is turned on, the thermistor is checked and THERMCMP signal is turned on to turn the transistor Q44 on. The reading resolution is increased through the variation of the thermistor resistance value.

If, for whatever reason, temperature control fails and the temperature rises abnormally, the abnormal high temperature detection circuit shown below forcibly cuts the power supply to the fuser.

Thermistor

From CPU

Thermistor Breakdown Detection Circuit

R306

1.5kΩ

Q44

THERM-CMP

Abnormal High Temperature Detection Circuit

+5V

R302

1kΩ

324

R303

1kΩ

R304

1.8kΩ

+5V

– +

R305

100kΩ

Q43

IC2

A/D

Converter

HEAT-NO

To PC1

- 22 -

3.12 Fan Motor Control

The stop/rotation of the fan motor is controlled by a FANON-P signal. When the fan motor rotates normally, a FANALM-P signal generated in the hole element built in the fan motor is input to the CPU.

+30V

CN1

TR512

TR1

Fan Motor

FANON-P 109

TR2

CPU

FANALM-N 110

FANON2-N

126

Q11-10

+5V

FANON-P FANON2-N

FANALM-P

FAN rotation

Drum motor

+5V

Q11

–

Slow Fast Slow

OFF

TR511

2 3

0.7 sec max

Lock

OFF

Fan motor start: Initial request, heater on, print start request Fan motor stop: • The motor immediately stops when an engine error or a fan error occurs.

Drum motor

Heater control

Fan motor

• The motor stops 20 minutes after the occurrence of a paper jam, size error, or fuse error.

• The motor stops in the power save mode as below.

Heater hold time

8 min. 20 min.

Rotation state

OFF

OFFON

Stop state

- 23 -

3.13 Sensor Control

The CPU supervises the state of each sensor every 40 ms.

Main Control Board Power Supply Board.

+5V

122

123

120

CPU

121

119

124

CN7 CN3

PSOUT-N10

WRSNS-N

PSIN1-N

PAPER-N

PSIN2-N

TNRSNS-N

+5V

PS1

PS2

PS3

PS4

PS5

PS6

Sensor signal

OFF

TransparentShield

- 24 -

3.14 Cover Open

When the cover is opened, a cover open microswitch is opened. This makes a CVOPN-N signal low, thereby the CPU detects the open state. Furthermore, opening the cover stops applying a +5V power to the high voltage power supply unit, resulting in stopping all high voltage outputs.

CVOPN-N

Main Control Board

125

CPU

+5V

Cover close Cover open

CVOPN-N

Power Supply Board

+5V

Low Voltage Power

Cover Open Microswitch

Supply Unit

High Voltage Power Supply Unit

High voltage output

- 25 -

3.15 Power Supply Board

(1) Low voltage power supply

An AC power from an inlet is input to a transformer via fuses, AC switch and noise filter and then lowered to a 28 VAC power and a 10 VAC power. The 28 VAC power is converted to a +30 VDC output through a rectifying/smoothing circuit. A +5 VDC output is derived from the resultant +30 VDC power through a regulation circuit. The 10 VAC power is converted to a +8 VDC output and a -8 VDC output through a rectifying/smoothing circuit.

ACIN

FG N

Filter

Circuit

Power supply board

CN1

Thermal Fuse

CN2

1, 2

3, 4

CN3

F3F2F1L

+30V

Smoothing

Circuit

+5V

Stabilizing

Circuit

OVP 21, 23, 25 +30 V 17, 18

+5 V

11, 12, 13, 14

0 V 9, 15, 16

Fuse Ratings

Fuse

AC Input

F1 F2 F3

120 V 230 V 125 V 6.3 A 125 V 1.6 A 125 V 2.5 A

250 V 5 A

250 V 2.5 A

AC Transformer

±8V

Rectifying/

Smoothing

Circuit

+8 V 24

-8 V 22

- 26 -

(2) Sensor control

Main Control Board

+5V

IC2

Power Supply Board

+5V

PSOUT-N

PS1

WRSNS-N

PS2

PSIN1-N

PS3

PAPER-N

PS4

PSIN2

PS5

TNRSNS-N

PS6

Sensor signal

OFF

Shield

Transparent

- 27 -

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