OKI 20, 20n Troubleshooting Manual

OKIP AGE 20
LED Page Printer

T roubleshooting Manual
with Component Parts List

ODA/OEL/INT

All specifications are subject to change without notice.

40692901TH

CONTENTS

1. OUTLINE ............................................................................................................ 1

2. TOOLS................................................................................................................ 1

3. CIRCUIT DESCRIPTION.................................................................................... 2

3.1 Outline ...................................................................................................... 2

3.2 CPU and Memory..................................................................................... 4

3.3 Reset Control ........................................................................................... 6

3.4 EEPROM Control ..................................................................................... 7

3.5 Centronics Parallel Interface .................................................................... 9

3.6 RS232C Interface................................................................................... 10

3.7 Operator Panel Control........................................................................... 11

3.8 LED Head Control .................................................................................. 12

3.9 Motor Control.......................................................................................... 14

3.10 Fuser Temperature Control .................................................................... 16

3.11 Fan Motor Control................................................................................... 19

3.12 Sensor Supervision ................................................................................ 21

3.13 Cover Open ............................................................................................ 22

3.14 Power Supply Interface .......................................................................... 23

3.15 Option (2nd/3rd paper feeder and Multi feeder) Interface ...................... 24

3.16 DUPLEX Interface .................................................................................. 25

3.17 Power Supply Board............................................................................... 26

4. TROUBLESHOOTING...................................................................................... 28

4.1 Troubleshooting Table............................................................................ 28

4.2 Troubleshooting Flowchart ..................................................................... 32

5. CIRCUIT DIAGRAM ......................................................................................... 48

6. COMPONENT PARTS LIST............................................................................. 70

APPENDIX A DUPLEX UNIT (OPTION) ..........................................................A-1

1. CIRCUIT DESCRIPTION ......................................................................A-1

2. TROUBLESHOOTING ..........................................................................A-3

3. CIRCUIT DIAGRAM ..............................................................................A-8

4. COMPONENT PARTS LIST................................................................A-12

APPENDIX B

1. CIRCUIT DESCRIPTION ......................................................................B-1

2. TROUBLESHOOTING ..........................................................................B-3

3. CIRCUIT DIAGRAM ..............................................................................B-7

4. COMPONENT PARTS LIST................................................................B-10

HIGH CAPACITY SECOND/THIRD PAPER FEEDER (OPTION).........B-1

APPENDIX C MULTI PURPOSE FEEDER (OPTION) .................................... C-1

1. CIRCUIT DESCRIPTION ..................................................................... C-1

2. TROUBLESHOOTING ......................................................................... C-3

3. CIRCUIT DIAGRAM ............................................................................. C-6

4. COMPONENT PARTS LIST................................................................. C-8

1. OUTLINE

This manual has been written to provide guidance for troubleshooting of the OKIPAGE 20 Printer
(primarily for its printed circuit boards), on an assumption that the reader is knowledgeable of the
printer. Read the maintenance manual for this printer P/N 40300001TH if necessary.

Notes:

1. The power supply board containing a high voltage power supply is dangerous. From the
viewpoint of the safety standards, the local repairing of a defective board is not allowed. Thus,
the objects to be locally repaired as a result of troubleshooting are switches and fuses.

2. Replacement of CPU (MHM2029K) is not recommended. If CPU is founded to be defective,
board replacement is suggested.

2. TOOLS

For troubleshooting the printer, the tools listed below may be needed in addition to general
maintenance tools.

Tool Remarks
Oscilloscope
Soldering iron

Frequency response 100 MHz or higher
A slender tip type, 15-20 Watt

- 1 -

3. CIRCUIT DESCRIPTION

3.1 Outline

The control board controls the reception of data transferred through a host I/F and processes
command analysis, bit image development, raster buffer read. It also controls the engine and the
operator panel. Its block diagram is shown in Fig. 3-1.

(1) Reception control

The OKIPAGE 20 has one centronics parallel I/F port and one RS-232C serial I/F port.
Two I/F ports which receives data first can be used automatically.
The other I/F port outputs a busy state.
The centronics parallel I/F port can specify the following item when set by the control panel:

PARALLEL SPEED: HIGH/MEDIUM
BI-DIRECTION : ENABLE/DISABLE
I-PRIME : OFF/ON

The RS-232C serial I/F port can specify the following item when set by the control panel.
Flow control : DTRHI/DTRLO/XONXOFF/RBSTXON

Baud rate : 300/600/1200/2400/4800/9600/19200 (Baud)
Data bit : 7/8 (bit)
Minimum busy time: 200/1000 (ms)
Parity : NONE/ODD/EVEN

An interface task stores all data received from the host into a receive buffer first.

(2) Command analysis processing

The OKIPAGE 20 has the following emulation mode.
Laser Jet Series V : Hewlett Packard

Proprinter III XL : IBM
FX : EPSON
PostScript Level 2 : Adobe (Only when the PostScript SIMM is installed additionally.)

An edit task fetches data from the receive buffer, analizes commands, and reconstructs the
data in such a way that print data are aligned from up to down and from right to left; then it writes
the resultant data into a page buffer with such control data as print position coordinate, font
type, etc. added.

(3) Font Processing

When one page editing is finished, a developing task makes an engine start and fetches data
from the page buffer synchronizing with a printing operation; then it developes the fetched data
to a bit map as referring to data from a character generator, and writes the resultant data into
the raster buffer (of band buffer structure).

(4) Raster buffer read.

As controlling the engine operation, an engine task sends data from the raster buffer to the
LED head.

- 2 -

FLASH ROM

Module

or

PS ROM

Module

ROM

DRAM

Module

DRAM

MAIN BOARD(BOARD - AAA)

LSI

DUPLET unit

MULTI feeder

2nd tray

Paper end
sensor

Paper near end
sensor

BOARD PXC

3rd tray

Tray size
sensor boad

Parllel

I/F

RS232C

I/F

LAN etc.

(option)

POWER
SUPLY
UNIT
(AC120/230V)

Outlet sensor

7407

75188

OKI
HSP
Boad
(option)

3V 5V +8V -8V 38V

CPU

EEPROM

LSI

TRANSISTOR

TRANSISTOR

DRIVER

DRIVER

CL

CL

M

M

Operator panel

Inlet sensor 1
paper sensor
Inlet sensor 2
Toner sensor

Clutch for
Regist Roller

Clutch for
Hopping Roller

Hopping Motor

Main Motor

LED HEAD

THERMISTOR

LOW VOLTAGE

GENERATINO

CIRCUIT

FILTER CIRCUIT

AC120V/230V

COVER
OPEN
SW

DRIVER

DRIVER

POWER
SUPLY
UNIT
(high voltage)

Figure 3-1 Block Diagram

- 3 -

0V

HIGH

VOLTAGE

CIRCUIT

Sub-CH
CH
TR
DB
SB
CB

SUB CHARGE ROLLER

CHARG ROLLER

TRANSFER ROLLER
DEVELOPPING ROLLER
TONER SUPLY ROLLER

CLEANING ROLLER

FAN

HEATOR

3.2 CPU and Memory

(1) CPU (MHM2029-003K-41)

CPU core : RISC CPU (MIPS R3000 compatible)
CPU clock : 40.5504 MHz
Data bus width: Exterior 32 bits, Interior 32 bits

(2) ROM (HP LaserJet V emulation)

ROM capacity : 6 Mbytes (24-Mbit mask ROM two pieces)
ROM type : 24 Mbits (1.5M x 16 bits)
Access time : 100 ns

(3) Option ROM (SIMM: one slot)

PostScript SIMM or FLASH SIMM

• PostScript SIMM (Adobe PostScript emulation)
ROM capacity : 4 Mbytes (16 Mbit mask ROM two pieces)
ROM type : 16 Mbits (2M x 16 bits)
Access time : 100 ns

• FLASH SIMM
ROM capacity : 4 Mbytes (8 Mbit FLASH ROM four pieces)

ROM type : 8 Mbits (1M x 8 bits) or 16 Mbits (2M x 8 bits)
Access time : 90 ns

or 8 Mbytes (16 Mbit FLASH ROM four pieces)

(4) Resident RAM

RAM capacity : 4 Mbytes (16 Mbit D-RAM two pieces)
RAM type : 16 Mbits (1 M x 16 bits)
Access time : 60 ns

(5) Option RAM (SIMM: two slots)

RAM capacity : Max. 32 Mbytes (4 Mbytes, 8 Mbytes, 16 Mbytes, 32 Mbytes)
Access time : 60 ns, 70 ns, 80 ns, 100 ns

The block diagram of CPU and memory circuits is shown in Fig. 3-2.

- 4 -

RS232C I/F
Centronics

I/F

LED Head

Dram Motor
Driver

Power supply
(SSIO)

Sensor

Ope-Pane
EEPROM

(MHM2029-003K-41)

CPU

HIOCLK
SUBINT,SUBRDY

CADR
[1-24]

CDATA
[0-31]

CRD
CWR

CRAS[0-5]
CCAS[0-3]

(SSIO)

IOS1

CADR
[2-22]
CDATA

[0-31]
CS0
CRD

RAS0
CAS[0-3]

(LZ9FF22)
Sub Chip

Sensor
Power supply :THERMCMP,PSOUT
1st tray paper size detection
Hopping motor driver
Clutch driver
Duplex(SSIO)
Option(Multi/2nd/3nd)(SSIO)
DRAM SIMM :PD
FLASH SIMM :BSY0

OKI HSP NIC :CURST,OPDCT[0-3]

ROM(6MB:24Mbit MASK *2)

RAM(4MB:16Mbit DRAM *2)

Connected
to theCPU

CUREQ
MUPISINT
MUPISRDY

RAS[2-5]
CAS[0-3]

CS3

CS6

SIMM(For DRAM*2)

PD

SIMM(For PSMASKROM
or FLASHROM)

BSY0

OKI HSP NIC

Connected
to the LSI

CURST
OPDCT[0-3]

Figure 3-2 Block Diagram of CPU & Memory

- 5 -

3.3 Reset Control

When power is turned on, a RESET-N signal is generated by the rising sequence of +8V power
supply.

+8V

D1
(4.3V)

R33

4.3K

Ω

R26

2.2K

Ω

R32
430K

D501

R28
240K

Ω

+5V

R89
68K

IC20

3

+

2

–

UPC393

Ω

C35

0.22

µ

F

+5V

Ω

R508

3.3K

Ω

TR504

3

1

1

2

R509

3.3K

Ω

RESET-N 72

IC1

(MHM2029K)

ETC

+8V

IC20 UPC393

INPUT

IC20 UPC393

1 pin

RESET-N

+5V

Power ON

Power OFF

2 pin

3 pin

- 6 -

3.4 EEPROM Control

The NM93C46LN is an electrical erasable/programmable ROM of 64-bit x 16-bit configuration and
the NM93C66N is an electrical erasable/programmable ROM of 256-bit x 16-bit configuration.
Data input to and output from the ROM are bidirectionally transferred in units of 16 bits through
a serial I/O port (SERIALDATA-P) in serial transmission synchronized with a clock signal from the
CPU (IC1).

IC1

(MHM2029K)

SERIALDATA-P

154

EEPRMCS0-P

150

EEPRMCS1-P

165

EEPRMCLK-P

151

NM93C46LN

3

DI DO

1

CS

2

NM93C66N

3

DI DO

1

CS

2

SK

SK

(PS SIMM)

4

IC19
(AAA-PCB)

4

The EEPROM operates in the following instruction modes

Instruction Start Bit

Operation

Code

NM93C46LN

Address

NM93C66N

: Option

Data

Read (READ)
Write Enabled (WEN)
Write (WRITE)
Write All Address (WRAL)
Write Disabled (WDS)
Erase
Chip Erasable (ERAL)

1
1
1
1
1
1
1

10
00
01
00
00
11
00

A5 to A0

11XXXX 11XXXXXX

A5 to A0 A7 to A0

01XXXX 01XXXXXX
00XXXX 00XXXXXX

A5 to A0 A7 to A0

10XXXX 10XXXXXX

A7 to A0

D15 to D0
D15 to D0

- 7 -

CS
SK

CS

SK

DI

DO

Write cycle timing (WRITE)

101

HIGH-Z

A5/A7

Read cycle timing (READ)

A4/A6

A1 A0 D15

D14

Min. 450 ns

STATUS

D1 D0

Max. 500 ns

BUSY READY

Max. 10 ms

DI
DO

HIGH-Z

11 0

A5/A7 A4/A6

A1 A0

A5/A7

A4/A6

D1 D00

- 8 -

3.5 Centronics Parallel Interface

The CPU (IC1) sets a BUSY-P signal to ON at the same time when it reads the parallel data
(CENTDATA1-P to CENTDATA8-P) from the parallel port at the fall of STB-N signal. Furthermore,
it makes the store processing of received data into a receive buffer terminate within a certain fixed
time and outputs an ACK-N signal, setting the BUSY-P signal to OFF.

87, 88, 91 to 96

IC1

(MHM2029K)

97

85

86

83

81

79

80

82

84

CENTDATA1-P to CENTDATA8-P

STB-N
BUSY-P

ACK-N

PE-P

SEL-P

FAULT-N

IPRIME-N

SELIN-N

AUTOFEED-N

IC17

2 to 9

11

10

12

13

32

31

36

+5V 14

CENT

DATA8-P
DATA1-P
STB-N

1

BUSY-P

ACK-N
PE-P

SEL-P

FAULT-N

IPRIME-N
SELIN-N
AUTOFEED-N

to

CENTDATA
1~8-P

STB-N

BUSY-P

ACK-N

0.5 µs min.

0.5 µs min.

0.5 µs max.

0 min.

10 µs max.

+5V

18

FU1

1A

0.5 µs min.

0.5 µs min.

0 min.

0 min.

0 min.

- 9 -

3.6 RS232C Interface

The serial data RXD from the host system, whose line voltage is clamped at the TTL level by D502/
D503, are received by the CPU built-in serial controller.
DSR, CTS and CD are not connected. Send signals TXD, RTS and DTR are put out from the CPU
and are sent to lines through a line driver IC (75188).

CPU

RXD-N

101

108
102

103

TXD-P
RTS-N
DTR-N

D502

+5V

RS232C

D503

3.3K

3.3K

2

75188

4

IC18

9

3
6
8

Idle

Idle
Idle

Idle

20

RXD

3

DSR

6

CTS

5

CD

1

TXD

2

RST

4

DTR
SSD

9

14 1

+8V -8V

(1) Send signal level (2) Receive signal level

Input 0V

Output 0V

TTL level

Input 0V

+8V

- 8V
Output 0V

+8V

- 8V

TTL level

- 10 -

3.7 Operator Panel Control

The operator panel consists of the following circuits.

AAA- PCO-

IC1

(MHM2029K)

SERIALDATA-P
154

PDATAIN-P
158

PSCLK-N
153

PLD-N
152

3
4

6

1

Flexible

Cable

CN1PANEL

4

3

1
6

(1) BU6152S (LSI)

This LSI is connected to a clock synchronous serial port of the CPU (IC1). It controls switch
data input, LED data output and LCD data input/output according to the commands given by
the CPU. The CPU sends the 2-byte (16-bit) command (SERIALDATA-P) together with the
shift clock signal (PCLK-N) to the LSI and then makes a predetermined input/output control
if the command decoded by the LSI is found to be a normal command.

BU6152S

LSI

DB4~DB7

RS
R/W

E

LED

44780
LCD
Control
Driver

Zebra Rubber

LCD

On receiving a command sent from the CPU, the LSI, synchronizing with the serial clock of
the command, returns a 2-byte command response to the CPU.

SERIALDATA-P

PSCLK-N

PDATAIN-P

PLD-N

bit 0 bit 15

Command

bit 0

Command response

bit 15

- 11 -

3.8 LED Head Control

AAA-

IC1

(MHM2029K)

181

180

144

143

HDCLK-P

142

HDDLD-P

139

HDSTB4-N

135

HDSTB3-N

136

HDSTB2-N

137

HDSTB1-N

138

HDD3-P

HDD2-P

HDD1-P

HDD0-P

HEAD 1

10

11

7

8

13

5

1

2

3

4

LED Head

EEPROM

5

4

8

7

2

10

14

13

12

11

Driver IC Driver IC

Driver IC Driver IC

38

Data is transferred to the head unit starting with the data at the left end of the paper in the
synchronous serial transfer mode using the HDCLK-P signal as the sync signal.

The total number of LEDs in the head unit is 4992. The data for the driver latches causes the
corresponding LEDs to light only during the time when the HDSTBn-N signal is output. There are
four HDSTBn-N signals (HDSTB1-N, HDSTB2-N, HDSTB3-N, and HDSTB4-N), each of which
controls the corresponding driver for 1248 LEDs (4992/4).

The four HDSTBn-N signals must be output within the time when the LEDs for one line continue
to emit light. After the data is moved to the latches by the HDSTBn-N signal, the transfer of the
data of the next line can be started.

- 12 -

The timing chart for the outline of this operation is shown below.

HDCLK-P
HDD0-P

HDD1-P
HDD2-P

1

59
2 6 10 4986 4990
3

11 4987 4991

7

4985

4989

✰

The LED lights
when the head
data is HIGH.

HDD3-P

HDCLK-P
HDD0-P

HDD1-P
HDD2-P

HDD3-P

HDDLD-P
HDSTB1-N

HDSTB2-N
HDSTB3-N
HDSTB4-N

4 8 12 4988 4992

Each figure denotes the dot
position taking the left end bit
position as "1".

Print activation
timing for the
1st line

LEDs

1-2496

lit

LEDs

2497-4992

lit

Print activation timing
for the 2nd line

Print activation timing
for the final line

- 13 -

3.9 Motor Control

OKIPAGE20 controls the paper flow by two motors (main motor & hopping motor) and two clutches
(clutch for feeding roller and clutch for regist roller).

(1) Main motor

The main motor is driven by the driver IC according to the control signal from the CPU (IC1:
MHM2029K).

DMON-N

DMPH1-P

DMPH2-P

Rotation

AAA-PCB

IC1

(MHM2029K)

T0 T1 T2 T3

DMPH1-P

132

DMPH2-P

131

DMON-N

127

13

8

7, 14

Forward rotation

MAIN

(A2918)

1

17

2

4

MOTOR

1

2

3

4

Main

Motor

M

Reverse rotationStop

Operation at normal speed: T0 to T3 = 703

µ

s

- 14 -

(2) Hopping motor

The hopping motor is driven by the driver IC according to the control signal from the LSI (IC2:
LZ9FF22).

HMON-N

HMPH1-P

HMPH2-P

Rotation

AAA-PCB

IC2

(LZ9FF11)

T0 T1 T2 T3

HMPH1-P

57

HMPH2-P

58

HMON-N

75

13

8

7, 14

Forward rotation

HOPPING

(A2918)

FRONT

1

1

2

17

3

2

4

4

Hopping

Motor

M

JackIn
connector (22P)

Reverse rotationStop

Operation at normal speed: T0 to T3 = 918

µ

s

(3) Clutch for feeding roller and clutch for regist roller

Clutch for feeding roller and clutch for regist roller are driven by the driver IC according to the
control signal from the LSI (IC2: LZ9FF22).

AAA-

IC2

(LZ9FF22)

PWM1-P

74

PWM2-P

59

+5VD

+5VD

0V

0V

TR505

TR506

TR1

TR2

+38V

+38V

0VP

0VP

CLH

1

2

3

CLR

1

2

Clutch for feeding roller

Clutch for regist roller

- 15 -

3.10 Fuser Temperature Control

For the temperature control by heater control, the variation in the resistance of the thermistor is A/
D converted in and the resultant digital value is read and transferred to the CPU. The CPU turns
on or off the HEATON-N signal according the value of the signal received from to keep the
temperature constant.

Immediately after the power is turned on, the thermistor is checked for shortcircuit and breakdown.
If the thermistor is shorted, the A/D converted value shows an extremely high temperature, so that
the shortcircuit can be detected. If the breakdown of the thermistor occurs, the A/D converted value
shows the normal temperature. In this case, the thermistor breakdown can be detected by the
sequence shown at the end of this section. If the heater is overheated, 5V supply is turned off by
detecting that the resistance of the thermistor exceeds the predetermined value.

Ther­mistor

Heater

Thermostat

CN8

1

2

CN2

1
2

Power Supply Board

5V

36

Thermistor
breakdown

detector

circuit

5V

PC1

AAA-

IC1 IC1

(MHM2029K)

Power
supply

interface

ACIN

HEATON-N

116

TR5

+5VD

+5V

TR4

- 16 -

The temperature control is described below.

Vt

Temperature

˚C

V2

V1

ON OFF ON OFF ONHEATON-N

V2 192˚C
V1

169˚C

* The values V1 and V2 vary according to setting mode.

(Standard paper : MEDIA TYPE = MEDIUM)

When Vt rises to V2 or more, the heater is turned off (by setting HEATON-N signal to HIGH). When
Vt drops to V1 or less, the heater is turned on (by setting HEATON-N signal to LOW). In this way,
the temperature can be kept within the predetermined range.

- 17 -

To detect the breakdown of the heater, the heater is turned on. If the corresponding temperature
rise is not detected, it is judged that heater breakdown occurs. To shorten the breakdown detecting
time, the following circuit is used. When the thermistor is checked for breakdown immediately after
the power is turned on, the THERMCHK-N signal is turned on to turn transistor Q5 off. As a result,
the thermistor serial resistance is varied to increase the reading resolution.

5V

Ther­mistor

A/D

converter

5V

THERMCHK-NFROM IC2 (LZ9FF22)

- 18 -

3.11 Fan Motor Control

The stop/rotation of the fan motor is controlled by a FANON-P signal. When the fan motor rotates
normally, a FANALM-N signal generated in the hole element built in the fan motor is input to the
CPU.

AAA-

IC1

(MHM2029K)

FANON-P
FANALARM-N

IC17

QC

109

FANALARM-N

110

+5VD

FANON-P

Power Supply Board

+38V

FAN Motor

M

1 sec max

0.7 sec max

FAN MOVE

Lock

- 19 -

Fan motor start:Initial request, heater on, print start request
Fan motor stop: • The motor immediately stops when an engine error or a fan error occurs.

• The motor stops 30 seconds after the occurrence of a paper jam, size error, or
fuse error.

• The motor stops in the power save mode as below.

Main motor

Heater control

Fan motor

ON

Heater

hold time

8 min.

or 0 min.

Rotation state

OFF

OFFON

30 sec.

Stop state

- 20 -

3.12 Sensor Supervision

OKIPAGE20 unit is provided with 11 sensors.
The signals of Toner sensor and Inlet sensor 2 among these sensors are read through the Power
supply interface.
Other sensor signals are read directly from the input ports of CPU (IC1: MHM2029K) and LSI (IC2:
LZ9FF22).
Also, regarding Inlet sensor 1 signal, Paper sensor signal and Outlet sensor signal, their changed
status can be notified as a CPU interruption.
In addition, these three signals can be read through the Power supply interface.

to Duplex unit

to Duplex unit

to

2nd/3rd paper feeder

and Multi feeder

AAA-PCB

81

IC20

164 120

IC2

(LZ9FF22)

IC1

(MHM2029K)

15to18

21

80

73

123

1st tray

PXC­PCB

Power supply board

Paper size sensor board

Paper end sensor

Paper low sensor

LSI

Outlet sensor

Paper sensor

Inlet sensorl

Power supply
interface

121

160

159

- 21 -

Inlet sensor2

Toner sensor

Front feeder

Paper end sensor

Home position sensor

Stacker cover

Stacker full sensor

3.13 Cover Open

When the cover is opened, a cover open microswitch is opened. This makes a XCOVEROPEN­N signal low, then off the +5VD, thereby the CPU detects the open state. Furthermore, opening
the cover stops applying a +38V power to the high voltage power supply unit, resulting in stopping
all high voltage outputs.

AAA-

CPU

+5V

125

+5VD

COVEROPEN-N

+5VD

0V

Power Supply Board

+38V

COVEROPEN-N

Cover Open
Microswitch

+38V

Cover close Cover open

Low Voltage

Supply Unit

Power

High

Voltage

Power
Supply

Unit

High

voltage

output

- 22 -

3.14 Power Supply Interface

The power supply interface is a 16 bit clock synchronous serial interface between the synchronous
serial I/O ports of CPU (IC1: MHM2029K) and the power control LSI in the power supply board
(High voltage) under the control of the CPU (IC1: MHM2029K).

When the control section transmits a command on POWTXD-P signal in synchronization with the
clock (POWSCLK-N) to the power supply board, this power supply board transmits a response on
POWRXD-P signal in synchronization with the same clock to the control section.

The commands include the control data of the high-voltage power supply, etc.
The responses include sensor information, fuser unit temperature information, etc.

AAA-PCB Power Supply Board

POWTXD-P

POWSCLK-N

POWRXD-P

POWLD-N

IC1

(MHM2029K)

Power Supply Board
(120V or 230V)

POWER CN3 CN6 CN7

POWTXD-P

112

POWSCLK-N

111

POWRXD-P

119

POWLD-N

115

LSB

b0 b1 b2 b3 b4 b5 b6 b7 b8 b9 b10 b11 b12 b13 b14 b15

b0 b1 b2 b3 b4 b5 b6 b7 b8 b9 b10 b11 b12 b13 b14 b15

3

3

2

2

4

4

1

1

11
12
10
13

Command

Response

(High voltage)

22

11

2

12

25

10

1

13

LSI

MSB

- 23 -

3.15 Option (2nd/3rd paper feeder and Multi feeder) Interface

The option interface is a 8 bit clock synchronous serial interface between the synchronous serial
I/O ports of LSI (IC2: LZ9FF22) and 4 bit micro-controllers in the option control boards under the
control of the CPU (IC1: MHM2029K).
First the control section transmits a command on OPDATA-P signal in synchronization with the
clock (OPSCLK-N) to the option.
The option which receives the command will analyze it and assert OPSDR-N signal after becoming
a ready state for returning a response. When the control section recognizes the OPSDR signal
asserted, it will output a clock signal only at this time.
The option will output a response on the OPDATA-P signal line in synchronization with this clock
signal (OPSCK-N).
The commands include the control data, etc.
The responses include sensor information, etc.

Jackln connector
(14P)

CN1

5

6

4

AOLE-PCB (Multi feeder)

AAA-PCB

IC1

(MHM2029K)

IC2

(LZ9FF22)

82

OPDATA-P

84

OPSCLK-N

83

OPSDR-N

Jackln connector
(22P)

ENVELOPE

3

2

4

Control
circuit

2NDTRAY

3

2

4

Jackln connector
(14P)

Jackln connector
(14P)

BBB-PCB (2nd paper feeder)

MAIN1

3

2

4

MAIN2

3

2

4

BBB-PCB (3rd paper feeder)

MAIN1

3

2

4

Control
circuit

Control
circuit

OPDATA-P

OPSCLK-N

OPSDR-N

COMMAND RESPONSE

b0 b1 b2 b3 b4 b5 b6 b7 b0 b1 b2 b3 b4 b5 b6 b7

- 24 -

3.16 DUPLEX Interface

The Duplex interface is a 8 bit clock synchronous serial interface between the synchronous serial
I/O ports of LSI (IC2: LZ9FF22) and 8 bit micro-controllers in the option control boards under the
control of the CPU (IC1: MHM2029K).
First the control section transmits a command on DUPDATA-P signal in synchronization with the
clock (DUPSCLK-N) to the Duplex unit.
The Duplex unit which receives the command will analyze it and assert OPSDR-N signal after
becoming a ready state for returning a response. When the control section recognizes the OPSDR
signal asserted, it will output a clock signal only at this time.
The Duplex unit will output a response on the OPDATA-P signal line in synchronization with this
clock signal (OPSCK-N).
The commands include the control data, etc.
The responses include sensor information, etc.

AAA-PCB

IC1

(MHM2029K)

IC2

(LZ9FF22)

86

DUPDATA-P

88

DUPSCLK-N

87

DUPSDR-N

DUP

9

8

11

Jackln connerctor
(14P)

LEX-PCB (Duplex unit)

MAIN

9

8

11

Control
circuit

DUPDATA-P
DUPSCLK-N
DUPSDR-N

COMMAND RESPONSE

b0 b1 b2 b3 b4 b5 b6 b7 b0 b1 b2 b3 b4 b5 b6 b7

- 25 -

3.17 Power Supply Board

The power supply circuit consists of the low-voltage power supply circuit and the high-voltage
power supply circuit. The low-voltage power supply circuit adopts a switching power supply system
and provides DC voltages required for the control of the equipment. The high-voltage power supply
circuit receives +38V power from the low-voltage power supply circuit and provides various high
voltages required for the electrophotographic process according to the control signals from the
control section.

(1) Low-voltage power supply circuit

SW

F2

Noise

filter

ACIN

circuit

Switching

circuit

Rectifying/

smoothing/

regulating

circuit

+8V
–8V

+5V
+3.3V

POW ON

+ 5V
+ 3.3V

+ 38V

+ 8V
– 8V

Switching

control

circuit

Overvoltage/

overcurrent

detector

circuit

Rectifying/

smoothing/

regulating

circuit

+38V

- 26 -

(2) High-voltage power supply circuit

This high-voltage power supply circuit receives the high-voltage generation timing control
command that is transmitted in serial through the power supply interface from the control
section. It decodes this command by LSI (IC1) and outputs high-frequency pulses to the
corresponding high-voltage generating circuits through pins 12, 13, 14, 15, 16, 17 and 18 of
LSI (IC1). It supplies +38V to each high-voltage generating circuit as the source voltage.
When the cover is open, the supply of +38V is interrupted to interrupt all the high-voltage
outputs. The relationship between the high-frequency pulse output pins and the high-voltage
outputs is shown in the following table.

Power Supply Board (High voltage)

+38V

CPU

Power supply

interface

LSI

14

16

12
17

11
15

DB+

DB–

CB

TR

SB
DB

CB

TR

High-voltage

High

-frequency
pulse output pins

outputs

11
12
13
14
15
16

-450V
17
18

CC : Constant Current
CV : Constant Voltage

13

18

SB DB TR CH CL

CB

CH

CL

CC : 0~20µA
CV : 0~5KV

+450V

-1.3KV

0V

+300V

-1.3KV

-220V

-1.35KV
CC : -15

Part with slant line: no output

CH

CL

µ

A

- 27 -