OKI 16n Troubleshooting Manual

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OKIPAGE 16n
LED Page Printer

Troubleshooting Manual
with Component Parts List

Approval

All specifications are subject to change without notice.

CONTENTS

1. OUTLINE............................................................................................................ 1

2. TOOLS ............................................................................................................... 1

3. CIRCUIT DESCRIPTION.................................................................................... 2

3.1 Outline ...................................................................................................... 2

3.2 CPU and Memory..................................................................................... 4

3.3 Reset Control ........................................................................................... 6

3.4 EEPROM Control ..................................................................................... 7

3.5 Centronics Parallel Interface .................................................................... 9

3.6 Operator Panel Control........................................................................... 10

3.7 LED Head Control .................................................................................. 11

3.8 Motor Control.......................................................................................... 13

3.9 Fuser Temperature Control .................................................................... 15

3.10 Fan Motor Control................................................................................... 18

3.11 Sensor Supervision ................................................................................ 20

3.12 Cover Open ............................................................................................ 21

3.13 Power Supply Interface .......................................................................... 22

3.14 Power Supply Board............................................................................... 23

4. TROUBLESHOOTING ..................................................................................... 25

4.1 Troubleshooting Table............................................................................ 25

4.2 Troubleshooting Flowchart ..................................................................... 29

5. CIRCUIT DIAGRAM ......................................................................................... 43

6. COMPONENT PARTS LIST ............................................................................ 73

APPENDIX A HIGH CAPACITY SECOND PAPER FEEDER (OPTION) ....... A-1

1. CIRCUIT DESCRIPTION................................................................................ A-1

2. TROUBLESHOOTING ................................................................................... A-3

3. CIRCUIT DIAGRAM ....................................................................................... A-8

4. COMPONENT PARTS LIST ........................................................................ A-11

APPENDIX B POWER ENVELOPE FEEDER (OPTION) ............................... B-1

1. CIRCUIT DESCRIPTION................................................................................ B-1

2. TROUBLESHOOTING ................................................................................... B-3

3. CIRCUIT DIAGRAM ....................................................................................... B-7

4. COMPONENT PARTS LIST ........................................................................ B-10

1. OUTLINE

This manual has been written to provide guidance for troubleshooting of the OKIPAGE 16n Printer
(primarily for its printed circuit boards), on an assumption that the reader is knowledgeable of the
printer. Read the maintenance manual for this printer P/N 40029801TH (ODA) and/or P/N
40029803TH (OEL) if necessary.

Notes:

1. The power supply board containing a high voltage power supply is dangerous. From the
viewpoint of the safety standards, the local repairing of a defective board is not allowed. Thus,
the objects to be locally repaired as a result of troubleshooting are switches and fuses.

2. Replacement of CPU (MHM2029K) is not recommended. If CPU is founded to be defective,
board replacement is suggested.

2. TOOLS

For troubleshooting the printer, the tools listed below may be needed in addition to general
maintenance tools.

Tool Remarks
Extension kit 4YA4046-1667G1
Connector extractor tool
Oscilloscope
Soldering iron

4PP4076-5395P1
Frequency response 100 MHz or higher
A slender tip type, 15-20 Watt

- 1 -

3. CIRCUIT DESCRIPTION

3.1 Outline

The control board controls the reception of data transferred through a host I/F and processes
command analysis, bit image development, raster buffer read. It also controls the engine and the
operator panel. Its block diagram is shown in Fig. 3-1.

(1) Reception control

The OKIPAGE 16n has one centronics parallel I/F port .
When optional PostScript board is installed, the printer is provided with one LocalTalk serial
I/F port. One of the two I/F ports which receives data first can be used automatically.
The other I/F port outputs a busy state.
The centronics parallel I/F port can specify the following item when set by the control panel:

PARALLEL SPEED: HIGH/MEDIUM
BI-DIRECTION : ENABLE/DISABLE
I-PRIME : OFF/ON

An interface task stores all data received from the host into a receive buffer first.

(2) Command analysis processing

The OKIPAGE 16n has the following emulation mode.
Laser Jet Series IV : Hewlett Packard

Proprinter III XL : IBM
FX : EPSON
PostScript Level 2 : Adobe (Only when the PostScript board is installed additionally.)

An edit task fetches data from the receive buffer, analizes commands, and reconstructs the
data in such a way that print data are aligned from up to down and from right to left; then it writes
the resultant data into a page buffer with such control data as print position coordinate, font
type, etc. added.

(3) Font Processing

When one page editing is finished, a developing task makes an engine start and fetches data
from the page buffer synchronizing with a printing operation; then it developes the fetched data
to a bit map as referring to data from a character generator, and writes the resultant data into
the raster buffer (of band buffer structure).

(4) Raster buffer read.

As controlling the engine operation, an engine task sends data from the raster buffer to the
LED head.

- 2 -

ROM SRAM

CPU

DS8925

LS374

LS374

ROM

PSBA­(Option)

EE
PROM

*: Only when the PostScript
board (PSBA-PCB) is
installed additionally.

LOCAL TALK

*

Interface

Parallel
Interface

OKI HSP
(Option)

COM-

Paper sensor

ROM

D RAM

SIMM

(Option)

7407

+8V

-8V

SW

LSI

CPU

DA

+5V

converter

+38V

0V

Heat on

DRIVER

EE
PROM

AOLC-

SW

LED head
Operator panel

2nd tray

Envelope tray

Home micro switch

Stacker full sensor

Paper end sensor

Hopping motor

M

AOLS-

(Option)

(Option)

Paper size
detection switch

Inlet sensor 1

Inlet sensor 2

Outlet sensor

Paper out sensor

Toner sensor

Filter

circuit

Power Supply board

DRIVER

DRIVER

DRIVER

LSI

Cover
open MS

Low voltage

generation circuit

Heat on

High voltage

generation

circuit

Driver

Figure 3-1 Block Diagram

- 3 -

CH
TR

DB
SB

CB

+5V

TH1

TH2

M
M

FAN

Charge roller
Transfer roller
Developing roller
Toner supply roller
Cleaning roller

Heater

Resist motor

Drum motor

DC FAN

Thermistor

3.2 CPU and Memory

(1) CPU (MHM2029-004K-37)

CPU core : RISC CPU (MIPS R3000 compatible)
CPU clock : 31.9488 MHz
Data bus width: Exterior 32 bits, Interior 32 bits

(2) ROM (HP LaserJet IV emulation)

ROM capacity : 4 Mbytes (16-Mbit mask ROM two pieces)
ROM type : 16 Mbits (1M x 16 bits)
Access time : 100 ns

(3) ROM (Adobe PostScript emulation) (Option)

ROM capacity : 4 Mbytes (16-Mbit mask ROM two pieces)
ROM type : 16 Mbits (1M x 16 bits)
Access time : 100 ns

(4) Resident RAM

RAM capacity : 2 Mbytes (4-Mbit D-RAM four pieces)
RAM type : 4 Mbits (512k x 8 bits)
Access time : 80 ns

(5) SIMM (When the PostScript board is installed, 4 Mbytes SIMM shall be installed at the time

of installation.)
RAM capacity : Max. 32 Mbytes (1 Mbyte, 2 Mbytes, 4 Mbytes, 8 Mbytes, 16 Mbytes,

Access time : 60 ns, 70 ns, 80 ns, 100 ns

32 Mbytes)

The block diagram of CPU and memory circuits is shown in Fig. 3-2.

- 4 -

CPU

CDATA 16

~ CDATA 31

Bus

buffer

245 x 2

D15~D31

RAS0
RAS2

~RAS5

buffer

244

CDATA 0

~ CDATA 15

CADR01 ~ CADR25

CCAS0 ~ CCAS3

CRD CWR

CS0
CS2

RAS00
SIMMRAS 10, 11

SIMMRAS 20, 21

Bus

buffer

245 x 2

Bus

buffer

244 x 4

CAS0~3
RD
WR

D0~D15

A21~A2

A21~A2

A21~A2

A21~A2

HP ROM1

16 M

MASK ROM

CS
RD

HP ROM2

16 M

MASK ROM

CS
RD

PS ROM1

16 M

MASK ROM

CS
RD

PS ROM2

16 M

MASK ROM

CS
RD

*1

*1: PSBA-PCB

(Option)

RAS00

DRAM

4M

DRAM

4M

SIMM1

A10

~A23

A20~A10

RD

WR

CAS0, CAS1

RAS00

A20~A10

RD
WR

CAS2, CAS3

WR CAS0~3

SIMM2

Figure 3-2 Block Diagram of CPU & Memory

- 5 -

D0~D31

3.3 Reset Control

When power is turned on, a RESET-N signal is generated by the rising sequence of +8V power
supply.

+8V

+5V

+5V

R554

4.3K

R527

2.2K

+8V

Ω

Ω

Power ON

D8
(4.3V)

R530
240K

CPU

RESET-N 72

Q25

3

+

D1

2

3 pin

C570

0.22

µ

F

2 pin

Ω

–

UPC393

1

TR2

3

2

1

ETC

Power OFF

Q25 UPC393

INPUT

Q25 UPC393

1 pin

RESET-N

+5V

- 6 -

3.4 EEPROM Control

The 93LC46A is an electrical erasable/programmable ROM of 64-bit x 16-bit configuration and the
NM93C66N is an electrical erasable/programmable ROM of 256-bit x 16-bit configuration. Data
input to and output from the ROM are bidirectionally transferred in units of 16 bits through a serial
I/O port (SERIALDATA-P) in serial transmission synchronized with a clock signal from the CPU.

CPU

SERIALDATA-P

154

EEPRMCS0-P

150

EEPRMCS1-P

165

EEPRMCLK-P

151

93LC46A

3

DI DO

1

CS

NM93C66N

3

DI DO

1

CS

SK

2

SK

2

4

Q12
(COM-PCB)

4

06H
(PSBA-PCB)

The EEPROM operates in the following instruction modes

Instruction Start Bit

Operation

Code

Address

93LC46A

NM93C66N

: Option

Data

Read (READ)
Write Enabled (WEN)
Write (WRITE)
Write All Address (WRAL)
Write Disabled (WDS)
Erase
Chip Erasable (ERAL)

1
1
1
1
1
1
1

10
00
01
00
00
11
00

A5 to A0

11XXXX 11XXXXXX

A5 to A0 A7 to A0

01XXXX 01XXXXXX
00XXXX 00XXXXXX

A5 to A0 A7 to A0

10XXXX 10XXXXXX

A7 to A0

D15 to D0
D15 to D0

- 7 -

CS
SK

CS

SK

DI

DO

Write cycle timing (WRITE)

A5/A7

101

A4/A6

HIGH-Z

Read cycle timing (READ)

A1 A0 D15

D14

Min. 450 ns

STATUS

D1 D0

Max. 500 ns

BUSY READY

Max. 10 ms

DI
DO

HIGH-Z

11 0

A5/A7 A4/A6

A1 A0

A5/A7

A4/A6

D1 D00

- 8 -

3.5 Centronics Parallel Interface

The CPU sets a BUSY-P signal to ON at the same time when it reads the parallel data
(CENTDATA1-P to CENTDATA8-P) from the parallel port at the fall of STB-N signal. Furthermore,
it makes the store processing of received data into a receive buffer terminate within a certain fixed
time and outputs an ACK-N signal, setting the BUSY-P signal to OFF.

87, 88, 91 to 96

CPU

97

85

86

83

81

79

80

82

84

CENTDATA1-P to CENTDATA8-P

STB-N
BUSY-P

ACK-N

PE-P

SEL-P

FAULT-N

IPRIME-N

SELIN-N

AUTOFEED-N

Q26

2 to 9

11

10

12

13

32

31

36

+5V 14

CENT

DATA8-P
DATA1-P
STB-N

1

BUSY-P

ACK-N
PE-P

SEL-P

FAULT-N

IPRIME-N
SELIN-N
AUTOFEED-N

to

CENTDATA
1~8-P

STB-N

BUSY-P

ACK-N

0.5 µs min.

0.5 µs min.

0.5 µs max.

0 min.

10 µs max.

0.5 µs min.

0.5 µs min.

0 min.

FU2

1A

0 min.

18

+5V

0 min.

- 9 -

3.6 Operator Panel Control

The operator panel consists of the following circuits.

COM OLNC-

CPU

SERIALDATA-P
154

PDATAIN-P
158

PSCLK-N
153

PLD-N
152

3
4

6

1

Flexible

Cable

CN1PANEL

4

3

1
6

(1) BU6152S (LSI)

This LSI is connected to a clock synchronous serial port of the CPU. It controls switch data
input, LED data output and LCD data input/output according to the commands given by the
CPU. The CPU sends the 2-byte (16-bit) command (SERIALDATA-P) together with the shift
clock signal (PCLK-N) to the LSI and then makes a predetermined input/output control if the
command decoded by the LSI is found to be a normal command.

BU6152S

LSI

DB4~DB7

RS
R/W

E

LED

44780
LCD
Control
Driver

Zebra Rubber

LCD

On receiving a command sent from the CPU, the LSI, synchronizing with the serial clock of
the command, returns a 2-byte command response to the CPU.

SERIALDATA-P

PSCLK-N

PDATAIN-P

PLD-N

bit 0 bit 7

Command (first)

bit 0

Command response (first) Command response (second)

bit 7

Command (second)

- 10 -

3.7 LED Head Control

COM-

CPU 31701-040

OSTACK-N

107

137

OSTREQ-N

105

138

FSYNC-N

89

145

LSYNC-N

90

146

12

10

4

3

2

5

9

8

7

6

HDD3-P

HDD2-P

HDD1-P

HDD0-P

HDCLK-P

HDDLD-P

HDSTB4-N

HDSTB3-N

HDSTB2-N

HDSTB1-N

HEAD 1

10

11

7

8

13

5

1

2

3

4

LED Head

EEPROM Driver IC

5

4

8

7

2

10

14

13

12

11

Driver IC

39

Driver IC

38

38

Data is transferred to the head unit starting with the data at the left end of the paper in the
synchronous serial transfer mode using the HDCLK-P signal as the sync signal.

Driver IC

1

The total number of LEDs in the head unit is 4992. The data for the driver latches causes the
corresponding LEDs to light only during the time when the HDSTBn-N signal is output. There are
four HDSTBn-N signals (HDSTB1-N, HDSTB2-N, HDSTB3-N, and HDSTB4-N), each of which
controls the corresponding driver for 1248 LEDs (4992/4).

The four HDSTBn-N signals must be output within the time when the LEDs for one line continue
to emit light. After the data is moved to the latches by the HDSTBn-N signal, the transfer of the
data of the next line can be started.

- 11 -

The timing chart for the outline of this operation is shown below.

HDCLK-P
HDD0-P

HDD1-P
HDD2-P

1

59
2 6 10 4986 4990
3

11 4987 4991

7

4985

4989

✰

The LED lights
when the head
data is HIGH.

HDD3-P

HDCLK-P
HDD0-P

HDD1-P
HDD2-P

HDD3-P

HDDLD-P
HDSTB1-N

HDSTB2-N
HDSTB3-N
HDSTB4-N

4 8 12 4988 4992

Each figure denotes the dot
position taking the left end bit
position as "1".

Print activation
timing for the
1st line

LEDs
1-1280 lit

LEDs
1281-2560 lit

Print activation timing
for the 2nd line

Print activation timing
for the final line

- 12 -

3.8 Motor Control

(1) Resist motor and Drum motor

A resist motor and a drum motor are driven by means of control signals from the CPU or the
LSI (31701) and a driver IC.

COM- AOLC-

POWER

CPU A2918

31701
LSI

DMPH1-P 12

132

DMON-N 9

127

DMPH2-P 11

131

RMON-N

128

0STPH1-P 6

25

0STPH2-P 8

20

7

a. Drum motor

CN9

XDMPH1-P 13

12

DMON-N 7,14

9

XDMPH2-P 8

11

RM-PMPHP1-P 13
7

RMON-N 7,14

6

RM-PMPHP2-P 8
8

IC1

IC2

A2918

+38V

+38V

DMPH1-N 1

1

DMPH1-P 2

17

DMPH2-N 3

2

DMPH2-P 4

4

RMT1-P 1

1

RMT2-P 2

17

RMT3-P 3

2

RMT4-P 4

4

CN6

CN7

Drum
Motor

M

Resist

Motor

M

DMON-N

XDMPH1-P

XDMPH2-P

Rotation

T0 T1 T2 T3

Forward rotation

Operation at normal speed: T0 to T3 = 918

Reverse rotationStop

µ

s

- 13 -

RMON-N

RM/PMPH1-P

b. Resist motor

RM/PMPH2-P

T0 T1 T2 T3

Rotation Forward rotation

Stop

Hopping drive

Operation at normal speed: T0 to T3 = 918

c. Drive control

Time T0 to T3 determines the motor speed, while the phase different direction between
phase signals XDMPH1-P and XDMPH2-P (0STPH1-P and 0STPH2-P) determines the
rotation direction. DMON-N and RMON-N signals control a motor coil current.

(2) Hopping motor

The hopping motor is driven by the driver IC according to the control signal from the CPU. The
hopping motor drives either the hopping roller of the 1st tray or the hopping roller of the front
feeder depending on its rotation.

COM-

CPU

RM/PMPH2-P

133

RM/PMPH1-P

134

PMON-N

126

15

14

2

+38V

M54646

4

10

25
19

PMT1-P

PMT2-P

PMT3-P
PMT4-P

FRONT

µ

s

Hopping

Motor

M

PMON-N

RM/PMPH1-P

RM/PMPH2-P

Rotation

T0 T1 T2 T3

Forward rotation

Operation at normal speed: T0 to T3 = 918

- 14 -

Reverse rotationStop

µ

s

3.9 Fuser Temperature Control

For the temperature control by heater control, the variation in the resistance of the thermistor is A/
D converted in IC501 and the resultant digital value is read and transferred to the CPU. The CPU
turns on or off the HEATON-N signal according the value of the signal received from IC501 to keep
the temperature constant.

Immediately after the power is turned on, the thermistor is checked for shortcircuit and breakdown.
If the thermistor is shorted, the A/D converted value shows an extremely high temperature, so that
the shortcircuit can be detected. If the breakdown of the thermistor occurs, the A/D converted value
shows the normal temperature. In this case, the thermistor breakdown can be detected by the
sequence shown at the end of this section. If the heater is overheated, 5V supply is turned off by
detecting that the resistance of the thermistor exceeds the predetermined value.

Ther-

mistor

Heater

Thermostat

TH1

TH2

CN2

1
2

Power Supply Board

5V

5V OFF

signal

-

+

40

Thermistor
breakdown

detector

circuit

5V

PC1

COM-

IC501 CPU

Power
supply

interface

ACIN

HEATON-N

116

TR503

+5VD

+5V

TR1

- 15 -

The temperature control is described below.

Vt

Temperature

˚C

V2

V1

ON OFF ON OFF ONHEATON-N

V2 194˚C
V1

190˚C

* The values V1 and V2 vary according to setting mode.

(Standard temperature)

When Vt rises to V2 or more, the heater is turned off (by setting HEATON-N signal to HIGH). When
Vt drops to V1 or less, the heater is turned on (by setting HEATON-N signal to LOW). In this way,
the temperature can be kept within the predetermined range.

- 16 -

To detect the breakdown of the heater, the heater is turned on. If the corresponding temperature
rise is not detected, it is judged that heater breakdown occurs. To shorten the breakdown detecting
time, the following circuit is used. When the thermistor is checked for breakdown immediately after
the power is turned on, the THERMCHK-N signal is turned on to turn transistor Q511 on. As a
result, the thermistor serial resistance is varied to increase the reading resolution.

5V

Ther­mistor

R534

5V

R551

Q511

THERMCHK-NFROM LSI (31701)

IC501

A/D

converter

- 17 -

3.10 Fan Motor Control

The stop/rotation of the fan motor is controlled by a FANON-P signal. When the fan motor rotates
normally, a FANALM-N signal generated in the hole element built in the fan motor is input to the
CPU.

COM-

CPU

FANON-P
FANALARM-N

Q26

QC

109

FANALARM-N

110

+5VD

FANON-P

AOLC

Power Supply Board

+38V

Q201

Q109

FAN Motor

M

1 sec max

0.7 sec max

FAN MOVE

Lock

- 18 -

Fan motor start: Initial request, heater on, print start request
Fan motor stop: • The motor immediately stops when an engine error or a fan error occurs.

• The motor stops 30 seconds after the occurrence of a paper jam, size error, or
fuse error.

• The motor stops in the power save mode as below.

Drum motor

Heater control

Fan motor

ON

Heater

hold time

8 min.

or 0 min.

Rotation state

OFF

OFFON

30 sec.

Stop state

- 19 -

3.11 Sensor Supervision

The paper sensor signal (WRSENSE-N) and inlet sensor 1 signal (PSIN1-N) enter the CPU
through their dedicated own lines. When the state of the WRSENSE-N signal or PSIN1-N signal
is changed, the paper sensor state is read into the CPU at the interrupt timing (INT3). The state
of other sensors is read into the CPU through the power supply interface at the CPU sense timing.

COM- AOLC Power Supply Board

Paper End Sensor

CPU 31701

LSI

123
120

164

(PSIN1-N)

Power supply interface

WRSENSE-N

PSIN1-N

To option

Power
supply
control

LSI

Inlet Sensor 2

Toner Sensor

Outlet Sensor

Paper Sensor

Inlet Sensor 1

+5V

PC 504

PC 505

PC 506

PC 501

PC 502

PC 503

- 20 -

3.12 Cover Open

When the cover is opened, a cover open microswitch is opened. This makes a XCOVEROPEN­N signal low, then off the +5VD, thereby the CPU detects the open state. Furthermore, opening
the cover stops applying a +38V power to the high voltage power supply unit, resulting in stopping
all high voltage outputs.

COM-

CPU

+5V

125

+5VD

XCOVEROPEN-N

+5VD

0V

Power Supply Board

+38V

XCOVEROPEN-N

Cover Open
Microswitch

+38V

Cover close Cover open

Low Voltage

Supply Unit

Power

High

Voltage

Power
Supply

Unit

High

voltage

output

- 21 -

3.13 Power Supply Interface

The power supply interface is an 8-bit clock synchronous serial interface between the synchronous
serial I/O ports of LSI (31701) and the power control LSI in the power supply board under the control
of the CPU.

When the control section transmits a command on OSTTXDATA-N signal in synchronization with
the clock (OSTSCLK-N) to the power supply board, this power supply board transmits a response
on OSTRXDATA-N signal in synchronization with the same clock to the control section.

The commands include the control data of the high-voltage power supply, sense command, etc.
The responses include sensor information, fuser unit temperature information, etc.

COM- AOLC Power Supply Board

POWER CN9 CN8 CN3

CPU

Time chart

Control section

DIN

SCLK

DATA-OUT

SQCR

31071

LSI

OSTTXDATA-N

26

OSTSCLK-N

14

OSTRXDATA-N 34

87

OSTTXLD-N

86
15

OSTRXLD

Sequence clear

OSTLD-N

33

33

35

35
34
36

36

3 DATA OUT
2 SCLK

4 DIN
1 SQCR

Data write

LSB

b0 b1 b2 b3 b4 b5 b6 b7

b0 b1 b2 b3 b4 b5 b6 b7

Command

Power
supply
control

LSI

Sequence clear

MSB

LSI internal

Judge of read/write

Serial I/F section clear

command and read

- 22 -

port latch

Command decode

Set high voltage out

port in write command

Serial I/F section clear

3.14 Power Supply Board

The power supply circuit consists of the low-voltage power supply circuit and the high-voltage
power supply circuit. The low-voltage power supply circuit adopts a switching power supply system
and provides DC voltages required for the control of the equipment. The high-voltage power supply
circuit receives +38V power from the low-voltage power supply circuit and provides various high
voltages required for the electrophotographic process according to the control signals from the
control section.

(1) Low-voltage power supply circuit

SW

F1

Noise

filter

ACIN

circuit

Switching

circuit

Rectifying/

smoothing/

regulating

circuit

+8V
–8V

+5V

POW ON

+ 5V

+ 38V

+ 8V
– 8V

Switching

control

circuit

Overvoltage/

overcurrent

detector

circuit

Rectifying/

smoothing/

regulating

circuit

+38V

- 23 -

(2) High-voltage power supply circuit

This high-voltage power supply circuit receives the high-voltage generation timing control
command that is transmitted in serial through the power supply interface from the control
section. It decodes this command by LSI (IC501) and outputs high-frequency pulses to the
corresponding high-voltage generating circuits through pins 12, 13, 14, 15 and 16 of LSI
(IC501). It supplies +38V to each high-voltage generating circuit as the source voltage. When
the cover is open, the supply of +38V is interrupted to interrupt all the high-voltage outputs.
The relationship between the high-frequency pulse output pins and the high-voltage outputs
is shown in the following table.

Power Supply Board

+38V

CPU LSI

Power supply

interface

IC501

12

13

LSI

14
15

DB+

DB–

CB

TR

SB
DB

CB

TR

High-voltage

outputs

High

-frequency
pulse output pins

12

13

14

15

16

SB

+450V

–360V

16

DB TR CH

+300V

–240V

CB

+220V

+400V

CH

+4.415KV

–1.3KV

-1.3KV

Part with slant line: no output

CH

- 24 -

4. TROUBLESHOOTING

4.1 Troubleshooting Table

(A) Power/sensor board

Note:

The malfunction of the power supply is not repaired by an agency. The abnormality
to be treated here is taht of sensors only.

Failure LCD Message

A paper input jam occurs frequently.

A paper feed jam occurs frequently.

A paper-exit jam occurs frequently.

A paper size error occurs frequently.

The message "PAPER OUT" remains
displayed on the LCD.

The message "COVER OPEN" remains
displayed on the LCD.

PAPER INPUT JAM
CHECK ******

PAPER FEED JAM
CHECK ******

PAPER EXIT JAM
REMOVE THE PAPER

ERROR PAPER SIZE
CHECK ******

PAPER OUT
********* TRAY1

COVER OPEN

Flowchart

No.

A - 1

A - 2

A - 3

A - 4

A - 5

A - 6

The message "TONER LOW" remains
displayed on the LCD.

The message "TONER SENSOR" remains
displayed on the LCD.

A thermistor open error occurs frequently.

A thermistor short error occurs frequently.

TONER LOW

TONER SENSOR

ERROR CONTROLLER
72

ERROR CONTROLLER
73

- 25 -

A - 7

A - 8

A - 9

A - 10