OKI 10e Troubleshooting Manual

OKIP AGE 10e
LED Page Printer

T roubleshooting Manual
with Component Parts List

ODA/OEL/INT

1999. 9. 24 Rev.1

41266201TH Rev.1 1 / 135

CONTENTS

1. OUTLINE.........................................................................................................3

2. TOOLS............................................................................................................3

3. CIRCUIT DESCRIPTION................................................................................4

4. TROUBLESHOOTING..................................................................................36

5. CIRCUIT DIAGRAM......................................................................................56

6. COMPONENT PARTS LIST .........................................................................90

41266201TH Rev.1 2 /

1. OUTLINE

This manual has been written to provide guidance for troubleshooting of the OKIPAGE 10e Printer
(primarily for its printed circuit boards), based on the assumption that the reader has a thorough
knowledge concerning the printer. Read the maintenance manual for this printer, if necessary.

Notes:

1. The power supply board containing a high voltage power supply is dangerous. From the
viewpoint of the safety standards, the local repairing of a defective board is not allowed. Thus,
the objects to be locally repaired as a result of troubleshooting are switches and fuses.

2. Replacement of CPU (MHM2029) is not recommended. If CPU is found to be defective,
board replacement is suggested.

2. TOOLS

For troubleshooting the printer, the tools listed below may be needed in addition to general
maintenance tools.

Tool Remarks
Extension cord kit
Oscilloscope
Soldering iron

P/N: 40581901
Frequency response 100 MHz or higher
A slender tip type, 15-20 watts

41266201TH Rev.1 3 /

3. CIRCUIT DESCRIPTION

3.1 Outline

The main control board controls the reception of data transferred through a host I/F and processes
command analysis, bit image development, raster buffer read. It also controls the engine and the
operator panel. Its block diagram is shown in Fig. 3-1 .

(1) Reception control

The OKIPAGE 10e Printer can be equipped with one I/F port by adding an RS232C I/F option
board in addition to the Centronics I/F on the main control board.
Either of the two I/F ports which receives data first can be used automatically.
The other I/F port outputs a busy state signal.
The parallel I/F port can specify the following item when set by the control panel:

I-PRIME: Enabled/Disabled

The serial I/F port can specify the following item when set by the control panel:

Flow control : DTRHI/DTR LO/XONXOFF/RBSTXON
Baud rate : 300/600/1200/2400/4800/9600/19200 (Baud)
Data bit : 7/8 (bits)
Minimum busy time : 200/1000 (ms)
Parity : NONE/ODD/EVEN

An interface task stores all data received from the host into a receive buffer first.

(2) Command analysis processing

The OKIPAGE 10e Printer support PCL6 (Hewlett Packard LJ6P compatible).
An edit task fetches data from the receive buffer, analyzes commands, and reconstructs the
data in such a way that print data are aligned from up to down and from right to left; then it
writes the resultant data into a page buffer with such control data as print position coordinate,
font type, etc. added.

(3) Font Processing

When one page editing is finished, a developing task makes an engine start and fetches data
from the page buffer synchronizing with a printing operation, then it developes the fetched
data to a bit map as referring to data from a character generator, and writes the resultant data
into the raster buffer (of band buffer structure).

(4) Raster buffer read.

As controlling the engine operation, an engine task sends data from the raster buffer to the
LED head.

41266201TH Rev.1 4 /

1MB Memory Board

(Option)

RS232C Interface Board

or

(Option)

Main Control Board

Program & Font ROM

6MB Mask ROM

EEPROM

Centronics
parallel I/F

7407

+8V -8V 0V +5V+38V

Reset
circuit

For optional board

DATA

BUS

(32bit)

1 Chip CPU

Resident RAM

1M x 16 bit DRAM

(4MB)

Drum motor &

Registration motor

drive circuit

FAN Driver

HEAT ON

Multi-Purpose

Feeder (Option)

High Capacity
Second Paper

Feeder (Option)

Operation Panel

Drum Motor

MMRegistration Motor

FAN

FAN ALM

LED Head

Power Supply
Board

Inlet sensor 1

Inlet sensor 2

Paper sensor

Outlet sensor

Paper out sensor

Toner low sensor

Cover

open

switch

Low voltage

generation circuit

LSI

AC

transformer

Charge roller

Transfer roller

High voltage

generation

circuit

Fusing temperature

control circuit

Heater drive

circuit

Filter circuit AC IN

Developping

roller

Toner supply

roller

Cleaning

roller

Thermistor

Heater

Figure 3-1 Block Diagram

41266201TH Rev.1 5 /

A2 to A23

D0 to D31

CAS0 to
CAS3

ALS244ALS244ALS244

DRAM

1M Byte

SIMM1

DRAM SIMM

PD2, 3

BSY

SIMM2

Flash SIMM

ALS244

OPTION CONNECTOR

RAS2 to
RAS4
ORE, RD,
WR

CS3, EEPCS, EECLK
EEPDAT
IOS1

Figure 3-2 Memory Expansion Board Block Diagram (Option)

RAS2
ORE
WR

RAS3, 4
WR

RD
WR

41266201TH Rev.1 6 /

A2 to A23

D0 to D31

ALS244ALS244

PD2, 3

ALS244

BSY

CAS0 to
CAS3

OPTION CONNECTOR

RAS2 to
RAS4
ORE, RD,
WR

CS3, EEPCS, EEPCLK
EEPDAT
IOS1

TXD, RST, DTR

ALS244

SIMM1

Figure 3-3 RS-232C Serial Interface Board Block Diagram (Option)

DRAM SIMM

RAS3, 4
WR

RD
WR

SIMM2

Flash SIMM

RXD

RS-232C
CONNECTOR

75188

41266201TH Rev.1 7 /

3.2 CPU and Memory

(1) CPU (MHM2029-004K)

CPU core RISC CPU (MIPS R3000 compatible)
CPU clock 7.067 MHz
Internal CPU CLK 28.268 MHz

(2) Program and Font ROMs

ROM capacity 6M bytes (24M bit mask ROM two pieces)
ROM type 24M bits (1.5M x 16 bits)
Access time 100 ns

(3) Resident RAM

RAM capacity 4M bytes (16-Mbit D-RAM two pieces)
RAM type 16M bits (1M x 16 bits)
Access time 60 ns

(4) Option Board

RAM capacity (chip) 1M byte
RAM type (chip) 4M bits D-RAM two pieces Memory Expansion Board only
Access time (chip) 60 ns

SIMM 1 socket 2, 4, 8, 16 or 32M bytes, 72 pin DRAM SIMM, 60 to 100 ns
SIMM 2 socket Flash SIMM (72 pin)

}

The block diagram of CPU and memory circuit is shown in Fig. 3-4.
The timing chart of CPU and memory ciucuit is shown in Fig. 3-5.

41266201TH Rev.1 8 /

CPU

CS0
CS2
CS3

RAS0
RAS2

RAS3
RAS4
RAS5

Option board

A00 to A25

D00 to D32

CS0

RD

IC2, IC3

Mask ROM

(1.5M x 16 bits)

2 pieces

<Program>

CAS0
CAS1
CAS2
CAS3

RAS0

RD/WR

CAS0, 1, 2, 3

RAS2, 3, 4, 5CAS0, 1, 2, 3 RD/WR

RAS2 WR

CAS0,1,2,3

RAS3, 4 WR

CAS0,1,2,3

CS3, RD/WR

IC4, IC5

DRAM

(1M x 16 bits)

2 pieces

Main
control
board

Option
board

DRAM

1M Byte

(Memory Expansion Board only)

SIMM 1

DRAM SIMM

SIMM 2

Flash SIMM

Figure 3-4 Block Diagram of CPU & Memory Circuit

41266201TH Rev.1 9 /

DATA

T1

T2

VARIDVARID

39.13

29.32

T3

T2

(DRAS1~5-N)

(DRAS0-N)

27.3

12.25

T4

T2

14.6

T3

T2

17.91

CPU detects the type of SIMM memory installed on the memory

expansion board, and sets the suitable timing as shown in the left

handside table.

Due to this, T1~T4 values shown above vary depending on the type

of SIMM memory being used.

122.1 ns

142.4 ns

142.4 ns

142.4 ns

142.4 ns

40.7 ns

61.0 ns

61.0 ns

61.0 ns

61.0 ns

162.8 ns

183.1 ns

223.8 ns

223.8 ns

223.8 ns

T1 T2 T3 T4

61.0 ns

101.7 ns

101.7 ns

101.7 ns

101.7 ns

0 17.7 35.4 53.1 70.8 88.4 106.1 123.8 141.5 159.2 176.9 (ns)

(28.268 MHz)

SYSCLK

A00-A25-P

DRAS0~5-N

DCAS0~3-N

RD-N

TIME

SIMM speed

D00~D31-P

60 ns

No SIMM

70 ns

80 ns

100 ns

Figure 3-5 Timing Chart of CPU & Memory Circuit

41266201TH Rev.1 10 /

3.3 Reset Control

When power is turned on, a CLRST-N signal is generated by the rising sequence of +38V and
+8V power supply.

D2
(15V)

+38V

+38V +8V

Power ON

+38V

IC10-10

IC10-11

11
10

+8V

+
–

IC10

13

+5V

172

Power OFF

CPU

To Option Board

Q10 Input

CLRST-N

+5V

+8V

41266201TH Rev.1 11 /

3.4 EEPROM Control

CS

SK

DI

DO

HIGH-Z

12 4 1112 27

Min. 2µs

10 1

A7 A6 A1 A0 D15 D14 D1 D0

STATUS

BUSY READY

Max. 500 ns

Max. 10 ms

HIGH-Z

12

110

4

11 12

A7 A6 A1 A0

27 28

D15 D14 D1 D00 D15 D14

CS

SK

DI

DO

The 93LC66ARF E2 is an electrical erasable/programmable ROM of 256 x 16-bit configuration.
Data input to and output from the ROM are bidirectionally transferred in units of 16 bits through
a serial I/O port (SSTXD-P) in serial transmission synchronized with a clock signal from the CPU.
The EEPROM operates in the following instruction modes

3

DI DO

4

1

CS

CPU

SSTXD-P

154

EEPRMCS0-P

150

SK

EEPRMCLK-P

2

151

The EEPROM operates in the following instruction modes

Instruction Start bit Operation Address Data

code

Read (READ) 1 10 A7 to A0
Write Enabled (WEN) 1 00 11XXXXXX
Write (WRITE) 1 1 01 A7 to A0
Write All Address (WRAL) 1 00 01XXXXXX D15 to D0
Write Disabled (WDS) 1 00 00XXXXXX
Erase 1 11 A7 to A0
Chip Erasable (ERAL) 1 00 10XXXXXX

Write cycle timing (WRITE)

Read cycle timing (READ)

41266201TH Rev.1 12 /

3.5 Centronics Parallel Interface

The CPU sets a BUSY-P signal to ON at the same time when it reads the parallel data (PDATA1­P to PDATA 8-P) from the parallel port at the fall of PSTB-N signal. Furthermore, it makes the store
processing of received data into a receive buffer terminate within a certain fixed time and outputs
an ACK-N signal, setting the BUSY-P signal to OFF.

87, 88, 91 to 96

97

85

86

CPU

83

81

79

80

82

84

PDATA1-P to PDATA8-P

PSTB-N

IC11

PBUSY-P

PACK-N

PPE-P

PSEL-P

PERROR-N

PINIT-N

PSELIN-N

PAUTOFD-N

+5V

2 to 9

1

11

10

12

13

32

31

36

14

CENT

DATA8-P

to

DATA1-P
STB-N

BUSY-P

ACK-N
PE-P

SEL-P

FAULT-N

IPRIME-N
SELIN-N
AUTOFEED-N

PARALLEL DATA
(DATA BITs 1 to 8)

DATA STOROBE

BUSY

ACKNOWLEDGE

0.5 µs min.

0.5 µs min.

0.5 µs max.

5V

0 min.

0.5 µs to 10 µs

3.9k

+5V

18

Ω

0.5 µs min.

0.5 µs min.

0 min.

0 min.

0 min.

41266201TH Rev.1 13 /

3.6 Operator Panel

Operator panel have four LED lamps and a switch on the operator panel board.

5V

PANEL

CN1

CPU

124

147

113

114

52

5V

5V

4

3

5V

3

4

5V

2

5

5V

1

6

ALARM(Red)

PAPER(Amber)

READY(Green)

POWER(Green)

6

1

0V 0V

Flexible

Cable

41266201TH Rev.1 14 /

3.7 LED Head Control

When a paper form is made to arrive at the data write position on print start, the sending of data
to the LED head starts as synchronized with the page synchronous signal/line synchronous signal
(CPU internal signal).

Bit image data developed on the raster buffer of a memory are DMA-transferred to the register
of a video interface controller (CPU built-in) and then sent to the shift register of the LED head
in a serial transmission synchronized with the HDCLK-P signal.

When 1-dot line data (2496 bits) is completely shifted, it is latched by means of the HDLD-P signal,
causing LEDs to be driven by means of the STB1-N to STB4-N signals in 4-time division.

41266201TH Rev.1 15 /

R1R2

OUT

ADJ

TL317 PS

#1~#576 #577~#1152 #1153~#1824 1825~ #2496

IN

C2

C1

8

6

1

IC26

9 DATA

7 CLOCK

6 LOAD

2 STB4

LED ARRAY26

IC20

LED ARRAY20

IC13(~IC19)

LED ARRAY13(~19)

IC7(~IC12)

LED ARRAY7(~12)

IC1(~IC6)

<Internal Circuit of D-IC>

LED ARRAY1(~6)

3 STB3

4 STB2

5 STB1

10 VSS 1

13, 14 VSS 2

11, 12 VDD

00 96 50

00 1 51

CLOCK 1

CLK 2

LOAD 1

LOAD 2

STROBE

YREF

ADJ(3)
ADJ(2)
ADJ(1)

00 96 50

00 1 51

CLOCK 1

CLK 2

LOAD 1

LOAD 2

STROBE

YREF

ADJ(3)
ADJ(2)
ADJ(1)

YSS

YSS

SEL

SEL

YDD

YDD

00 96 50

00 1 51

CLOCK 1

CLK 2

LOAD 1

LOAD 2

STROBE

YREF

ADJ(3)
ADJ(2)
ADJ(1)

YSS

SEL

YDD

00 96 50

00 1 51

CLOCK 1

CLK 2

LOAD 1

LOAD 2

STROBE

YREF

ADJ(3)
ADJ(2)
ADJ(1)

YSS

SEL OPEN

YDD

00 96 50

00 1 51

CLOCK 1

CLK 2

LOAD

LOAD 2

STROBE

YREF

ADJ(3)
ADJ(2)
ADJ(1)

YSS

SEL OPEN

YDD

41266201TH Rev.1 16 /

Page
synchronous
signal*

Line
synchronous
signal*

HDDTO-P

HDCLK-P

HDDTO-P

HDCLK-P
HDDTO-P

HDLD-P
STRB1-N
STRB2-N

2.19 msec

2560 clock

0.6µs

STRB3-N

STRB4-N

* CPU internal signal

41266201TH Rev.1 17 /

3.8 Motor Control

(1) Registration and main (drum) motors

A registration motor and a drum motor are driven by means of control signals from the CPU
and a driver IC.

Main Control Board

CPU A2918SW

132

131

127

134

133

RMON-N

3

(2) Drum motor

DMPH1-P

DMPH2-P

DMON1-N

RMPH1-P

RMPH2-P

Current
control (IC10)

13

8

7

14

26

MTD2005F

17

20
23

IC9

IC8

+38V

+38V

DMPH1-N 1

1

DMPH1-P 2

17

DMPH2-N 3

2

DMPH2-P 4

4

RMPH1-P 1

3

RMPH1-N 2

7

RMPH2-P 3

8

RMPH2-N 4

12

DM

Main (Drum) Motor

M

RM

Registration Motor

M

DMON1-N

DMPH1-P

DMPH2-P

T0

T1 T2 T3

Operation at normal speed: T0 to T3 =1.016 ms

41266201TH Rev.1 18 /

(3) Registration motor

RMON-N

RMPH1-P

RMPH2-P

T0 T1 T2 T3

Rotation

(4) Drive control

Stop

Forward rotation
Hopping drive

Operation at normal speed: T0 to T3 = 1.016 ms

Reverse rotation
Registration roller drive

Time T0 to T3 determines the motor speed, while the difference of phase direction between
phase signals DMPH1-P and DMPH2-P (RMPH1-P and RMPH2-P) determines the rotation
direction. DMON1-N and RMON-N signals control a motor coil current. According to the
polarity of the phase signal, the coil current flow as follows:

1) +38V → SW → motor coil → SW → resistor → earth, or,

2) +38V → SW → motor coil → SW → resistor → earth
The voltage drop across the resistor is input to comparator, where it is compared with a

reference voltage. If an overcurrent flow occurs, a limiter operates to maintain it within a
certain fixed amount of current.

41266201TH Rev.1 19 /

3.9 Fuser Temperature Control

For the temperature control by heater control, the variation in the resistance of the thermistor is
A/D converted in IC2 and the resultant digital value is read and transferred to the CPU. The CPU
turns on or off the HEATON-N signal according to the value of the signal received from IC2 to keep
the temperature at a constant level.
Immediately after the power is turned on, the thermistor is checked for shortcircuit and
breakdown. If the thermistor is shorted, the A/D converted value shows an abnormally high
temperature, so that the shortcircuit can be detected. If the breakdown of the thermistor occurs,
the A/D converted value shows the normal temperature. In this case, the thermistor breakdown
can be detected by the sequence shown at the end of this section. If the heater is overheated,
5V supply is turned off when the resistance of the thermistor is detected to be exceeding the
predetermined value.

Main Control BoardPower Supply Board

Thermistor

Heater

TH1

TH2

CN2

1
2 PC1

5V

Thermistor
Breakdown

Detector

Circuit

IC2 CPU

Power

27

Abnormally

High

Temperature

Detection

Circuit

Supply

Interface

ACIN

20

HEATON-N
116

5V

IC11

1

0C

2

41266201TH Rev.1 20 /

The temperature control is described below.

Vt

Temperature

˚C

V2

V1

ON OFF ON OFF ONHEATON-N

V2 176˚C
V1 175˚C

* The values V1 and V2 vary according to setting mode.

(Standard temperature)

When Vt rises to V2 or more, the heater is turned off (by setting HEATON-N signal to LOW).
When Vt drops to V1 or less, the heater is turned on (by setting HEATON-N signal to HIGH). In
this way, the temperature can be kept within the predetermined range.

41266201TH Rev.1 21 /

For heater breakdown detection, the heater must first be turned on. When a temperature rise
which corresponds to the switching on of the heater does not occur, then a heater breakdown is
detected. To shorten the breakdown detection time, the following circuit is used. Immediately
after the power is turned on, the thermistor is checked and THERM-CMP signal is turned on to
turn the resistor Q44 on. The reading resolution is increased through the variation of the
thermistor resistance value.

If, for whatever reason, temperature control fails and the temperature rises abnormally, the
abnormal high temperature detection circuit shown below forcibly cuts the power supply to the
fuser.

5V

Thermistor

From CPU

Thermistor Breakdown Detection Circuit

R24

1.5k

Q6

THERM-CMP

Abnormal High Temperature Detection Circuit

+5V +5V

R26
1k

Ω

IC4

R28

1k

Ω

R25

Ω

100k

Ω

+

324

R27

1.8k

Ω

–

Q7

IC2
A/D

Converter

HEAT-N0

To PC1

41266201TH Rev.1 22 /

3.10 Fan Motor Control

The stop/rotation of the fan motor is controlled by FANON1-P and FANON2-N signals. When the
fan motor rotates normally, FANALM-P signal generated in the hole element built in the fan motor
is input to the CPU.

FANON1-P

109

5V

38V

CPU

FANON2-N

126

FANALM-N

110

R545

R549

0V

R4

IC10

TR503

8VR

339/2901

0V

5V

R540

38V

R554

3

0V

TR501

TR504

FAN

1

TR502

3

D1

1

D503

0V

1

2

3

Fan Motor

M

FANON1-P

H
H
L

FANON2-N

L

H

X

Fan motor rotation
Normal speed
Half speed
STOP

FANON1-P

FANALM-P

0.7 sec max

FAN MOVE

Lock

Fan motor start: Initial request, heater on, print start request
Fan motor stop: • The motor immediately stops when an engine error or a fan error occurs.

• The motor stops 0 second or 20 minutes after the occurrence of a paper jam, size
error, or fuse error.

• The motor stops in the power save mode as below.

Main (drum) motor

ON

OFF

Heater control

OFFON

Fan motor

Heater

hold time

8 min. or

30 sec.

0 sec.

Rotation state

Stop state

41266201TH Rev.1 23 /

3.11 Cover Open

When the cover is opened, a cover open microswitch is opened. This makes a CVOPN-N signal
low, thereby the CPU detects the open state. Furthermore, opening the cover stops applying a
+5V power to the high voltage power supply unit, resulting in stopping all high voltage outputs.

Main Control Board

CPU

+5V

CVOPN-N

0V

Power Supply Board

+5V

125

Cover close Cover open

CVOPN-N

Cover
Open
Microswitch

+5V

+5V

Low Voltage

Power

Supply Unit

High

Voltage

Power

Supply

Unit

High

voltage

output

41266201TH Rev.1 24 /

3.12 Power Supply Board

(1) Low voltage power supply

An AC power from an inlet is input to a transformer via fuses, AC switch and noise filter and
then lowered to a 32 VAC power and a 10 VAC power. The 32 VAC power is converted to
a +38 VDC output through a rectifying/smoothing circuit. A +5 VDC output is derived from the
resultant +38 VDC power through a regulation circuit. The 10 VAC power is converted to a
+8 VDC output and a -8 VDC output through a rectifying/smoothing circuit.

Power supply board

ACIN

FG
N

Filter

Circuit

Fuse Ratings

AC Input

Fuse

F1
F2
F3

120 V 230 V

125 V 6.3 A
125 V 1.6 A
125 V 3.15 A

250 V 5 A
–
250 V 2.5 A

(2) High voltage power supply

The +5 VDC power supplied to the high voltage power supply unit via the cover open
microswitch as source voltage. The high voltage power supply unit supplies necessary
voltage for electro-photography print to output terminals CH, DB, SB, TR, and CB according
to a control signal from the CPU. The table on the next page shows the relationship between
control signals and high voltage outputs.

CN1 CN2

Thermal Fuse1

2

AC Transformer

1, 2

3, 4

6

5

F3F2F1L

+5V

Smoothing

Stabilizing

±

8V

Rectifying/

Smoothing

Circuit

+38V

Circuit

+5V

Circuit

CN3

+38 V 17, 18

+5 V 11, 12, 13, 14
0 V 9, 15, 16

+8 V 24

-8 V 22

Cover Open Switch

CPU

SCLK
SQCR
DATA IN
DATA OUT

High Voltage

Power Supply

Unit

CH
DB
SB
TR
CB

TRSEL 3
TRSEL 4
TRSEL 5

41266201TH Rev.1 25 /

(3) Sensor control

Main Control Board

7

6

8

IC2

4

3

5

PSOUT-N

WRSNS-N

PAPER-N

PSIN1-N

TNRSNS-N

PSIN2-N

Power Supply Board

+5V

+5V

PS1

PS2

PS4

PS3

PS6

PS5

Sensor
signal

OFF

ON

TransparentShield

41266201TH Rev.1 26 /

(4) High-voltage power supply circuit

This high-voltage power supply circuit receives the high-voltage generation timing control
command that is transmitted in serial through the power supply interface from the control
section. It decodes this command by LSI (IC2) and outputs high-frequency pulses to the
corresponding high-voltage generating circuits through pins 11, 12, 13, 14 and 15 of LSI
(IC2). It supplies +5V to each high-voltage generating circuit as the source voltage. When
the cover is open, the supply of +5V is interrupted to interrupt all the high-voltage outputs.
The relationship between the high-frequency pulse output pins and the high-voltage outputs
is shown in the following table.

Power Supply CircuitMain Control Board

CPU

Power supply interface

IC2

LSI

13

15
11

14

+5V

DB

CB

TR

SB

SB
DB

CB

TR

High-voltage

outputs

High

-frequency
pulse output pins

11

12

13

14

15

SB

0V

DB

+300V

-500V -265V

CB

+400V

-1.35kV

TR

+1.2kV

-1.1kV

12

CH

-1.3kV

CH

CH

Remarks

TRSEL 3: Hi-Z
TRSEL 5: L

TRSEL 3: L
TRSEL 5: Hi-Z

Part with slant line: no output

41266201TH Rev.1 27 /

3.13 Option Tray Control

The kinds of option trays, High capacity Second Paper Feeder and Multi purpose Feeder can be
connected to the printer. The trays are distinguished by two digit ID numbers.

The option trays and the printer communicate with each other through bi-directional clock
synchoronized serial interface. The printer always sends a command first, then each option tray
interpret it. Because the command contains an ID, the selectes option tray takes approriate
actions, then sends back a reply. The command and reply are transmitted back and forth on
OPTSD-P signal line by synchronizing OPTSCLK-N clock signal which is sent by the printer. The
printer knows the timing when it outputs the clock for the reply by sensing OPTSDR-N signal which
is turned to zero by the option tray when it is ready for the reply.

The option tray’s paper feeding action is triggered by a command sent by the printer. When the
tray delects a signal on OPTPSIN-N signal line, which indicates the paper reaches a input sensor
in the printer, the tray stops the paper feeding after carrying out the paper feeding according to
the predetermined steps which have been downloaded from the printer at power-up time.

Status of the option trays such as no paper cassette, paper out and cover open, are informed to
the printer though a reply in response to a status inquiry command.

41266201TH Rev.1 28 /

Main Control board

CPU

3
2
4
1

OPTSD-P

OPTSCLK-N

OPTSDR-N

OPTSIN-N

TQSB-2
(Option)

PU2ND TRAY

3
2
4
1

High capacity Second

Paper Feeder

5V

IC1

3

4

0C

6

5

3
5

8

0C

9

9

10

28

1

0C

2

IC2

65-43

F0

G0

F2

F1
G2
E0 C2

C1
C0

D0

E1

7
4

22
21

20

24
29

5V

TR2

1

30V

3

A
B

C
D

270

560

2

Ω

Ω

0V

IC3

MS4646

2

VR1

27

VR2

14

A

PH1

15

B

PH2

5V

6

MA1
MA2

MB1
MB2

D1
D2

CN2

4

25
10
19

5V

M

ENVELOPE

OPTSD-P

3

OPTSCLK-N

2

OPTSDR-N

4

OPTPSIN-N

1

OLEV-(Option)

CN2

3
2
4
1

SEN1

3

SEN2

1

3

1

(Paper)

5V

42

IC1

12

0C

11

0C

9

13

8

C

0V

D

(Cover Open)

2

4

0V

10

IC2

65-43

3

F0

G0

5

F2

0C

1

9

2

28

G2
E0 C2

3

F1

C1

C0

D0

A0

7
4

3

22

A

21

B

20

C

24

1, 2 3, 4

11

SW1

TR1

5V

1

30V

CN2

D1
D2

2

IC3

MS4646

MA1

0V

2

VR1

27

14

A

15

B

VR2
PH1

PH2

MA2
MB1

MB2

25
10
19

4

M

0V

5V

SEN2

3

1

(Paper)

42

Multi purpose Feeder

C

0V

Option Tray Connection and Block Diagram

41266201TH Rev.1 29 /

OPTSD-P

Min. 3000

µ

S

Option Tray Control Serial Interface Time Chart

b7 b6 b5 b4 b3 b2 b1 b0

b7 b6 b5 b4 b3 b2 b1 b0

b7 b6 b5 b4 b3 b2 b1 b0

1.5

µ

S40

µ

S21

µ

S

Min. 1300

µ

S

Max. 3000

µ

S

OPTSCLK-N

OPTSDR-N

Next Command (CPU

→

Tray)Reply (Tray

→

CPU)Command (CPU

→

Tray)

Option Tray Serial Interface Time Chart

41266201TH Rev.1 30 /