NXP Semiconductors LPC1102 User Manual

UM10429

LPC1102 User manual

Rev. 1 — 20 October 2010 User manual

Document information

Info Content Keywords ARM Cortex-M0, LPC1102, LPC1102UK Abstract LPC1102 User manual

NXP Semiconductors

UM10429

LPC1102 UM

Revision history

Rev Date Description

1 20101020 LPC1102 User manual

Contact information

For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com

User manual Rev. 1 — 20 October 2010 2 of 258

1.1 Introduction

1.2 Features

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Chapter 1: LPC1102 Introductory information

Rev. 1 — 20 October 2010 User manual

The LPC1102 is an ARM Cortex-M0 based, low-cost 32-bit MCU, designed for 8/16-bit microcontroller applications, offering performance, low power, simple instruction set and memory addressing together with reduced code size compared to existing 8/16-bit architectures.

The LPC1102 operates at CPU frequencies of up to 50 MHz. The peripheral complement of the LPC1102 includes 32 kB of flash memory, 8 kB of data

memory, one RS-485/EIA-485 UART, one SPI interface with SSP features, four general purpose counter/timers, a 10-bit ADC, and 11 general purpose I/O pins.

• System:

– ARM Cortex-M0 processor, running at frequencies of up to 50 MHz. – ARM Cortex -M 0 bu ilt- in Ne ste d Vectored Interrupt Controller (NVIC). – Serial Wire Debug. – System tick timer.

• Memory:

– 32 kB on-chip flash programming memory. – 8 kB SRAM. – In-Application Programming (IAP) and In-System Programming (ISP) support via

on-chip bootloader software.

• Digital peripherals:

– 11 General Purpose I/O (GPIO) pins with configurable pull-up/pull-down resistors. – GPIO pins can be used as edge and level sensitive interrupt sources. – Four general purpose counter/timers with a total of one capture input and nine

match outputs.

– Programmable WatchDog Timer (WDT).

• Analog peripherals:

– 10-bit ADC with input multiplexing among five pins.

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• Serial interfaces:

• Clock generation:

• Power control:

• Unique device serial number for identification.

• Single 3.3 V power supply (1.8 V to 3.6 V).

• Available as WLCSP16 package.

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Chapter 1: LPC11 02 Introductory information

– UART with fractional baud rate generation, internal FIFO, and RS-485 support. – One SPI controller with SSP features and with FIFO and multi-protocol capabilities.

– 12 MHz internal RC oscillator trimmed to 1% accuracy that can optionally be used

as a system clock.

– Programmable watchdog oscillator with a frequency range of 7.8 kHz to 1.8 MHz. – PLL allows CPU operation up to the maximum CPU rate without the need for a

high-frequency crystal. May be run from an external clock or the internal RC oscillator.

– Clock output function with divider that can reflect the external clock, IRC clo ck,

CPU clock, and the Watchdog clock.

– Integrated PMU (Power Management Unit) to minimize power consumption dur ing

Sleep and Deep-sleep modes.

– Power profiles residing in boot ROM allowing to optimize performance and

minimize power consumption for any give n application th rough one simple fu nction call.

– Two reduced power modes: Sleep and Deep-sleep modes. – Processor wake-up from Deep-sleep mode via a dedicated start logic using up to

six of the functional pins.

– Power-On Reset (POR). – Brownout detect with four separate thresholds for interrupt and forced reset.

1.3 Ordering information

Table 1. Ordering information

Type number Package

LPC1102UK WLCSP16 wafer level chip-size package; 16 bumps; 2.17 × 2.32 × 0.6 mm -

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Name Description Version

Table 2. Ordering options

Type number Flash Total

SRAM

LPC1102UK 32 kB 8 kB 1 - 1 5 WLCSP16

UART I2C/

Fm+

SPI ADC

channels

Package

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SRAM

8 kB

ARM

CORTEX-M0

TEST/DEBUG

INTERFACE

FLASH

32 kB

HIGH-SPEED

GPIO

AHB TO APB

BRIDGE

CLOCK

GENERATION,

POWER CONTROL,

SYSTEM

FUNCTIONS

XTALIN

RESET

clocks and

controls

SWD

LPC1102

002aaf524

slave

slave slave

ROM

slave

AHB-LITE BUS

GPIO port

PIO0/1

IRC

POR

SPI

10-bit ADC

UART

32-bit COUNTER/TIMER 0

WDT

IOCONFIG

CT32B0_MAT[3,1,0]

AD[4:0]

RXD

TXD

SYSTEM CONTROL

PMU

32-bit COUNTER/TIMER 1

CT32B1_MAT[2:0]

CT32B1_CAP0

16-bit COUNTER/TIMER 1

16-bit COUNTER/TIMER 0

CT16B0_MAT[2:0]

SCK, MISO, MOSI

system bus

1.4 Block diagram

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Chapter 1: LPC11 02 Introductory information

Fig 1. LPC1102 Block diagram

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1.5 ARM Cortex-M0 processor

The ARM Cortex-M0 processor is described in detail in Section 19.2 “About the

Cortex-M0 processor and core peripherals”. For the LPC1102, the ARM Cortex-M0

processor core is configured as follows:

• System options:

– The Nested Vectored Interrupt Controller (NVIC) is includ ed and su pport s up to 32

interrupts.

– The system tick timer is included.

• Debug options: Serial Wire Debug is included with two watchpoints and four

breakpoints.

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Chapter 1: LPC11 02 Introductory information

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Chapter 2: LPC1102 Memory mapping

Rev. 1 — 20 October 2010 User manual

2.1 How to read this chapter

Table 3 shows the memory configuration for the LPC1102 part.

Table 3. LPC1102 memory configuration

Part Flash SRAM Suffix

LPC1102 32 kB 8 kB

2.2 Memory map

Figure 2 shows the memory and peripheral address space of the LPC1102.

The AHB peripheral area is 2 MB in size and is divided to allow for up to 128 peripherals. On the LPC1102, the GPIO ports are the only AHB peripherals. The APB peripheral area is 512 kB in size and is divided to allow for up to 32 peripherals. Each peripheral of either type is allocated 16 kB of space. This allows simplifying the address decoding for each peripheral.

All peripheral register addresses are 32-bit word aligned regardless of their size. An implication of this is that word and half-word registers must be accessed all at once. For example, it is not possible to read or write the upper byte of a word register separately.

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0x5000 0000

0x5001 0000

0x5002 0000

0x5020 0000

AHB peripherals

127 - 16 reserved

GPIO PIO1

7-4

0x5003 0000

0x5004 0000

reserved

11-8

15-12

GPIO PIO0

3-0

APB peripherals

0x4000 4000

0x4000 8000

0x4000 C000

0x4001 0000

0x4001 8000

0x4002 0000

0x4002 8000

0x4003 8000

0x4003 C000

0x4004 0000

0x4004 4000

0x4004 8000

0x4004 C000

0x4005 8000

0x4005 C000

0x4008 0000

0x4002 4000

0x4001 C000

0x4001 4000

0x4000 0000

WDT

32-bit counter/timer 0

32-bit counter/timer 1

ADC

UART

PMU

reserved

13 - 10 reserved

reserved reserved

21 - 19 reserved

31 - 23 reserved

16 15

reserved

0x0000 0000

0 GB

0.5 GB

4 GB

1 GB

0x1000 2000

0x1FFF 0000

0x1FFF 4000

0x2000 0000

0x4000 0000

0x4008 0000

0x5000 0000

0x5020 0000

0xFFFF FFFF

reserved

APB peripherals

AHB peripherals

8 kB SRAM

0x1000 0000

LPC1102

0x0000 8000

32 kB on-chip flash

16 kB boot ROM

0x0000 0000

0x0000 00C0

active interrupt vectors

002aaf526

reserved

SPI

16-bit counter/timer 1 16-bit counter/timer 0

IOCONFIG

system control

reserved

flash controller

0xE000 0000

0xE010 0000

private peripheral bus

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Chapter 2: LPC1102 Memory mapping

Fig 2. LPC1102 memory map

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Chapter 3: LPC1102 System configuration

Rev. 1 — 20 October 2010 User manual

3.1 How to read this chapter

This chapter applies to part LPC1102.

3.2 Introduction

The system configuration block controls oscillators, start logic, and clock generation of the LPC1102. Also included in this block are registers for setting the priority for AHB access and a register for remapping flash, SRAM, and ROM memory areas.

3.3 Pin description

Table 4 shows pins that are associated with system con tr o l bloc k func tio ns .

Table 4. Pin summary

Pin name Pin direction Pin description

PIO0_0; PIO0_8 to PIO0_11 I Start logic wake-up pins port 0 PIO1_0 I Start logic wake-up pin port 1

3.4 Clocking and power control

See Figure 3 for an overview of the LPC1102 Clock Generation Unit (CGU). The LPC1102 include three independent oscillators. These are the system oscillator, the

Internal RC oscillator (IRC), and the watchdog oscillator. Each oscillator can be used for more than one purpose as required in a particular application.

Following reset, the LPC1102 will operate from the Internal RC oscillator until switched by software. This allows systems to operate without any external crystal and the bootloader code to operate at a known frequency.

The SYSAHBCLKCTRL register gates the system clock to the various peripherals and memories. UART, the WDT, and SPI0 have individual clock dividers to derive peripheral clocks from the main clock.

For details on power control see Section 3.8

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SYSTEM PLL

IRC oscillator

system oscillator

watchdog oscillator

IRC oscillator

watchdog oscillator

MAINCLKSEL

(main clock select)

SYSPLLCLKSEL

(system PLL clock select)

SYSTEM CLOCK

DIVIDER

AHB clock 0 (system)

AHBCLKCTRL[1:18]

SPI0 PERIPHERAL

CLOCK DIVIDER

SPI0_PCLK

UART PERIPHERAL

CLOCK DIVIDER

UART_PCLK

WDT CLOCK

DIVIDER

WDT_PCLK

WDTUEN

(WDT clock update enable)

main clock

system clock

IRC oscillator

AHB clocks 1 to 18 (memories and peripherals)

sys_pllclkout

sys_pllclkin

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Chapter 3: LPC1102 System configuration

3.5 Register description

Table 5. Register overview: system control block (base address 0x4004 8000)

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Fig 3. LPC1102 CGU block diagram

All registers, regardless of size, are on word address boundaries. Details of the registers appear in the description of each function.

See Section 3.11

for the flash access timing register, which can be re-configured as part

the system setup. This register is not part of the system configuration block.

Name Access Address offset Description Reset

Reference

value

SYSMEMREMAP R/W 0x000 System memory remap 0x002 Table 6 PRESETCTRL R/W 0x004 Peripheral reset control 0x000 Table 7 SYSPLLCTRL R/W 0x008 System PLL control 0x000 Table 8 SYSPLLSTAT R 0x00C System PLL status 0x000 Table 9

- - 0x010 - 0x01C Reserved - - SYSOSCCTRL R/W 0x020 System oscillator control 0x000 Table 10 WDTOSCCTRL R/W 0x024 Watchdog oscillator control 0x000 Table 11 IRCCTRL R/W 0x028 IRC control 0x080 Table 12

- - 0x02C Reserved - -

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Chapter 3: LPC1102 System configuration

Table 5. Register overview: system control block (base address 0x4004 8000) …continued

Name Access Address offset Description Reset

value

SYSRSTST AT R 0x030 System reset status register 0x000 Table 13

- - 0x034 - 0x03C Reserved - - SYSPLLCLKSEL R/W 0x040 System PLL clock source select 0x000 Table 14 SYSPLLCLKUEN R/W 0x044 System PLL clock source update enable 0x000 Table 15

- - 0x048 - 0x06C Reserved - - MAINCLKSEL R/W 0x070 Main clock source select 0x000 Table 16 MAINCLKUEN R/W 0x074 Main clock source update enable 0x000 Table 17 SYSAHBCLKDIV R/W 0x078 System AHB clock divider 0x001 Table 18

- - 0x07C Reserved - - SYSAHBCLKCTRL R/W 0x080 System AHB clock control 0x85F Table 19

- - 0x084 - 0x090 Reserved - - SSP0CLKDIV R/W 0x094 SPI0 clock divder 0x000 Table 20 UARTCLKDIV R/W 0x098 UART clock divder 0x000 Table 21

- - 0x09C Reserved - -

- - 0x0A0-0x0CC Reserved - - WDTCLKSEL R/W 0x0D0 WDT clock source select 0x000 Table 22 WDTCLKUEN R/W 0x0D4 WDT clock source update enable 0x000 Table 23 WDTCLKDIV R/W 0x0D8 WDT clock divider 0x000 Table 24

- - 0x0DC Reserved - -

- - 0x0E0 Reserved - -

- - 0x0E4 Reserved - -

- - 0x0E8 Reserved - -

- - 0x0EC - 0x0FC Reserved PIOPORCAP0 R 0x100 POR captured PIO status 0 user

dependent

- - 0x104 Reserved - -

- R 0x108 - 0x14C Reserved - - BODCTRL R/W 0x150 BOD control 0x000 Table 26 SYSTCKCAL R/W 0x154 System tick counter calibration 0x004 Table 27

- - 0x158 - 0x1FC Reserved - - STARTAPRP0 R/W 0x200 Start logic edge control register 0 Table 28 STARTERP0 R/W 0x204 Start logic signal enable register 0 Table 29 STARTRSRP0CLR W 0x208 Start logic reset register 0 n/a Table 30 STARTSRP0 R 0x20C Start logic status register 0 n/a Table 31

- - 0x210 - 0x22C Reserved - - PDSLEEPCFG R/W 0x230 Power-down states in Deep-sleep mode 0x0000

0000

PDAWAKECFG R/W 0x234 Power-down states after wake-up from

Deep-sleep mode

0x0000 EDF0

Reference

Table 25

Table 33

Table 34

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Chapter 3: LPC1102 System configuration

Table 5. Register overview: system control block (base address 0x4004 8000) …continued

Name Access Address offset Description Reset

value

PDRUNCFG R/W 0x238 Power-down configuration register 0x0000

EDF0

- - 0x23C - 0x3F0 Reserved - - DEVICE_ID R 0x3F4 Device ID part

dependent

3.5.1 System memory remap register

The system memory remap register selects whether the ARM interrupt vectors are read from the boot ROM, the flash, or the SRAM.

Table 6. System memory remap register (SYSMEMREMAP, address 0x4004 8000) bit

description

Bit Symbol Value Description Reset

1:0 MAP System memory remap 10

0x0 Boot Loader Mode. Interrupt vectors are re-mapped to Boot

ROM.

0x1 User RAM Mode. Interrupt vectors are re-mapped to Static

RAM.

0x2 User Flash Mode. Interrupt vectors are not re-mapped and

reside in Flash.

0x3 User Flash Mode. Interrupt vectors are not re-mapped and

reside in Flash.

31:2 - - Reserved 0x00

Reference

Table 35

Table 36

value

3.5.2 Peripheral reset control register

This register allows software to reset the SPI peripheral. Writing a 0 to the SSP0_RST_N bit resets the SPI0 peripheral. Writing a 1 de-asserts the reset.

Remark: Before accessing the SPI peripheral, write a 1 to this register to ensure that the reset signal to the SPI is de-asserted.

Table 7. Peripher al reset control register (PRESETCTRL, address 0x4004 8004) bit

description

Bit Symbol Value Description Reset

value

0 SSP0_RST_N SPI0 reset control 0

0 Resets the SPI0 periphe ral. 1 SPI0 reset de-asserted.

31:1 - - Reserved 0x00

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3.5.3 System PLL control register

This register connects and enables the system PLL a nd configur es the PLL multiplie r and divider values. The PLL accepts an input frequency from 10 MHz to 25 MHz from various clock sources. The input frequency is multiplied up to a high frequency, then divided down to provide the actual clock used by the CPU, peripherals, and memories. The PLL can produce a clock up to the maximum allowed for the CPU.

Table 8. Syste m PLL control register (SYSPLLCTRL, address 0x4004 8008) bit description

Bit Symbol Value Description Reset

4:0 MSEL Feedback divider value. The division value M is the

6:5 PSEL Post divider ratio P. The division ratio is 2 × P. 0x00

31:7 - - Reserved. Do not write ones to reserved bits. 0x0

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Chapter 3: LPC1102 System configuration

value

0x000 programmed MSEL value + 1. 00000: Division ratio M = 1 to 11111: Division ration M = 32

0x0 P = 1 0x1 P = 2 0x2 P = 4 0x3 P = 8

3.5.4 System PLL status register

This register is a Read-only register and supplies the PLL lock status (see

Section 3.10.1

Table 9. Syste m PLL status register (SYSPLLSTAT, address 0x4004 800C) bit description

Bit Symbol Value Description Reset

0 LOCK PLL lock status 0x0

31:1 - - Reserved 0x00

0 PLL not locked 1 PLL locked

3.5.5 System oscillator control register

This register configures the frequency range for the system oscillator.

Table 10. System oscillator control register (SYSOSCCTRL, address 0x4004 8020) bit

description

Bit Symbol Value Description Reset

0 BYPASS Bypass system oscillator 0x0

0 Oscillator is not bypassed. 1 Bypass enabled. PLL input (sys_osc_clk) is fed

directly from the XTALIN pin.

value

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Table 10. System oscillator control register (SYSOSCCTRL, address 0x4004 8020) bit

Bit Symbol Value Description Reset

1 FREQRANGE Determines frequency range for Low-power

31:2 - - Reserved 0x00

3.5.6 Watchdog oscillator control register

This register configures the watchdog oscillator. The oscillator consists of an analog and a digital part. The analog part contains the oscillator function and generates an analog clock (Fclkana). With the digital part, the analog output clock (Fclkana) can be divided to the required output clock frequency wdt_osc_clk. The analog output frequency (Fclkan a) can be adjusted with the FREQSEL bits between 500 kHz and 3.4 MHz. With the digital part Fclkana will be divided (divider ratios = 2, 4,...,64) to wdt_osc_clk using the DIVSEL bits.

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Chapter 3: LPC1102 System configuration

description

value

0x0

oscillator. 0 1 - 20 MHz frequen cy range. 1 15 - 25 MHz freque ncy range

The output clock frequency of the watchdog oscillator can be calculated as wdt_osc_clk =

⁄

(2 × (1 + DIVSEL))

= 7.8 kHz to 1.7 MHz (nominal values).

Fclkana

Remark: Any setting of the FREQSEL bits will yield a Fclkana value within ±40% of the listed frequency value. The watchdog oscillator is the clock source with the lowest power consumption. If accurate timing is required, use the IRC or system oscillator.

Remark: The frequency of the watchdog oscillator is undefined after reset. The watchdog oscillator frequency must be programmed by writing to the WDTOSCCTRL register before using the watchdog oscillator.

Table 11. Watchdog oscillator control register (WDTOSCCTRL, address 0x4004 8024) bit

description

Bit Symbol Value Description Reset

value

4:0 DIVSEL Select divider for Fclkana.

wdt_osc_clk = Fclkana/ (2 × (1 + DIVSEL)) 00000: 2 × (1 + DIVSEL) = 2 00001: 2 × (1 + DIVSEL) = 4 to 11111: 2 × (1 + DIVSEL) = 64

0x00

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Table 11. Watchdog oscillator control register (WDTOSCCTRL, address 0x4004 8024) bit

Bit Symbol Value Description Reset

8:5 FREQSEL Select watchdog oscillator analog output frequency

31:9 - - Reserved 0x00

description

0x1 0.5 MHz 0x2 0.8 MHz 0x3 1.1 MHz 0x4 1.4 MHz 0x5 1.6 MHz 0x6 1.8 MHz 0x7 2.0 MHz 0x8 2.2 MHz 0x9 2.4 MHz 0xA 2.6 MHz 0xB 2.7 MHz 0xC 2.9 MHz 0xD 3.1 MHz 0xE 3.2 MHz 0xF 3.4 MHz

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Chapter 3: LPC1102 System configuration

…continued

value

0x00

(Fclkana).

3.5.7 Internal resonant crystal control register

This register is used to trim the on-chip 12 MHz oscillator. The trim value is factory-preset and written by the boot code on start-up.

Table 12. Internal resonant crystal control register (IRCCTRL, address 0x4004 8028) bit

description

Bit Symbol Value Description Reset value

7:0 TRIM Trim value 0x1000 0000,

31:9 - - Reserved 0x00

then flash will reprogram

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3.5.8 System reset status register

if another reset signal - for example EXTRST - remains asserted after the POR signal is negated, then its bit is set to detected.

Table 13. System reset status register (SYSRSTSTAT, address 0x4004 8030) bit description

Bit Symbol Value Description Reset

0 POR POR reset status 0x0

1 EXTRST 0x0

2 WDT Status of the Watchdog reset 0x0

3 BOD Status of the Brown-out detect reset 0x0

4 SYSRST Status of the software system reset 0x0

31:5 - - Reserved 0x00

Chapter 3: LPC1102 System configuration

0 no POR detected 1 POR detected

0 no RESET 1 RESET

0 no WDT reset de tected 1 WDT reset detected

0 no BOD reset detected 1 BOD reset detected

0 no System reset detected 1 System reset detected

event detected

detected

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value

3.5.9 System PLL clock source select register

This register selects the clock source for the system PLL. The SYSPLLCLKUEN register (see Section 3.5.10

Remark: When switching clock sources, both clocks must be running before the clock source is updated.

Remark: When using the C_CAN controller with baudrates above 100 kbit/s, the system oscillator must be selected.

T able 14. System PLL clock source select register (SYSPLLCLKSEL, address 0x4004 8040)

bit description

Bit Symbol Value Description Reset

1:0 SEL System PLL clock source 0x00

31:2 - - Reserved 0x00

) must be toggled from LOW to HIGH for the update to take effect.

0x0 IRC oscillator 0x1 System oscillator 0x2 Reserved 0x3 Reserved

value

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3.5.10 System PLL clock source update enable register

This register updates the clock source of the system PLL with the new input clock after the SYSPLLCLKSEL register has been written to. In order for the update to take effect, first write a zero to the SYSPLLUEN register and then write a one to SYSPLLUEN.

Remark: When switching clock sources, both clocks must be running before the clock source is updated.

Table 15. System PLL clock source update enable register (SYSPLLUEN, address 0x4004

Bit Symbol Value Description Reset value

0 ENA Enable system PLL clock source update 0x0

31:1 - - Reserved 0x00

3.5.11 Main clock source select register

This register selects the main system clock which can be either any input to the system PLL, the output from the system PLL (sys_pllclkout), or the watchdog or IRC oscillators directly. The main system clock clocks the core, the peripherals, and the memories.

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Chapter 3: LPC1102 System configuration

8044) bit description

0 No change 1 Update clock source

The MAINCLKUEN register (see Section 3.5.12

) must be toggled from LOW to HIGH for

the update to take effect. Remark: When switching clock sources, both clocks must be running before the clock

source is updated. Remark: When using the C_CAN controller with baudrates above 100 kbit/s, the system

oscillator must be selected.

Table 16. Main clock source select register (MAINCLKSEL, address 0x4004 8070) bit

description

Bit Symbol Value Description Reset value

1:0 SEL Clock source for main clock 0x00

0x0 IRC oscillator 0x1 Input clock to system PLL 0x2 WDT oscillator 0x3 System PLL clock out

31:2 - - Reserved 0x00

3.5.12 Main clock source update enable register

This register updates the clock source of the main clock with the new input clock after the MAINCLKSEL register has been written to. In order for the update to take effect, first write a zero to the MAINCLKUEN register and then write a one to MAINCLKUEN.

Remark: When switching clock sources, both clocks must be running before the clock source is updated.

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Table 17. Main clock source update enable register (MAINCLKUEN, address 0x4004 8074)

Bit Symbol Value Description Reset value

0 ENA Enable main clock source update 0x0

31:1 - - Reserved 0x00

3.5.13 System AHB clock divider register

This register divides the main clock to provide the system clock to the core, memories, and the peripherals. The system clock can be shut down completely by setting the DIV bits to 0x0.

Table 18. System AHB clock divider register (SYSAHBCLKDIV, address 0x4004 8078) bit

Bit Symbol Description Reset

7:0 DIV System AHB clock divider values

31:8 - Reserved 0x00

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Chapter 3: LPC1102 System configuration

bit description

0 No change 1 Update clock source

description

value

0x01 0: System clock disabled. 1: Divide by 1. to 255: Divide by 255.

3.5.14 System AHB clock control register

The AHBCLKCTRL register enables the clocks to individual system and peripheral blocks. The system clock (sys_ahb_clk[0], bit 0 in the AHBCLKCTRL register) provides the clock for the AHB to APB bridge, the AHB matrix, the ARM Cortex- M 0, the Syscon block, and the PMU. This clock cannot be disabled.

Table 19. System AHB clock control register (SYSAHBCLKCTRL , ad dress 0x4004 8080) bit

description

Bit Symbol Value Description Reset

0 SYS Enables clock for AHB to APB bridge, to the AHB

matrix, to the Cortex-M0 FCLK and HCLK, to the

SysCon, and to the PMU. This bit is read only. 0 Reserved 1 Enable

1 ROM Enables clock for ROM. 1

0 Disable 1 Enable

2 RAM Enables clock for RAM. 1

0 Disable 1 Enable

value

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Table 19. System AHB clock control register (SYSAHBCLKCTRL , ad dress 0x4004 8080) bit

Bit Symbol Value Description Reset

3 FLASHREG Enables clock for flash register interface. 1

4 FLASHARRAY Enables clock for flash array access. 1

5- Reserved. 0 6 GPIO Enables clock for GPIO. 1

7 CT16B0 Enables clock for 16-bit counter/timer 0. 0

8 CT16B1 Enables clock for 16-bit counter/timer 1. 0

9 CT32B0 Enables clock for 32-bit counter/timer 0. 0

10 CT32B1 Enables clock for 32-bit counter/timer 1. 0

11 SSP0 Enables clock for SPI0. 1

12 UART Enables clock for UART. Note that the UART pins

13 ADC Enables clock for ADC. 0

14 - Reserved 0 15 WDT Enables clock for WDT. 0

description

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Chapter 3: LPC1102 System configuration

…continued

value

0 Disabled 1 Enabled

0 Disable 1 Enable

0 must be configured in the IOCON block before the UART clock can be enabled.

0 Disable 1 Enable

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Table 19. System AHB clock control register (SYSAHBCLKCTRL , ad dress 0x4004 8080) bit

Bit Symbol Value Description Reset

16 IOCON Enables clock for I/O configuration block. 0

31:17 - - Reserved 0x00

3.5.15 SPI0 clock divider register

This register configures the SPI0 peripheral clock SPI0_PCLK. The SPI0_PCLK can be shut down by setting the DIV bits to 0x0.

Table 20. SPI0 clock divider register (SSP0CLKDIV, address 0x4004 8094) bit description

Bit Symbol Description Reset

7:0 DIV SPI0_PCLK clock divider values

31:8 - Reserved 0x00

description

0: Disable SPI0_PCLK. 1: Divide by 1. to 255: Divide by 255.

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Chapter 3: LPC1102 System configuration

…continued

value

0 Disable 1 Enable

value

0x00

3.5.16 UART clock divider register

This register configures the UART peripheral clock UART_PCLK. The UART_PCLK can be shut down by setting the DIV bits to 0x0.

Remark: Note that the UART pins must be configured in the IOCON block before the UART clock can be enabled.

Table 21. UART clock divider register (UARTCLKDIV, address 0x4004 8098) bit description

Bit Symbol Description Reset

7:0 DIV U ART_PCLK clock divider values

0: Disable UART_PCLK. 1: Divide by 1. to 255: Divide by 255.

31:8 - Reserved 0x00

3.5.17 WDT clock source select register

This register selects the clock source for the watchdog timer. The WDTCLKUEN register (see Section 3.5.18

Remark: When switching clock sources, both clocks must be running before the clock source is updated.

) must be toggled from LOW to HIGH for the update to take effect.

value

0x00

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Table 22. WDT clock source select register (WDTCLKSEL, address 0x4004 80D0) bit

Bit Symbol Value Description Reset

1:0 SEL WDT clock source 0x00

31:2 - - Reserved 0x00

3.5.18 WDT clock source update enable register

This register updates the clock source of the watchdog timer with the new input clock a fter the WDTCLKSEL register has been written to. In order for the update to take effect at the input of the watchdog timer, first write a zero to the WDTCLKUEN register and then write a one to WDTCLKUEN.

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description

value

0x0 IRC oscillator 0x1 Main clock 0x2 Watchdog oscillator 0x3 Reserved

Remark: When switching clock sources, both clocks must be running before the clock source is updated.

Table 23. WDT clock source update enable register (WDTCLKUEN, address 0x4004 80D4)

bit description

Bit Symbol Value Description Reset value

0 ENA Enable WDT clock source update 0x0

0 No change 1 Update clock source

31:1 - - Reserved 0x00

3.5.19 WDT clock divider register

This register determines the divider values for the watchdog clock wdt_clk.

Table 24. WDT clock divider register (WDTCLKDIV, address 0x4004 80D8) bit description

Bit Symbol Description Reset

7:0 DIV W DT clock divider values

0: Disable WDT_PCLK. 1: Divide by 1. to 255: Divide by 255.

31:8 - Reserved 0x00

value

0x00

3.5.20 POR captured PIO status register 0

The PIOPORCAP0 register captures the state (HIGH or LOW) of the PIO pins of ports 0,1, and 2 (pins PIO2_0 to PIO2_7) at power-on-reset. Each bit represents the reset state of one GPIO pin. This register is a read-only status register.

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Table 25. POR captured PIO status registers 0 (PIOPORCAP0, address 0x4004 8100) bit

Bit Symbol Description Reset value

0 CAPPIO0_0 Raw reset status input PIO0_0 User implementation dependent 7:1 - Reserved. 8 CAPPIO0_8 Raw reset status input PIO0_8 User implementation dependent 9 CAPPIO0_9 Raw reset status input PIO0_9 User implementation dependent 10 CAPPIO0_10 Raw reset status input PIO0_10 User implementation dependent 1 1 CAPPIO0_11 Raw reset status input PIO0_11 User implementation dependent 12 CAPPIO1_0 Raw reset status input PIO1_0 User implementation dependent 13 CAPPIO1_1 Raw reset status input PIO1_1 User implementation dependent 14 CAPPIO1_2 Raw reset status input PIO1_2 User implementation dependent 15 CAPPIO1_3 Raw reset status input PIO1_3 User implementation dependent 17:16 - Reserved. 18 CAPPIO1_6 Raw reset status input PIO1_6 User implementation dependent 19 CAPPIO1_7 Raw reset status input PIO1_7 User implementation dependent 31:20 - Reserved. -

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description

3.5.21 BOD control register

The BOD control register selects four separate threshold values for sending a BOD interrupt to the NVIC and for forced reset. Reset and interrupt threshold values listed in

Table 26

Table 26. BOD control register (BODCTRL, address 0x400 4 8150) bit description

Bit Symbol Value Description Reset

1:0 BODRSTLEV BOD reset level 00

3:2 BODINTVAL BOD interrupt level 00

are typical values.

0x0 Level 0: The reset assertion threshold voltage is 1.46 V; the

0x1 Level 1: The reset assertion threshold voltage is 2.06 V; the

0x2 Level 2: The reset assertion threshold voltage is 2.35 V; the

0x3 Level 3: The reset assertion threshold voltage is 2.63 V; the

0x0 Level 0: The interrupt assertion threshold voltage is 1.65 V;

0x1 Level 1:The interrupt assertion threshold voltage is 2.22 V;

0x2 Level 2: The interrupt assertion threshold voltage is 2.52 V;

0x3 Level 3: The interrupt assertion threshold voltage is 2.80 V;

value

reset de-assertion threshold voltage is 1.63 V.

reset de-assertion threshold voltage is 2.15 V.

reset de-assertion threshold voltage is 2.43 V.

reset de-assertion threshold voltage is 2.71 V.

the interrupt de-assertion threshold voltage is 1.80 V.

the interrupt de-assertion threshold voltage is 2.35 V.

the interrupt de-assertion threshold voltage is 2.66 V.

the interrupt de-assertion threshold voltage is 2.90 V.

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Table 26. BOD control register (BODCTRL, address 0x400 4 8150) bit description

Bit Symbol Value Description Reset

4 BODRSTENA BOD reset enable 0

31:5 - - Reserved 0x00

3.5.22 System tick counter calibration register

This register determines the value of the SYST_CALIB register (see Table 138).

Table 27. System tick timer calibration register (SYSTCKCAL, address 0x4004 8154) bit

Bit Symbol Value Description Reset

25:0 CAL System tick timer calibration value 0x04 31:26 - - Reserved 0x00

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value

0 Disable reset function. 1 Enable reset function.

description

value

3.5.23 Start logic edge control register 0

The STARTAPRP0 register controls the start logic input s of ports 0 (PIO0_0 to PIO0_11) and 1 (PIO1_0). This register selects a falling or rising edge on the corresponding PIO input to produce a falling or rising clock edge, respectively, for the start logic (see

Section 3.9.2

Every bit in the STARTAPRP0 register controls one port input and is connected to one wake-up interrupt in the NVIC. Bit 0 in the STARTAPRP0 register corresponds to interrupt 0, bit 1 to interrupt 1, etc. (see Table 44

Remark: Each interrupt connected to a start log ic input must be enabled in the NVIC if the corresponding PIO pin is used to wake up the chip from Deep-sleep mode.

Table 28. Start logic edge control register 0 (STARTAPRP0, address 0x4004 8200) bit

Bit Symbol Value Description Reset

0 APRPIO0_0 Edge select for start logic input PIO0_0 0x0

7:1 - - Reserved 0x0 8 APRPIO0_8 Edge select for start logic input PIO0_8 0x0

9 APRPIO0_9 Edge select for start logic input PIO0_9 0x0

), up to a total of 13 interrupts.

description

0 Falling edge 1 Rising edge

value

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Table 28. Start logic edge control register 0 (STARTAPRP0, address 0x4004 8200) bit

Bit Symbol Value Description Reset

10 APRPIO0_10 Edge select for start logic input PIO0_10 0x0

11 APRPIO0_11 Edge select for start logic input PIO0_11 0x0

12 APRPIO1_0 Edge select for start logic input PIO1_0. 0x0

31:13 - - Reserved 0x0

3.5.24 Start logic signal enable register 0

description

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…continued

value

0 Falling edge 1 Rising edge

This ST ARTERP0 reg ister enables or disables the st art signal bits in the st art logic. The bit assignment is identical to Table 28

Table 29. Start logic signal enable register 0 (STARTERP0, address 0x4004 8204) bit

description

Bit Symbol Value Description Reset

0 ERPIO0_0 Enable start signal for start logic input PIO0_0 0 x 0

0 Disabled

1 Enabled 7:1 - Reserved 0x0 8 ERPIO0_8 Enable start signal for start logic input PIO0_8 0 x 0

0 Disabled

1 Enabled 9 ERPIO0_9 Enable start signal for start logic input PIO0_9 0 x 0

0 Disabled

1 Enabled 10 ERPIO0_10 Enable start signal for start logic input PIO0_10 0x0

0 Disabled

1 Enabled 11 ERPIO0_11 Enable start signal for start logic input PIO0_11 0x0

0 Disabled

1 Enabled 12 ERPIO1_0 Enable start signal for start logic input PIO1_0 0x0

0 Disabled

1 Enabled 31:13 - Reserved 0x0

value

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3.5.25 Start logic reset register 0

Writing a one to a bit in the STARTRSRP0CLR register resets the start logic state. The bit assignment is identical to Table 28 clock edge for registering a start signal. This clock edge (falling or rising) sets the interrupt for waking up from Deep-sleep mode. Therefore, the sta rt-up logic st ates must be cleared before being used.

Table 30. Start logic reset register 0 (STARTRSRP0CLR, address 0x4004 8208) bit

Bit Symbol Value Description Reset

0 RSRPIO0_0 Start signal reset for start logic input PIO0_0 n/a

7:1 - - Reserved n/a 8 RSRPIO0_8 Start signal reset for start logic input PIO0_8 n/a

9 RSRPIO0_9 Start signal reset for start logic input PIO0_9 n/a

10 RSRPIO0_10 Start signal reset for start logic input PIO0_10 n/a

11 RSRPIO0_11 Start signal reset for start logic input PIO0_11 n/a

12 RSRPIO1_0 Start signal reset for start logic input PIO1_0 n/a

31:13 - - Reserved n/a

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. The start-up logic uses the input signals to generate a

description

value

01 Write: reset start signal

3.5.26 Start logic status register 0

This register reflects the status of the enabled start signal bits. The bit assignment is identical to Table 28 or not a wake-up signal has been received for a given pin.

Table 31. Start logic status register 0 (START SRP0, add ress 0x4004 820C) bit description

Bit Symbol Value Description Reset

0 SRPIO0_0 Start signal status for start logic input 0PIO0_0 n/a

7:1 - - Reserved n/a

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. Each bit (if enabled) reflects the state of the start logic, i.e. whether

value

0 No start signal received 1 Start signal pending

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Table 31. Start logic status register 0 (START SRP0, add ress 0x4004 820C) bit description

Bit Symbol Value Description Reset

value

8 SRPIO0_8 Start signal status for start logic input PIO0_8 n/a

0 No start signal received 1 Start signal pending

9 SRPIO0_9 Start signal status for start logic input PIO0_9 n/a

0 No start signal received 1 Start signal pending

10 SRPIO0_10 Start signal status for start logic input PIO0_10 n/a

0 No start signal received 1 Start signal pending

11 SRPIO0_11 Start signal status for start logic input PIO0_11 n/a

0 No start signal received 1 Start signal pending

12 SRPIO1_0 Start signal status for start logic input PIO1_0 n/a

0 No start signal received 1 Start signal pending

31:13 - - Reserved n/a

3.5.27 Deep-sleep mode configuration register

This register controls the behavior of the WatchDog (WD) oscillator and the BOD circuit when the device enters Deep-sleep mode.

This register must be initialized at least once before entering Deep-sleep mode with one of the four values shown in Table 32

Table 32. Allowed values for PDSLEEPCFG register

Configuration WD oscillator on WD oscillator off BOD on PDSLEEPCFG = 0x0000 18B7 PDSLEEPCFG = 0x0000 18F7 BOD off PDSLEEPCFG = 0x0000 18BF PDSLEEPCFG = 0x0000 18FF

Remark: Failure to initialize and program this register correctly may result in undefined behavior of the microcontroller. The values listed in Table 32 for PDSLEEPCFG register.

To select the appropriate power configuration for Deep-sleep mode, consider the following:

• BOD: Leaving the BOD circuit enabled will protect the part from a low voltage event

occurring while the part is in Deep-sleep mode. However, the BOD circuit causes an additional current drain in Deep-sleep mode.

• WD oscillator: The watchdog oscillator can be left running in Deep-sleep mode to

provide a clock for the watchdog timer or a general purpose timer if they are needed for timing a wake-up event (see Section 3.9.3 oscillator analog output frequency must be set to its lowest value (bits FREQSEL in

for details). In this case, the watchdog

are the only values allowed

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Remark: Reserved bits in this register must always be written as indicated. This register

must be initialized correctly before entering Deep-sleep mode.

Table 33. Deep-sleep configuration register (PDSLEEPCFG, address 0x4004 8230) bit

Bit Symbol Value Description Reset

2:0 - Reserved. Always write these bits as 111. 0 3 BOD_PD BOD power-down control in Deep-sleep mode, see

5:4 - Reserved. Always write these bits as 11. 0 6 WDTOSC_PD Watchdog oscillator power control in Deep-sleep

7- Reserved. Always write this bit as 1. 0 10:8 - Reserved. Always write these bits as 000. 0 12:11 - Reserved. Always write these bits as 11. 0 31:13 - Reserved 0

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the WDTOSCCTRL = 0001, see Table 11) and all peripheral clocks other than the timer clock must be disabled in the SYSAHBCLKCTRL register (see Table 19 entering Deep-sleep mode.

The watchdog oscillator, if running, contributes an additional current drain in Deep-sleep mode.

description

Table 32

0 Powered 1 Powered down

mode, see Table 32 0 Powered 1 Powered down

) before

value

3.5.28 Wake-up configuration register

The bits in this register determine the state the chip enters when it is waking up from Deep-sleep mode.

By default, the IRC and flash memory are powered and running and the BOD circuit is enabled when the chip wakes up from Deep-sleep mode.

Remark: Reserved bits must be always written as indicated.

Table 34. Wake-up configuration register (PDAWAKECFG, address 0x4004 8234) bit

description

Bit Symbol Value Description Reset

value

0 IRCOUT_PD IRC oscillator output wake-up configuration 0

0 Powered 1 Pow ered down

1 IRC_PD IRC oscillator power-down wake-up configuration 0

0 Powered 1 Pow ered down

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Table 34. Wake-up configuration register (PDAWAKECFG, address 0x4004 8234) bit

Bit Symbol Value Description Reset

2 FLASH_PD Flash wake-up configuration 0

3 BOD_PD BOD wake-up configuration 0

4 ADC_PD ADC wake-up configuration 1

5 SYSOSC_PD System oscillator wake-up configuration 1

6 WDTOSC_PD Watchdog oscillator wake-up configuration 1

7 SYSPLL_PD System PLL wake-up configuration 1

8 - Reserved. Always write this bit as 1. 1 9 - Reserved. Always write this bit as 0. 0 10 - Reserved. Always write this bit as 1. 1 1 1 - Reserved. Always write this bit as 1. 1 12 - Reserved. Always write this bit as 0. 0 15:13 - Reserved. Always write these bits as 111. 111 31:16 - - Reserved -

description

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…continued

value

0 Powered 1 Pow ered down

3.5.29 Power-down configuration register

The bits in the PDRUNCFG register control the power to the various analog blocks. This register can be written to at any time while the chip is running, and a write will take effect immediately with the exception of the power-down signal to the IRC.

To avoid glitches when powering down the IRC, the IRC clock is automatically switched off at a clean point. Therefore, for the IRC a delay is possible before the power-down state takes effect.

By default, the IRC and flash memory are powered and running and the BOD circuit is enabled.

Remark: Reserved bits must be always written as indicated.

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Table 35. Power-down configuration register (PDRUNCFG, address 0x4004 8238) bit

Bit Symbol Value Description Reset

0 IRCOUT_PD IRC oscillator output power-down 0

1 IRC_PD IRC oscillator power-down 0

2 FLASH_PD Flash power-down 0

3 BOD_PD BOD power-down 0

4 ADC_PD ADC power-down 1

5 SYSOSC_PD System oscillator power-down 1

6 WDTOSC_PD Watchdog oscillator power-down 1

7 SYSPLL_PD System PLL power-down 1

8 - Reserved. Always write this bit as 1. 1 9 - Reserved. Always write this bit as 0. 0 10 - Reserved. Always write this bit as 1. 1 11 - Reserved. Always write this bit as 1. 1 12 - Reserved. Always write this bit as 0. 0 15:13 - Reserved. Always write these bits as 111. 111 31:16 - - Reserved -

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description

value

0 Powered 1 Powered down

3.5.30 Device ID register

This device ID register is a read-only register and contains the part ID for each LPC1102 part. This register is also read by the ISP/IAP commands (Section 19.5.11

Table 36. Device ID register (DEVICE_ID, address 0x4004 83F4) bit d escription

Bit Symbol Description Reset value

31:0 DEVICEID Part ID numbers for LPC1102 parts

LPC1102 = 0x2500 102B

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3.6 Reset

Reset has four sources on the LPC1102: the RESET pin, Watchdog Reset, Power-On Reset (POR), and Brown Out Detect (BOD). In addition, there is a software reset.

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The RESET the operating voltage attains a usable level, starts the IRC causing reset to remain asserted until the external Reset is de-asserted, the oscillator is running, and the flash controller has completed its initialization.

On the assertion of a reset source external to the Cortex-M0 CPU (POR, BOD reset, External reset, and Watchdog reset), the following processes are initiated:

1. The IRC starts up. After the IRC-start-up time (maximum of 6 μs on power-up), the IRC provides a stable clock output.

2. The boot code in the ROM starts. The boot code per forms the boot tasks and may jump to the flash.

3. The flash is powered up. This takes approximately 100 μs. Then the flash initialization sequence is started, which takes about 250 cycles.

When the internal Reset is removed, the processor begins executing at address 0, which is initially the Reset vector mapped from the boot block. At that point, all of the processor and peripheral registers have been initialized to predetermined values.

3.7 Brown-out detection

The LPC1 10 2 includes four levels for m onitoring th e volta ge on the VDD pin. If this voltage falls below one of the four selected levels, the BOD asserts an interrupt signal to the NVIC. This signal can be enabled for interrupt in the Interr upt Enable Register in the NVIC in order to cause a CPU interrupt; if not, software can monitor the signal by reading the NVIC status register (see Table 44 cause a forced reset of the chip (see Table 26

pin is a Schmitt trigger input pin. Assertion of chip Reset by any source, once

). An additional four threshold levels can be selected to

3.8 Power management

The LPC1102 support a variety of power control features. In Active mode, when the chip is running, power and clocks to selected peripherals can be optimized for power consumption. In addition, there are three special modes of processor power reduction: Sleep mode and Deep-sleep mode mode.

Remark: The Debug mode is not supported in Sleep or Deep-sleep mode.

3.8.1 Active mode

In Active mode, the ARM Cortex-M0 core and memories are clocked by the syste m clock, and peripherals are clocked by the system clock or a dedicated peripheral clock.

The chip is in Active mode after reset and the default power configuration is determined by the reset values of the PDRUNCFG and SYSAHBCLKCTRL registers. The power configuration can be changed during run time.

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+ 228 hidden pages

NXP Semiconductors LPC1102 User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

1.1 Introduction

1.2 Features

Chapter 1: LPC1102 Introductory information

1.3 Ordering information

1.4 Block diagram

1.5 ARM Cortex-M0 processor

Chapter 2: LPC1102 Memory mapping

2.1 How to read this chapter

2.2 Memory map

Chapter 3: LPC1102 System configuration

3.1 How to read this chapter

3.2 Introduction

3.3 Pin description

3.4 Clocking and power control

3.5 Register description

3.5.1 System memory remap register

3.5.2 Peripheral reset control register

3.5.3 System PLL control register

3.5.4 System PLL status register

3.5.5 System oscillator control register

3.5.6 Watchdog oscillator control register

3.5.7 Internal resonant crystal control register

3.5.8 System reset status register

3.5.9 System PLL clock source select register

3.5.10 System PLL clock source update enable register

3.5.11 Main clock source select register

3.5.12 Main clock source update enable register

3.5.13 System AHB clock divider register

3.5.14 System AHB clock control register

3.5.15 SPI0 clock divider register

3.5.16 UART clock divider register

3.5.17 WDT clock source select register

3.5.18 WDT clock source update enable register

3.5.19 WDT clock divider register

3.5.20 POR captured PIO status register 0

3.5.21 BOD control register

3.5.22 System tick counter calibration register

3.5.23 Start logic edge control register 0

3.5.24 Start logic signal enable register 0

3.5.25 Start logic reset register 0

3.5.26 Start logic status register 0

3.5.27 Deep-sleep mode configuration register

3.5.28 Wake-up configuration register

3.5.29 Power-down configuration register

3.5.30 Device ID register

3.6 Reset

3.7 Brown-out detection

3.8 Power management

3.8.1 Active mode