NXP Semiconductors KITFS85SKTEVM User Manual

UM11183

KITFS85SKTEVM evaluation board

Rev. 2.0 — 20 February 2019 User guide

Figure 1. KITFS85SKTEVM

Important Notice

NXP provides the enclosed product(s) under the following conditions: This evaluation kit is intended for use of ENGINEERING DEVELOPMENT OR EVALUATION PURPOSES ONLY. It is provided as a

sample IC pre-soldered to a printed circuit board to make it easier to access inputs, outputs, and supply terminals. This evaluation board may be used with any development system or other source of I/O signals by simply connecting it to the host MCU or computer board via off-the-shelf cables. This evaluation board is not a Reference Design and is not intended to represent a final design recommendation for any particular application. Final device in an application will be heavily dependent on proper printed circuit board layout and heat sinking design as well as attention to supply filtering, transient suppression, and I/O signal quality.

The goods provided may not be complete in terms of required design, marketing, and or manufacturing related protective considerations, including product safety measures typically found in the end product incorporating the goods. Due to the open construction of the product, it is the user's responsibility to take any and all appropriate precautions with regard to electrostatic discharge. In order to minimize risks associated with the customers applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. For any safety concerns, contact NXP sales and technical support services.

Should this evaluation kit not meet the specifications indicated in the kit, it may be returned within 30 days from the date of delivery and will be replaced by a new kit.

NXP reserves the right to make changes without further notice to any products herein. NXP makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does NXP assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. Typical parameters can and do vary in different applications and actual performance may vary over time. All operating parameters, including Typical, must be validated for each customer application by customer’s technical experts.

NXP does not convey any license under its patent rights nor the rights of others. NXP products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the NXP product could create a situation where personal injury or death may occur.

Should the Buyer purchase or use NXP products for any such unintended or unauthorized application, the Buyer shall indemnify and hold NXP and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges NXP was negligent regarding the design or manufacture of the part.

NXP Semiconductors

1 Introduction

This document is the user guide for the KITFS85SKTEVM evaluation board. This document is intended for the engineers involved in the evaluation, design, implementation, and validation of FS8500 Fail-safe system basis chip with multiple SMPS and LDO.

The scope of this document is to provide the user with information to evaluate the FS8500 Fail-safe system basis chip with multiple SMPS and LDO. This document covers connecting the hardware, installing the software and tools, configuring the environment and using the kit.

The KITFS85SKTEVM enables development on FS84/FS85 family of devices. The kit can be connected to the FlexGUI software which allows you to play with registers, try OTP configurations, and burn the part.

The devices can be placed and removed easily from the board by using the socket. The device OTP can be burned three times, which provides a good flexibility. This board supports FS84/FS85 family of devices.

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KITFS85SKTEVM evaluation board

2 Finding kit resources and information on the NXP web site

NXP Semiconductors provides online resources for this evaluation board and its supported device(s) on http://www.nxp.com.

The information page for KITFS85SKTEVM evaluation board is at http://www.nxp.com/

KITFS85SKTEVM. The information page provides overview information, documentation,

software and tools, parametrics, ordering information and a Getting Started tab. The Getting Started tab provides quick-reference information applicable to using the KITFS85SKTEVM evaluation board, including the downloadable assets referenced in this document.

2.1 Collaborate in the NXP community

The NXP community is for sharing ideas and tips, ask and answer technical questions, and receive input on just about any embedded design topic.

The NXP community is at http://community.nxp.com.

3 Getting ready

Working with the KITFS85SKTEVM requires the kit contents, additional hardware and a Windows PC workstation with installed software.

3.1 Kit contents

• Assembled and tested evaluation board in an anti-static bag

• 3.0 ft USB-STD A to USB-B-mini cable

• Two connectors, terminal block plug, 2 pos., str. 3.81 mm

• Three connectors, terminal block plug, 3 pos., str. 3.81 mm

• Jumpers mounted on board

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3.2 Additional hardware

In addition to the kit contents, the following hardware is necessary or beneficial when working with this kit.

• Power supply with a range of 8.0 V to 60 V and a current limit set initially to 1.0 A

3.3 Windows PC workstation

This evaluation board requires a Windows PC workstation. Meeting these minimum specifications should produce great results when working with this evaluation board.

• USB-enabled computer with Windows 7 or Windows 10

3.4 Software

Installing software is necessary to work with this evaluation board. All listed software is available on the evaluation board's information page at http://www.nxp.com/

KITFS85SKTEVM or from the provided link.

• FlexGUI latest version

• FS85_FS84_OTP_Config.xlsm

• Java installation https://www.oracle.com/technetwork/java/javase/downloads/jre8-

downloads-2133155.html

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KITFS85SKTEVM evaluation board

4 Getting to know the hardware

The KITFS85SKTEVM provides flexibility to play with all the features of the device and make measurements on the main part of the application. The KL25Z MCU installed on the board, combined with the FlexGUI software allows access to the registers in read and write mode. All regulators are accessible through connectors. Nonuser signals, like DC/ DC switcher node are mapped on test points. Digital signals (SPI, I2C, RSTb, etc.) are accessible through connectors. Wake1 pin has a switch to control (Ignition) them. A V switch is available to power On or Off the device.

The main purpose of this kit is to burn the OTP configuration. This kit can be operated in Emulation mode or in OTP mode. In Emulation mode, as long as the power is supplied, the board configuration stays valid. The OTP mode uses the fused configuration. The device can be fused three times. In OTP mode, the device always starts with the fused configuration, except if the user wants to overwrite OTP configuration using Emulation mode. This board is able to fuse the OTP without any extra tools or board.

Note: Due to the socket, this kit is not optimized for performance measurement or current higher than 1.0 A.

4.1 Kit overview

The KITFS85SKTEVM is a hardware evaluation tool that allows OTP burning. Due to the socket, the FS84/FS85 part can be configured without the need to solder it. Devices can be programmed three times (see Section 7.3 "Programming the device with an OTP

configuration").

BAT

An Emulation mode is possible to test as many configurations as needed.

An external LDO provides VDDI2C voltage with a choice of 1.8 V or 3.3 V (default). VDDIO is assigned by default to VDDI2C. From USB voltage, an external DC/DC

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generates the OTP programming voltage (8.0 V) without any need for an external power supply.

4.1.1 KITFS85SKTEVM features

• VBAT power supply connectors (Jack and Phoenix)

• VPRE output capability up to 1.0 A (socket limit)

• VBUCK1/2 in Standalone (default) or Multiphase mode

• VBUCK3

• VBOOST 5.0 V or 5.74 V

• LDO1 and LDO2, from 1.1 V to 5.0 V

• Ignition key switch

• FS0B external safety pin

• Embedded USB connection for easy connection to software GUI (access to SPI/I2C

bus, IOs, RSTB, FS0B, INTB, Debug, MUX_OUT, regulators)

• LEDs that indicate signal or regulator status

• Support OTP fuse capabilities

• USB connection for register access, OTP emulation and programming

• Voltage monitoring jumper setting

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KITFS85SKTEVM evaluation board

Note: Due to the socket, all current capabilities are limited to 1.0 A.

4.1.2 VMON board configuration

The VMONx configuration is highly dependent on the use case. This kit is delivered with a default configuration shown in Figure 2.

This configuration supports the following mapping:

• VPRE, assigned to VMON1; Bridge resistor set for 3.3 V

• BUCK2, assigned to VMON2; Bridge resistor set for 1.8 V

• BUCK3, assigned to VMON3; Bridge resistor set for 3.3 V

• LDO1, assigned to VMON4; Bridge resistor set for 3.3 V

• LDO2, assigned to VMON4; Bridge resistor set for 5.0 V

LDO1 and LDO2 use the same VMON, a reassignement is necessary to monitor both.

Due to the jumpers, VMONx can be tied to a 0.8 V to force a good voltage at pin level. This behaves like hardware disabling and makes debug easy in some cases.

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aaa-03276

VPRE_MON1

VPRE

VMON _08V

J22

GND

HDR 1X3

R191

22.1 kΩ

R217 0 Ω DNP

R181

68.1 kΩ

BUCK2_MON2

BUCK2

VMON _08V

J23

GND

HDR 1X3

R190

22.1 kΩ

R180

27.4 kΩ

BUCK3_MON3

BUCK3

VMON _08V

J24

GND

HDR 1X3

R189

22.1 kΩ

R178

68.1 kΩ

LDO_MON4

LDO1

VMON _08V

J21

GND

HDR 1X3

R192

22.1 kΩ

R182

68.1 kΩ

LDO2

GND

R208

22.1 kΩ

R207

115 kΩ

aaa-03276

GND

450 KHz

C18

6800 pF

C14

150 pF

J12

3.57 kΩ

GND

2.25 MHz

C19

1500 pF

C15

22 pF

R10

16.9 kΩ

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KITFS85SKTEVM evaluation board

Figure 2. VMONx configuration

4.1.3 VPRE compensation network

This board is delivered with a VPRE compensation network defined for VPRE 4.1 V at 450 kHz. All other VPRE configurations require a new calculation for these components.

User guide Rev. 2.0 — 20 February 2019

Figure 3. VPRE compensation network

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aaa- 032767

BUCK1

BUCK2

R11 0 DNP

R145 0 DNP

aaa-03276

2 4 6 8 10 12

RSTb_SH FS0b_SH MISO_SH MOSI_SH

[3] RSTb [3] FS0b [3] MISO [3] MOSI

[3] CSB

[3] SCLK

SCLK_SH CSB_SH

J28

3 5 7 9

Table 1. Compensation network

Components VPRE 450 kHz VPRE 2.2 MHz

C18/C19 6.8 nF 1.5 nF

C14/C15 150 pF 22 pF

R6/R10 3.57 kΩ 16.9 kΩ

LPRE 4.7 µH or 6.8 µH 1.5 µH, 2.2 µH or 4.7 µH

4.1.4 BUCK1 and BUCK2 multiphase configuration

The board is designed to work independently with BUCK1 and BUCK2. Due to R11 and R145, it is possible to connect both connectors together and work in multiphase.

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KITFS85SKTEVM evaluation board

Figure 4. BUCK1 and BUCK2 multiphase configuration

4.1.5 SPI/I2C

The SPI and I2C buses are connected to KL25Z MCU. The user can use either one or the other. The choice can be done at start of the FlexGUI or at any time after launch (see

Section 8 "Using FlexGUI").

This kit uses a KL25Z MCU to communicate with FlexGUI. However, if the user wants to connect the SPI to another MCU, this is possible. In this case, remove J28 and appropriate jumpers to disconnect the KL25Z MCU (see Figure 5) and connect the external MCU on J30 connector as shown in Figure 6. In addition to this change, make sure that the VDDIO voltage domain is the same on MCU side and SBC side.

Figure 5. SPI connection to KL25Z

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aaa-032822

109

1211

1413

MOSI

MISO

SCLK

CSB

VSUP

GND

WAKE1

J30

VDDI2C

I2C_SDA

I2C_SCL

VDDIO_EXT

DBG

GND

aaa-03276

2 4 6 8 10

LDO1 LDO2 VDDI2C BUCK3

VDDIO_EXT

P3V3_KL25Z

DNP

0 Ω

VDDIO

selection

VDDIO

J11

3 5 7 9

aaa-03277

GND

OUT

MIC523 5YM5

VDDI2C

ADJ

GND

VDDI2C_SEL

P5V0_USB

C145

1.0 µF

C137

2.2 µF

J20

1.8 V3.3 V

123

R21

52.3 kΩ

R15 191 kΩ

R193 115 kΩ

Figure 6. J30 SPI connection

4.1.6 VDDI2C

As an option, an external LDO is provided to feed VDDI2C. This LDO can also be used to feed VDDIO, which is the default implementation.

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KITFS85SKTEVM evaluation board

The I2C is compatible with 1.8 V or 3.3 V, while VDDIO is compatible with 3.3 V and

5.0 V. For this reason, the LDO default configuration is 3.3 V. The LDO is supplied by

5.0 V coming from the USB.

Figure 7. VDDIO selection

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Figure 8. VDDI2C supply

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aaa-03196

SPI/I2C

primary CONFIG

images CONFIG

FS85 SOC

configuration

mirror

S1 - CONFIG

OTP fuse

configuration

S1 - CONFIG

S1bis - CONFIG

S1ter - CONFIG

4.2 Device OTP user configuration

It is recommended to learn about OTP before operating with the device. The device has a high level of flexibility due to parameter configuration available in the OTP. This impacts the functionality of the device. It is key to understand how OTP parameters can be programmed, the interaction with mirror registers and the FS85 SoC.

The OTP related operations can be performed either in Emulation mode, where the product uses a given configuration as long as power supply is not switched Off or from OTP fuse content that is valid even after a power down/power up sequence.

4.2.1 OTP and mirrors registers

There are two OTP blocks in the device. One is for the main section, and the other for the fail-safe. During configuration, each of them are using dedicated sectors. The OTP configuration scheme is shown in Figure 9 (same implementation for main and fail-safe).

The device can be fused three times using mirror registers. The user can first load the mirror register content with the desired contents, then decide either to use the device in Emulation mode or to burn the next sector. The first sector to be burned is S1, the second S1bis and the third S1ter. FlexGUI automatically manages the next sector to be burned. It is not possible to revert back to the previous sector. When the user reaches the sector S1ter, there no other possibility for burn, however emulation mode is still available.

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KITFS85SKTEVM evaluation board

Figure 9. OTP configuration

At boot, the content of the valid sector is loaded into the Mirror Register Sector 1. The mirror register content is accessible from FlexGUI by using specific SPI/I2C commands. The mirror configuration is managed by the FlexGUI, which eases the access.

4.2.2 OTP hardware implementation

To work in OTP emulation or OTP programming, it is required to start the device in Debug mode.

User guide Rev. 2.0 — 20 February 2019

Figure 10 shows the sequence to be followed to enter in Debug mode. The voltage

sequence on the kit is done using switches installed on the board, while the OTP registers configuration is managed by the FlexGUI GUI. This is described in detail in the following sections.

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aaa-03196

DBG

VSUP1/2

WAKE1

SPI/I2C

REGx

> V

SUP_UVH

> WAKE12

VIH

SPI/I2C OTP pgm

OFF PWR UP ON

SPI/I2C

aaa- 032762

SW1

SW2

VSUP1/2

FS8500

Debug

ref

OTP level (DBG = 8 V)

VSUP

DBG_OTP

(8 V)

DBG VDDI2C

USB

VBAT

to KL25

DC/DC

P5V_USB

DBG_BAT

WAKE1

SW3

J17

Figure 10. Debug mode entry

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KITFS85SKTEVM evaluation board

Figure 11 shows the hardware kit implementation.

Figure 11. OTP hardware implementation

4.3 Kit featured components

Figure 12 identifies important components on the board and Table 2 provides additional

details on these components.

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KITFS85SKTEVM evaluation board

1. V

2. V

3. V

Jack connector

BAT

three position switch

BAT

Phoenix connector

BAT

4. LDO1/LDO2 power supplies

5. VPRE power supply

6. BUCK1/BUCK2 power supply

7. USB connector (for FlexGUI control)

8. Debug connectivity

9. Programming

10. Wake1 switch

11. OTP burning voltage switch

12. VBOOST and BUCK3 power supply

13. DEBUG voltage source

14. Compensation network selection

15. VDDIO selection

16. SPI / RSTb / FS0b connection to MCU

17. RSTb, INTb and FS0b signals

18. VMONx, VDDI2C selection

Figure 12. Evaluation board featured component locations

Table 2. Evaluation board board component descriptions

Number Description

1 V

2 V

3 V

4 LDO1/LDO2 power supply

5 VPRE power supply

6 BUCK1/BUCK2 power supply

7 USB connector (for FlexGUI control)

Jack connector

BAT

three position switch

BAT

• Left position: board supplied by Jack connector

• Middle position: board not supplied

• Right position: board supplied by Phoenix connector

Phoenix connector

BAT

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Number Description

8 Debug connectivity. Access to:

9 Programming

10 Wake1 switch

11 OTP burning voltage switch

12 VBOOST and BUCK3 power supply

13 DEBUG voltage source either from USB (recommended) or from VSUP

14 VPRE compensation network selection, either 2.2 MHz or 450 kHz

15 VDDIO source from device regulators or external sources

16 SPI, RSTb or FS0b can be disconnected between device and MCU

17 RSTb, INTb and FS0b signals available here (device pin level)

18 Allows to select VMON from regulators or a fix 0.8 V

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KITFS85SKTEVM evaluation board

• VSUP, GND

• FOUT/FIN

• PGOOD/RST/FS0b

• FCCUx

• Wake2

• PSYNC, ERRMON, AMUX

• VMONx

• SPI bus

• I2C bus

• Debug pin

• VPRE, VSUP, GND

VDDI2C can be selected either 1.8 V or 3.3 V

4.3.1 FS8500/FS8400: Fail-safe system basis chip with multiple SMPS and LDO

4.3.1.1 General description

This device family is part of a global platform FS84 (fit for ASIL B) and FS85 (fit for ASIL D), pin to pin and software compatible. The FS85/FS84 is an automotive functionally safe multi-output power supply integrated circuit, with focus on Radar, Vision, ADAS domain controller, Radio and Infotainment applications. It includes multiple switch mode and linear voltage regulators. It offers external frequency synchronization input and output, for optimized system EMC performance.

The FS85/FS84 includes enhanced safety features, with fail-safe output, becoming a full part of a safety-oriented system partitioning, covering both ASIL B and ASIL D safety integrity level. It is developed in compliance with ISO 26262 standard. Several device versions are available, offering choice in number of output rails, output voltage setting, operating frequency and power up sequencing, to address multiple applications.

4.3.1.2 Features

• 60 V DC maximum input voltage for 12 V and 24 V applications

• VPRE synchronous buck controller with external MOSFETs. Configurable output

voltage, switching frequency, and current capability up to 10 A peak.

• Low voltage integrated synchronous BUCK1 converter, dedicated to MCU core supply with SVS capability. Configurable output voltage and current capability up to 3.6 A peak.

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• Based on part number: low voltage integrated synchronous BUCK2 converter.

Configurable output voltage and current capability up to 3.6 A peak. Multi-phase capability with BUCK1 to extend the current capability up to 7.2 A peak on a single rail. Static voltage scaling capability.

• Based on part number: low voltage integrated synchronous BUCK3 converter. Configurable output voltage and current capability up to 2.5 A typical peak.

• BOOST converter with integrated low-side switch. Configurable output voltage and max input current up to 1.5 A peak.

• EMC optimization techniques including SMPS frequency synchronization, spread spectrum, slew rate control, manual frequency tuning

• 2x linear voltage regulators for MCU IOs and ADC supply, external physical layer. Configurable output voltage and current capability up to 400 mA DC.

• Standby OFF mode with very low sleep current (10 μA typ)

• 2x input pins for wake-up detection and battery voltage sensing

• Device control via 32 bits SPI or I2C interface with CRC

• Power synchronization pin to operate 2x FS85 devices or FS85 plus an external PMIC

• Scalable portfolio from ASIL B to ASIL D with independent monitoring circuitry,

dedicated interface for MCU monitoring, simple and challenger watchdog function, power good, reset and interrupt, built-in self-test, fail-safe output

• Configuration by OTP programming. Prototype enablement to support custom setting during project development in engineering mode.

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KITFS85SKTEVM evaluation board

4.3.2 Indicators

The following LEDs are provided as visual output devices for the evaluation board:

Figure 13. Evaluation board indicator locations

Table 3. Evaluation board indicator descriptions

Label Name Color Description

D1 V

D2 LDO1 Green LDO1 On

D3 LDO2 Green LDO2 On

BAT

Green V

BAT

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Label Name Color Description

D4 BUCK1 Green BUCK1 On

D6 BUCK2 Green BUCK2 On

D7 BUCK3 Green BUCK3 On

D8 VBOOST Green VBOOST On

D9 V

D12 DBG > 8.0 V Blue DBG pin voltage > 8.0 V (OTP programming)

D13 RSTb Red RSTb asserted (logic level = 0)

D14 INTb Red INTb asserted (logic level = 0)

D15 FS0b Red FS0b asserted (logic level = 0)

D16 P3V3_KL25 Green P3V3_KL25 On

D106 PGOOD Green PGOOD released

4.3.3 Connectors

Figure 14 shows the location of connectors on the board.

PRE

Green V

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KITFS85SKTEVM evaluation board

PRE

Figure 14. Evaluation board connector locations

4.3.3.1 V

connector (J1)

BAT

VBAT connects to the board through Phoenix connector (J1).

Table 4. V

Schematic label Signal name Description

J1-1 V

J1-2 GND Ground

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Phoenix connector (J1)

BAT

Battery voltage supply input

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4.3.3.2 Output power supply connectors

Table 5. BUCK1/BUCK2 connector (J14)

Schematic label Signal name Description

J14-1 BUCK2 BUCK2 power supply output

J14-2 BUCK1 BUCK1 power supply output

J14-3 GND Ground

Table 6. VBOOST/BUCK3 connector (J16)

Schematic label Signal name Description

J16-1 VBOOST VBOOST output

J16-2 BUCK3 BUCK3 power supply output

J16-3 GND Ground

Table 7. LDO1/LDO2 connector (J2)

Schematic label Signal name Description

J2-1 LDO1 LDO1 power supply output

J2-2 LDO2 LDO2 power supply output

J2-3 GND Ground

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Table 8. VPRE connector (J3)

Schematic label Signal name Description

J3-1 VPRE VPRE power supply output

J3-2 GND Ground

4.3.3.3 Debug connector (J29)

Table 9. Debug connector (J29)

Schematic label Signal name Description

J29-1 FOUT Frequency synchronization output

J29-2 FIN Frequency synchronization input

J29-3 PGOOD Power GOOD

J29-4 n.c. not connected

J29-5 INTB Interrupt, active low

J29-6 n.c. not connected

J29-7 RSTb Reset, active low

J29-8 n.c. not connected

J29-9 ERRMON Error monitoring

J29-10 n.c. not connected

J29-11 AMUX Analog multiplexer

J29-12 FS0b_Out Fail-safe, active low

J29-13 VDDIO_EXT VDDIO external reference

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Schematic label Signal name Description

J29-14 PSYNC Power synchronization

J29-15 VDDIO VDDIO used by FS85

J29-16 WAKE2_IN Wake2 input

J29-17 FCCU1 Fault collector control unit 1

J29-18 VSUP VSUP power supply

J29-19 FCCU2 Fault collector control unit 2

J29-20 GND Ground

4.3.3.4 Program connector (J30)

Table 10. Program connector (J30)

Schematic label Signal name Description

J30-1 WAKE1 WAKE1 input

J30-2 MOSI SPI master output slave input

J30-3 VDDI2C VDDI2C voltage

J30-4 MISO SPI master input slave output

J30-5 I2C_SDA I2C serial data

J30-6 SCLK SPI clock

J30-7 I2C_SCL I2C serial clock

J30-8 CSB SPI chip select

J30-9 n.c. not connected

J30-10 VPRE VPRE output

J30-11 DBG Connected to Debug pin

J30-12 GND Ground

J30-13 n.c. not connected

J30-14 VSUP Connected to VSUP pin

J30-15 GND Ground

J30-16 GND Ground

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4.3.4 Test points

The following test points provide access to various signals to and from the board.

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+ 35 hidden pages

NXP Semiconductors KITFS85SKTEVM User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

1 Introduction

2.1 Collaborate in the NXP community

3 Getting ready

3.1 Kit contents

3.2 Additional hardware

3.3 Windows PC workstation

3.4 Software

4 Getting to know the hardware

4.1 Kit overview

4.1.2 VMON board configuration

4.1.3 VPRE compensation network

4.1.4 BUCK1 and BUCK2 multiphase configuration

4.1.5 SPI/I2C

4.1.6 VDDI2C

4.2 Device OTP user configuration

4.2.1 OTP and mirrors registers

4.2.2 OTP hardware implementation

4.3 Kit featured components

4.3.1 FS8500/FS8400: Fail-safe system basis chip with multiple SMPS and LDO

4.3.1.1 General description

4.3.1.2 Features

4.3.2 Indicators

4.3.3 Connectors

4.3.3.2 Output power supply connectors

4.3.3.3 Debug connector (J29)

4.3.3.4 Program connector (J30)

4.3.4 Test points