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Kinetis KE1xZ256
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NXP Semiconductors Kinetis KE1xZ256, MKE15Z128VLH7, MKE14Z256VLL7, MKE14Z256VLH7, MKE14Z128VLL7 Reference Manual

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Page 1
Kinetis KE1xZ256 Sub-Family
Reference Manual
Supports: MKE15Z256VLL7, MKE15Z256VLH7; MKE15Z128VLL7,
MKE15Z128VLH7; MKE14Z256VLL7, MKE14Z256VLH7;
MKE14Z128VLL7, MKE14Z128VLH7.
Document Number: KE1xZP100M72SF0RM
Rev. 3, 07/2018
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Contents
Section number Title Page
Chapter 1
About This Manual
1.1 Audience....................................................................................................................................................................... 43
1.2 Organization..................................................................................................................................................................43
1.3 Module descriptions......................................................................................................................................................43
1.3.1 Example: chip-specific information that supersedes content in the same chapter.........................................44
1.3.2 Example: chip-specific information that refers to a different chapter........................................................... 45
1.4 Register descriptions.....................................................................................................................................................46
1.5 Conventions.................................................................................................................................................................. 47
1.5.1 Numbering systems........................................................................................................................................47
1.5.2 Typographic notation..................................................................................................................................... 47
1.5.3 Special terms.................................................................................................................................................. 48
Chapter 2
Introduction
2.1 Overview.......................................................................................................................................................................49
2.2 Block Diagram..............................................................................................................................................................49
2.3 Module Functional Categories......................................................................................................................................50
Chapter 3
Core Overview
3.1 ARM Cortex-M0+ ....................................................................................................................................................... 53
3.2 Core Buses and Interfaces.............................................................................................................................................54
3.3 Core Component Configuration....................................................................................................................................55
3.4 SysTick Clock Configuration....................................................................................................................................... 55
Chapter 4 Interrupts
4.1 Introduction...................................................................................................................................................................57
4.2 NVIC configuration...................................................................................................................................................... 57
4.2.1 Interrupt priority levels.................................................................................................................................. 57
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4.2.2 Non-maskable interrupt..................................................................................................................................58
4.3 Interrupt channel assignments.......................................................................................................................................58
4.3.1 Determining the bitfield and register location for configuring a particular interrupt.................................... 60
Chapter 5
System Integration Module (SIM)
5.1 Introduction...................................................................................................................................................................63
5.1.1 Features.......................................................................................................................................................... 63
5.2 Memory map and register definition.............................................................................................................................63
5.2.1 Chip Control register (SIM_CHIPCTL)........................................................................................................ 64
5.2.2 FTM Option Register 0 (SIM_FTMOPT0)................................................................................................... 66
5.2.3 ADC Options Register (SIM_ADCOPT)...................................................................................................... 67
5.2.4 FTM Option Register 1 (SIM_FTMOPT1)................................................................................................... 69
5.2.5 System Device Identification Register (SIM_SDID).....................................................................................71
5.2.6 Flash Configuration Register 1 (SIM_FCFG1)............................................................................................. 72
5.2.7 Flash Configuration Register 2 (SIM_FCFG2)............................................................................................. 74
5.2.8 Unique Identification Register High (SIM_UIDH)....................................................................................... 75
5.2.9 Unique Identification Register Mid-High (SIM_UIDMH)............................................................................75
5.2.10 Unique Identification Register Mid Low (SIM_UIDML)............................................................................. 76
5.2.11 Unique Identification Register Low (SIM_UIDL)........................................................................................ 76
5.2.12 Miscellaneous Control register (SIM_MISCTRL)........................................................................................ 77
Chapter 6
Memory-Mapped Divide and Square Root (MMDVSQ)
6.1 Chip-specific Information for this Module...................................................................................................................79
6.2 Introduction...................................................................................................................................................................79
6.2.1 Features.......................................................................................................................................................... 79
6.2.2 Block diagram................................................................................................................................................ 80
6.2.3 Modes of operation........................................................................................................................................ 82
6.3 External signal description............................................................................................................................................83
6.4 Memory map and register definition.............................................................................................................................83
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6.4.1 Dividend Register (MMDVSQ_DEND)........................................................................................................84
6.4.2 Divisor Register (MMDVSQ_DSOR)........................................................................................................... 84
6.4.3 Control/Status Register (MMDVSQ_CSR)................................................................................................... 86
6.4.4 Result Register (MMDVSQ_RES)................................................................................................................ 89
6.4.5 Radicand Register (MMDVSQ_RCND)....................................................................................................... 89
6.5 Functional description...................................................................................................................................................90
6.5.1 Algorithms..................................................................................................................................................... 90
6.5.2 Execution times..............................................................................................................................................93
6.5.3 Software interface.......................................................................................................................................... 95
Chapter 7
Miscellaneous Control Module (MCM)
7.1 Chip-specific Information for this Module...................................................................................................................97
7.2 Introduction...................................................................................................................................................................98
7.2.1 Features.......................................................................................................................................................... 98
7.3 Memory map/register descriptions............................................................................................................................... 98
7.3.1 Crossbar Switch (AXBS) Slave Configuration (MCM_PLASC)..................................................................99
7.3.2 Crossbar Switch (AXBS) Master Configuration (MCM_PLAMC).............................................................. 99
7.3.3 Platform Control Register (MCM_PLACR)..................................................................................................100
7.3.4 Compute Operation Control Register (MCM_CPO)..................................................................................... 103
Chapter 8
Bit Manipulation Engine (BME)
8.1 Chip-specific Information for this Module...................................................................................................................105
8.2 Introduction...................................................................................................................................................................105
8.2.1 Overview........................................................................................................................................................ 106
8.2.2 Features.......................................................................................................................................................... 107
8.2.3 Modes of operation........................................................................................................................................ 107
8.3 Memory map and register definition.............................................................................................................................107
8.4 Functional description...................................................................................................................................................108
8.4.1 BME decorated stores.................................................................................................................................... 108
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8.4.2 BME decorated loads..................................................................................................................................... 115
8.4.3 Additional details on decorated addresses and GPIO accesses......................................................................121
8.5 Application information................................................................................................................................................122
Chapter 9
Crossbar Switch Lite (AXBS-Lite)
9.1 Chip-specific Information for this Module...................................................................................................................125
9.2 Introduction...................................................................................................................................................................126
9.2.1 Features.......................................................................................................................................................... 126
9.3 Memory Map / Register Definition...............................................................................................................................127
9.4 Functional Description..................................................................................................................................................127
9.4.1 General operation........................................................................................................................................... 127
9.4.2 Arbitration...................................................................................................................................................... 128
9.5 Initialization/application information........................................................................................................................... 129
Chapter 10
Peripheral Bridge (AIPS-Lite)
10.1 Chip-specific information for this module....................................................................................................................131
10.1.1 Instantiation Information................................................................................................................................131
10.2 Introduction...................................................................................................................................................................132
10.2.1 Features.......................................................................................................................................................... 132
10.2.2 General operation...........................................................................................................................................133
10.3 Memory map/register definition...................................................................................................................................133
10.4 Functional description...................................................................................................................................................133
10.4.1 Access support............................................................................................................................................... 133
Chapter 11
Trigger MUX Control (TRGMUX)
11.1 Chip-specific information for this module....................................................................................................................135
11.1.1 Module Interconnectivity...............................................................................................................................135
11.2 Introduction...................................................................................................................................................................140
11.2.1 Features.......................................................................................................................................................... 140
11.3 Functional description...................................................................................................................................................140
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11.4 Memory map and register definition.............................................................................................................................140
11.4.1 TRGMUX1 Register Descriptions.................................................................................................................140
11.4.2 TRGMUX0 Register Descriptions.................................................................................................................145
11.5 Usage Guide..................................................................................................................................................................176
11.5.1 ADC Trigger Source...................................................................................................................................... 176
11.5.2 CMP Window/Sample Input .........................................................................................................................177
11.5.3 FTM Fault Detection Input / Hardware Triggers and Synchronization.........................................................177
Chapter 12
Direct Memory Access Multiplexer (DMAMUX)
12.1 Chip-specific information for this module....................................................................................................................179
12.1.1 DMAMUX request sources........................................................................................................................... 179
12.1.2 DMA trigger sources......................................................................................................................................181
12.2 Introduction...................................................................................................................................................................181
12.2.1 Overview........................................................................................................................................................181
12.2.2 Features.......................................................................................................................................................... 182
12.2.3 Modes of operation........................................................................................................................................ 182
12.3 External signal description............................................................................................................................................183
12.4 Memory map/register definition...................................................................................................................................183
12.4.1
12.5 Functional description...................................................................................................................................................185
12.5.1 DMA channels with periodic triggering capability........................................................................................185
12.5.2 DMA channels with no triggering capability.................................................................................................187
12.5.3 Always-enabled DMA sources...................................................................................................................... 187
12.6 Initialization/application information........................................................................................................................... 189
12.6.1 Reset...............................................................................................................................................................189
12.6.2 Enabling and configuring sources..................................................................................................................189
Channel Configuration register (DMAMUX_CHCFGn).............................................................................. 184
Chapter 13
Enhanced Direct Memory Access (eDMA)
13.1 Introduction...................................................................................................................................................................193
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13.1.1 eDMA system block diagram........................................................................................................................ 193
13.1.2 Block parts..................................................................................................................................................... 194
13.1.3 Features.......................................................................................................................................................... 195
13.2 Modes of operation.......................................................................................................................................................196
13.3 Memory map/register definition...................................................................................................................................197
13.3.1 TCD memory................................................................................................................................................. 197
13.3.2 TCD initialization.......................................................................................................................................... 197
13.3.3 TCD structure.................................................................................................................................................197
13.3.4 Reserved memory and bit fields.....................................................................................................................198
13.3.5 Control Register (DMA_CR).........................................................................................................................204
13.3.6 Error Status Register (DMA_ES).................................................................................................................. 207
13.3.7 Enable Request Register (DMA_ERQ)......................................................................................................... 209
13.3.8 Enable Error Interrupt Register (DMA_EEI).................................................................................................211
13.3.9 Clear Enable Error Interrupt Register (DMA_CEEI).................................................................................... 212
13.3.10 Set Enable Error Interrupt Register (DMA_SEEI)........................................................................................ 213
13.3.11 Clear Enable Request Register (DMA_CERQ).............................................................................................214
13.3.12 Set Enable Request Register (DMA_SERQ).................................................................................................215
13.3.13 Clear DONE Status Bit Register (DMA_CDNE)..........................................................................................216
13.3.14 Set START Bit Register (DMA_SSRT)........................................................................................................ 217
13.3.15 Clear Error Register (DMA_CERR)..............................................................................................................218
13.3.16 Clear Interrupt Request Register (DMA_CINT)........................................................................................... 219
13.3.17 Interrupt Request Register (DMA_INT)........................................................................................................220
13.3.18 Error Register (DMA_ERR).......................................................................................................................... 221
13.3.19 Hardware Request Status Register (DMA_HRS).......................................................................................... 223
13.3.20 Enable Asynchronous Request in Stop Register (DMA_EARS)...................................................................225
13.3.21
Channel n Priority Register (DMA_DCHPRIn)............................................................................................ 226
13.3.22
13.3.23
13.3.24
TCD Source Address (DMA_TCDn_SADDR).............................................................................................227
TCD Signed Source Address Offset (DMA_TCDn_SOFF)..........................................................................227
TCD Transfer Attributes (DMA_TCDn_ATTR)...........................................................................................228
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13.3.25
13.3.26 TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled)
13.3.27 TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled)
13.3.28
13.3.29
13.3.30
13.3.31 TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled)
13.3.32 TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled)
13.3.33
13.3.34
13.3.35 TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled)
TCD Minor Byte Count (Minor Loop Mapping Disabled) (DMA_TCDn_NBYTES_MLNO)................... 229
(DMA_TCDn_NBYTES_MLOFFNO).........................................................................................................229
(DMA_TCDn_NBYTES_MLOFFYES)....................................................................................................... 231
TCD Last Source Address Adjustment (DMA_TCDn_SLAST)...................................................................232
TCD Destination Address (DMA_TCDn_DADDR).....................................................................................232
TCD Signed Destination Address Offset (DMA_TCDn_DOFF)..................................................................233
(DMA_TCDn_CITER_ELINKYES).............................................................................................................233
(DMA_TCDn_CITER_ELINKNO).............................................................................................................. 235
TCD Last Destination Address Adjustment/Scatter Gather Address (DMA_TCDn_DLASTSGA)............ 236
TCD Control and Status (DMA_TCDn_CSR).............................................................................................. 236
(DMA_TCDn_BITER_ELINKYES).............................................................................................................239
13.3.36 TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled)
(DMA_TCDn_BITER_ELINKNO).............................................................................................................. 240
13.4 Functional description...................................................................................................................................................241
13.4.1 eDMA basic data flow................................................................................................................................... 241
13.4.2 Fault reporting and handling..........................................................................................................................244
13.4.3 Channel preemption....................................................................................................................................... 246
13.4.4 Performance................................................................................................................................................... 246
13.5 Initialization/application information........................................................................................................................... 251
13.5.1 eDMA initialization....................................................................................................................................... 251
13.5.2 Programming errors....................................................................................................................................... 253
13.5.3 Arbitration mode considerations....................................................................................................................253
13.5.4 Performing DMA transfers............................................................................................................................ 254
13.5.5 Monitoring transfer descriptor status............................................................................................................. 258
13.5.6 Channel Linking.............................................................................................................................................260
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13.5.7 Dynamic programming.................................................................................................................................. 261
13.5.8 Suspend/resume a DMA channel with active hardware service requests......................................................264
13.6 Usage Guide..................................................................................................................................................................266
Chapter 14
Memory and memory map
14.1 Introduction...................................................................................................................................................................267
14.2 Flash memory............................................................................................................................................................... 269
14.2.1 Flash memory types....................................................................................................................................... 269
14.2.2 Flash Memory Sizes.......................................................................................................................................269
14.3 SRAM memory.............................................................................................................................................................270
14.3.1 SRAM sizes....................................................................................................................................................270
14.3.2 SRAM retention in low power modes............................................................................................................270
14.4 System memory map.....................................................................................................................................................270
14.4.1 Aliased bit-band regions................................................................................................................................ 272
14.4.2 Bit Manipulation Engine................................................................................................................................273
14.5 Peripheral memory map................................................................................................................................................273
14.5.1 Peripheral Bridge (AIPS-Lite) Memory Map................................................................................................ 274
14.6 Private Peripheral Bus (PPB) memory map..................................................................................................................277
Chapter 15
Flash Acceleration Unit (FAU)
15.1 Flash Acceleration Unit (FAU).....................................................................................................................................279
15.1.1 Introduction....................................................................................................................................................279
15.1.2 Modes of operation........................................................................................................................................ 279
15.1.3 External signal description.............................................................................................................................279
15.1.4 Memory map and register descriptions..........................................................................................................279
15.1.5 Functional description....................................................................................................................................280
15.2 Usage Guide..................................................................................................................................................................280
15.2.1 FAU Features................................................................................................................................................. 281
15.2.2 FAU Configuration........................................................................................................................................ 281
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Chapter 16
Flash Memory Module (FTFE)
16.1 Chip-specific Information for this Module...................................................................................................................283
16.2 Introduction...................................................................................................................................................................283
16.2.1 Features.......................................................................................................................................................... 284
16.2.2 Block diagram................................................................................................................................................286
16.2.3 Glossary......................................................................................................................................................... 286
16.3 External signal description............................................................................................................................................288
16.4 Memory map and registers............................................................................................................................................289
16.4.1 Flash configuration field description............................................................................................................. 289
16.4.2 Program flash 0 IFR map...............................................................................................................................289
16.4.3 Data flash 0 IFR map..................................................................................................................................... 290
16.4.4 Register descriptions......................................................................................................................................293
16.5 Functional Description..................................................................................................................................................309
16.5.1 Flash Protection..............................................................................................................................................309
16.5.2 Flash Access Protection................................................................................................................................. 311
16.5.3 FlexNVM Description....................................................................................................................................312
16.5.4 Interrupts........................................................................................................................................................ 316
16.5.5 Flash Operation in Low-Power Modes.......................................................................................................... 317
16.5.6 Flash memory reads and ignored writes........................................................................................................ 317
16.5.7 Read while write (RWW).............................................................................................................................. 317
16.5.8 Flash Program and Erase................................................................................................................................318
16.5.9 FTFE Command Operations.......................................................................................................................... 318
16.5.10 Margin Read Commands............................................................................................................................... 325
16.5.11 Flash command descriptions..........................................................................................................................326
16.5.12 Security.......................................................................................................................................................... 351
16.6 Reset Sequence............................................................................................................................................................. 354
16.7 Usage Guide..................................................................................................................................................................355
Chapter 17
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Clock Distribution
17.1 Introduction...................................................................................................................................................................357
17.2 High-Level clocking diagram.......................................................................................................................................358
17.3 Clock definitions...........................................................................................................................................................358
17.4 Typical Clock Configuration........................................................................................................................................ 359
17.4.1 Default start-up clock.....................................................................................................................................359
17.4.2 VLPR mode clocking.....................................................................................................................................360
17.5 Clock Gating.................................................................................................................................................................360
17.6 Module clocks...............................................................................................................................................................360
17.6.1 LPO clock distribution...................................................................................................................................362
17.6.2 EWM clocks...................................................................................................................................................362
17.6.3 WDOG Clocking Information....................................................................................................................... 362
17.6.4 ADC Clocking Information........................................................................................................................... 363
17.6.5 PDB Clock Options........................................................................................................................................364
17.6.6 FTM Clocking Information............................................................................................................................364
17.6.7 LPTMR prescaler/glitch filter clocking options............................................................................................ 365
17.6.8 RTC Clocking Information............................................................................................................................ 365
17.6.9 TSI Clocking Information..............................................................................................................................366
17.6.10 Module Clocking Information for LPUART, LPSPI, LPI2C, FlexIO and LPIT...........................................366
Chapter 18
System Clock Generator (SCG)
18.1 Chip-specific information for this module....................................................................................................................369
18.1.1 Instantiation Information................................................................................................................................369
18.2 Introduction...................................................................................................................................................................372
18.2.1 Features.......................................................................................................................................................... 372
18.3 Memory Map/Register Definition.................................................................................................................................373
18.3.1 Version ID Register (SCG_VERID)..............................................................................................................374
18.3.2 Parameter Register (SCG_PARAM)............................................................................................................. 374
18.3.3 Clock Status Register (SCG_CSR)................................................................................................................375
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18.3.4 Run Clock Control Register (SCG_RCCR)...................................................................................................377
18.3.5 VLPR Clock Control Register (SCG_VCCR)...............................................................................................379
18.3.6 SCG CLKOUT Configuration Register (SCG_CLKOUTCNFG).................................................................381
18.3.7 System OSC Control Status Register (SCG_SOSCCSR)..............................................................................382
18.3.8 System OSC Divide Register (SCG_SOSCDIV).......................................................................................... 384
18.3.9 System Oscillator Configuration Register (SCG_SOSCCFG)...................................................................... 385
18.3.10 Slow IRC Control Status Register (SCG_SIRCCSR)....................................................................................387
18.3.11 Slow IRC Divide Register (SCG_SIRCDIV)................................................................................................ 388
18.3.12 Slow IRC Configuration Register (SCG_SIRCCFG)....................................................................................389
18.3.13 Fast IRC Control Status Register (SCG_FIRCCSR)..................................................................................... 390
18.3.14 Fast IRC Divide Register (SCG_FIRCDIV)..................................................................................................392
18.3.15 Fast IRC Configuration Register (SCG_FIRCCFG)..................................................................................... 393
18.3.16 Fast IRC Trim Configuration Register (SCG_FIRCTCFG)..........................................................................394
18.3.17 Fast IRC Status Register (SCG_FIRCSTAT)................................................................................................395
18.3.18 Low Power FLL Control Status Register (SCG_LPFLLCSR)......................................................................396
18.3.19 Low Power FLL Divide Register (SCG_LPFLLDIV).................................................................................. 398
18.3.20 Low Power FLL Configuration Register (SCG_LPFLLCFG)...................................................................... 399
18.3.21 Low Power FLL Trim Configuration Register (SCG_LPFLLTCFG)...........................................................400
18.3.22 Low Power FLL Status Register (SCG_LPFLLSTAT).................................................................................401
18.4 Functional description...................................................................................................................................................402
18.4.1 SCG Clock Mode Transitions........................................................................................................................402
Chapter 19
RTC Oscillator (OSC32)
19.1 Introduction...................................................................................................................................................................405
19.1.1 Features and Modes....................................................................................................................................... 405
19.1.2 Block Diagram............................................................................................................................................... 405
19.2 RTC Signal Descriptions.............................................................................................................................................. 406
19.2.1 EXTAL32 — Oscillator Input....................................................................................................................... 406
19.2.2 XTAL32 — Oscillator Output....................................................................................................................... 406
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19.3 External Crystal Connections....................................................................................................................................... 407
19.4 Memory Map/Register Descriptions.............................................................................................................................407
19.4.1 RTC Oscillator Control Register (OSC32_CR).............................................................................................407
19.5 Functional Description..................................................................................................................................................408
19.6 Reset Overview.............................................................................................................................................................409
19.7 Interrupts.......................................................................................................................................................................409
Chapter 20
Peripheral Clock Controller (PCC)
20.1 Chip-specific information for this module....................................................................................................................411
20.1.1 Information of PCC on this device................................................................................................................ 411
20.2 Introduction...................................................................................................................................................................411
20.2.1 Features.......................................................................................................................................................... 411
20.3 Functional description...................................................................................................................................................412
20.4 Memory map and register definition.............................................................................................................................413
20.4.1 PCC Register Descriptions.............................................................................................................................413
Chapter 21
Reset and Boot
21.1 Introduction...................................................................................................................................................................459
21.2 Reset..............................................................................................................................................................................460
21.2.1 Power-on reset (POR).................................................................................................................................... 460
21.2.2 System resets..................................................................................................................................................460
21.2.3 MCU Resets................................................................................................................................................... 463
21.2.4 Reset Pin ....................................................................................................................................................... 464
21.3 Boot...............................................................................................................................................................................464
21.3.1 Boot options................................................................................................................................................... 465
21.3.2 Boot sequence................................................................................................................................................ 466
Chapter 22
Kinetis ROM Bootloader
22.1 Chip-specific information for this module....................................................................................................................469
22.1.1 Boot ROM Configuration.............................................................................................................................. 469
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22.2 Introduction...................................................................................................................................................................470
22.3 Functional Description..................................................................................................................................................471
22.3.1 Memory Maps................................................................................................................................................471
22.3.2 The Kinetis Bootloader Configuration Area (BCA)......................................................................................472
22.3.3 Start-up Process..............................................................................................................................................474
22.3.4 Clock Configuration.......................................................................................................................................476
22.3.5 Bootloader Entry Point / API Tree.................................................................................................................477
22.3.6 Bootloader Protocol....................................................................................................................................... 478
22.3.7 Bootloader Packet Types............................................................................................................................... 481
22.3.8 Bootloader Command API.............................................................................................................................487
22.3.9 Bootloader Exit state......................................................................................................................................500
22.4 Kinetis Flash Driver API.............................................................................................................................................. 500
22.4.1 Flash Driver Entry Point................................................................................................................................ 500
22.4.2 Flash driver API Tree.....................................................................................................................................501
22.4.3 Quick demo using Kinetis Flash Driver API................................................................................................. 502
22.4.4 Flash driver data structures............................................................................................................................ 503
22.4.5 Flash driver API.............................................................................................................................................504
22.5 Peripherals Supported...................................................................................................................................................518
22.5.1 I2C Peripheral................................................................................................................................................ 518
22.5.2 SPI Peripheral................................................................................................................................................ 520
22.5.3 UART Peripheral........................................................................................................................................... 523
22.6 Get/SetProperty Command Properties..........................................................................................................................525
22.6.1 Property Definitions.......................................................................................................................................527
22.7 Kinetis Bootloader Status Error Codes.........................................................................................................................528
Chapter 23
Reset Control Module (RCM)
23.1 Chip-specific information for this module....................................................................................................................531
23.1.1 Instantiation Information................................................................................................................................531
23.2 Introduction...................................................................................................................................................................531
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23.3 Reset memory map and register descriptions............................................................................................................... 532
23.3.1 Version ID Register (RCM_VERID).............................................................................................................532
23.3.2 Parameter Register (RCM_PARAM)............................................................................................................ 534
23.3.3 System Reset Status Register (RCM_SRS)................................................................................................... 536
23.3.4 Reset Pin Control register (RCM_RPC)........................................................................................................ 539
23.3.5 Mode Register (RCM_MR)........................................................................................................................... 540
23.3.6 Force Mode Register (RCM_FM)..................................................................................................................541
23.3.7 Sticky System Reset Status Register (RCM_SSRS)......................................................................................542
23.3.8 System Reset Interrupt Enable Register (RCM_SRIE)................................................................................. 544
Chapter 24
Power Management
24.1 Introduction...................................................................................................................................................................547
24.2 Power Modes Description.............................................................................................................................................548
24.2.1 Run mode....................................................................................................................................................... 549
24.2.2 Wait mode......................................................................................................................................................550
24.2.3 Stop mode...................................................................................................................................................... 551
24.2.4 Power domains...............................................................................................................................................553
24.2.5 Entering and exiting power modes.................................................................................................................554
24.3 Power mode transitions.................................................................................................................................................554
24.4 Power modes shutdown sequencing............................................................................................................................. 555
24.5 Module operation in low power modes........................................................................................................................ 556
24.5.1 Peripheral doze...............................................................................................................................................559
24.6 Low-power wake-up sources........................................................................................................................................560
24.7 Power supply supervisor...............................................................................................................................................560
Chapter 25
System Mode Controller (SMC)
25.1 Introduction...................................................................................................................................................................563
25.2 Modes of operation.......................................................................................................................................................563
25.3 Memory map and register descriptions.........................................................................................................................565
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25.3.1 SMC Version ID Register (SMC_VERID)....................................................................................................565
25.3.2 SMC Parameter Register (SMC_PARAM)................................................................................................... 566
25.3.3 Power Mode Protection register (SMC_PMPROT).......................................................................................567
25.3.4 Power Mode Control register (SMC_PMCTRL)...........................................................................................569
25.3.5 Stop Control Register (SMC_STOPCTRL)...................................................................................................570
25.3.6 Power Mode Status register (SMC_PMSTAT)............................................................................................. 572
25.4 Functional description...................................................................................................................................................572
25.4.1 Power mode transitions..................................................................................................................................572
25.4.2 Power mode entry/exit sequencing................................................................................................................ 574
25.4.3 Run modes......................................................................................................................................................576
25.4.4 Wait modes.................................................................................................................................................... 578
25.4.5 Stop modes.....................................................................................................................................................579
25.4.6 Debug in low power modes........................................................................................................................... 580
Chapter 26
Power Management Controller (PMC)
26.1 Chip-specific Information for this Module...................................................................................................................581
26.2 Introduction...................................................................................................................................................................581
26.3 Features.........................................................................................................................................................................581
26.4 Modes of Operation...................................................................................................................................................... 581
26.4.1 Full Performance Mode (FPM)......................................................................................................................581
26.4.2 Low Power Mode (LPM)...............................................................................................................................582
26.5 Low Voltage Detect (LVD) System............................................................................................................................. 582
26.5.1 Low Voltage Reset (LVR) Operation............................................................................................................ 582
26.5.2 LVD Interrupt Operation............................................................................................................................... 583
26.5.3 Low-voltage warning (LVW) interrupt operation......................................................................................... 583
26.6 Memory Map and Register Definition..........................................................................................................................583
26.6.1 Low Voltage Detect Status and Control 1 Register (PMC_LVDSC1)..........................................................584
26.6.2 Low Voltage Detect Status and Control 2 Register (PMC_LVDSC2)..........................................................585
26.6.3 Regulator Status and Control Register (PMC_REGSC)................................................................................586
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26.6.4 Low Power Oscillator Trim Register (PMC_LPOTRIM)............................................................................. 587
Chapter 27
Security
27.1 Introduction...................................................................................................................................................................589
27.2 Flash security feature summary....................................................................................................................................589
27.2.1 Flash security byte......................................................................................................................................... 589
27.2.2 Flash access protection (FAC)....................................................................................................................... 590
27.3 Security hardware accelerators.....................................................................................................................................590
27.3.1 CRC................................................................................................................................................................590
27.4 General security features...............................................................................................................................................591
27.4.1 Unique ID.......................................................................................................................................................591
27.4.2 Program Once Field....................................................................................................................................... 591
Chapter 28
External Watchdog Monitor (EWM)
28.1 Introduction...................................................................................................................................................................593
28.1.1 Features.......................................................................................................................................................... 593
28.1.2 Modes of Operation....................................................................................................................................... 594
28.1.3 Block Diagram............................................................................................................................................... 595
28.2 EWM Signal Descriptions............................................................................................................................................ 596
28.3 Memory Map/Register Definition.................................................................................................................................596
28.3.1 Control Register (EWM_CTRL)................................................................................................................... 596
28.3.2 Service Register (EWM_SERV)....................................................................................................................597
28.3.3 Compare Low Register (EWM_CMPL)........................................................................................................597
28.3.4 Compare High Register (EWM_CMPH).......................................................................................................598
28.3.5 Clock Prescaler Register (EWM_CLKPRESCALER)..................................................................................599
28.4 Functional Description..................................................................................................................................................599
28.4.1 The EWM_out Signal.................................................................................................................................... 599
28.4.2 The EWM_in Signal...................................................................................................................................... 600
28.4.3 EWM Counter................................................................................................................................................601
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28.4.4 EWM Compare Registers.............................................................................................................................. 601
28.4.5 EWM Refresh Mechanism.............................................................................................................................601
28.4.6 EWM Interrupt...............................................................................................................................................602
28.4.7 Counter clock prescaler..................................................................................................................................602
28.5 Usage Guide..................................................................................................................................................................602
28.5.1 EWM low-power modes................................................................................................................................ 602
28.5.2 EWM_out pin state in low power modes.......................................................................................................603
28.5.3 Example code.................................................................................................................................................603
Chapter 29
Watchdog timer (WDOG)
29.1 Chip-specific information for this module....................................................................................................................605
29.1.1 WDOG Clocking Information....................................................................................................................... 605
29.1.2 WDOG low-power modes............................................................................................................................. 605
29.2 Introduction...................................................................................................................................................................606
29.2.1 Features.......................................................................................................................................................... 606
29.2.2 Block diagram................................................................................................................................................607
29.3 Memory map and register definition.............................................................................................................................607
29.3.1 Watchdog Control and Status Register (WDOG_CS)................................................................................... 608
29.3.2 Watchdog Counter Register (WDOG_CNT).................................................................................................611
29.3.3 Watchdog Timeout Value Register (WDOG_TOVAL)................................................................................ 611
29.3.4 Watchdog Window Register (WDOG_WIN)................................................................................................612
29.4 Functional description...................................................................................................................................................613
29.4.1 Clock source...................................................................................................................................................613
29.4.2 Watchdog refresh mechanism........................................................................................................................614
29.4.3 Configuring the Watchdog.............................................................................................................................616
29.4.4 Using interrupts to delay resets......................................................................................................................617
29.4.5 Backup reset...................................................................................................................................................617
29.4.6 Functionality in debug and low-power modes...............................................................................................618
29.4.7 Fast testing of the watchdog...........................................................................................................................618
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29.5 Application Information................................................................................................................................................619
29.5.1 Disable Watchdog..........................................................................................................................................620
29.5.2 Configure Watchdog......................................................................................................................................620
29.5.3 Refreshing the Watchdog...............................................................................................................................621
Chapter 30
Cyclic Redundancy Check (CRC)
30.1 Introduction...................................................................................................................................................................623
30.1.1 Features.......................................................................................................................................................... 623
30.1.2 Block diagram................................................................................................................................................623
30.1.3 Modes of operation........................................................................................................................................ 624
30.2 Memory map and register descriptions.........................................................................................................................624
30.2.1 CRC Data register (CRC_DATA)................................................................................................................. 625
30.2.2 CRC Polynomial register (CRC_GPOLY).................................................................................................... 626
30.2.3 CRC Control register (CRC_CTRL)..............................................................................................................626
30.3 Functional description...................................................................................................................................................627
30.3.1 CRC initialization/reinitialization..................................................................................................................627
30.3.2 CRC calculations............................................................................................................................................628
30.3.3 Transpose feature........................................................................................................................................... 629
30.3.4 CRC result complement.................................................................................................................................631
30.4 Usage Guide..................................................................................................................................................................631
30.4.1 32-bit POSIX CRC.........................................................................................................................................632
30.4.2 16-bit KERMIT CRC.....................................................................................................................................633
Chapter 31
Debug
31.1 Introduction...................................................................................................................................................................635
31.2 Debug port pin descriptions..........................................................................................................................................635
31.3 SWD status and control registers..................................................................................................................................635
31.3.1 MDM-AP status register................................................................................................................................ 637
31.3.2 MDM-AP Control register.............................................................................................................................638
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31.4 Debug resets..................................................................................................................................................................639
31.5 Micro Trace Buffer (MTB)...........................................................................................................................................639
31.6 Debug in low-power modes..........................................................................................................................................640
31.7 Debug and security....................................................................................................................................................... 640
Chapter 32
Micro Trace Buffer (MTB)
32.1 Introduction...................................................................................................................................................................641
32.1.1 Overview........................................................................................................................................................641
32.1.2 Features.......................................................................................................................................................... 644
32.1.3 Modes of operation........................................................................................................................................ 645
32.2 External signal description............................................................................................................................................645
32.3 Memory map and register definition.............................................................................................................................646
32.3.1 MTB_RAM Memory Map.............................................................................................................................646
32.3.2 MTB_DWT Memory Map.............................................................................................................................658
32.3.3 System ROM Memory Map...........................................................................................................................668
32.4 Usage Guide..................................................................................................................................................................672
32.4.1 ARM reference...............................................................................................................................................672
Chapter 33
Signal Multiplexing and Pin Assignment
33.1 Introduction...................................................................................................................................................................675
33.2 Pinouts.......................................................................................................................................................................... 675
33.2.1 KE1xZ Signal Multiplexing and Pin Assignments........................................................................................675
33.2.2 Pin properties................................................................................................................................................. 679
33.2.3 Pinout diagram............................................................................................................................................... 682
33.3 Module Signal Description Tables................................................................................................................................684
33.3.1 Core Modules.................................................................................................................................................684
33.3.2 System Modules.............................................................................................................................................685
33.3.3 Clock Modules............................................................................................................................................... 685
33.3.4 Analog............................................................................................................................................................686
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33.3.5 Timer Modules...............................................................................................................................................686
33.3.6 Communication Interfaces............................................................................................................................. 687
33.3.7 Human-Machine Interfaces (HMI)................................................................................................................ 688
Chapter 34
Port Control and Interrupts (PORT)
34.1 Chip-specific information for this module....................................................................................................................691
34.1.1 I/O pin structure............................................................................................................................................. 691
34.1.2 Port control and interrupt module features.................................................................................................... 692
34.1.3 Application-related Information.................................................................................................................... 692
34.2 Introduction...................................................................................................................................................................693
34.3 Overview.......................................................................................................................................................................693
34.3.1 Features.......................................................................................................................................................... 693
34.3.2 Modes of operation........................................................................................................................................ 694
34.4 External signal description............................................................................................................................................695
34.5 Detailed signal description............................................................................................................................................695
34.6 Memory map and register definition.............................................................................................................................695
34.6.1
34.6.2
34.6.3
34.6.4
34.6.5
34.6.6
34.6.7
34.7 Functional description...................................................................................................................................................708
34.7.1 Pin control......................................................................................................................................................708
34.7.2 Global pin control.......................................................................................................................................... 709
34.7.3 External interrupts..........................................................................................................................................709
Pin Control Register n (PORTx_PCRn).........................................................................................................702
Global Pin Control Low Register (PORTx_GPCLR)....................................................................................705
Global Pin Control High Register (PORTx_GPCHR)...................................................................................705
Interrupt Status Flag Register (PORTx_ISFR).............................................................................................. 706
Digital Filter Enable Register (PORTx_DFER).............................................................................................706
Digital Filter Clock Register (PORTx_DFCR)..............................................................................................707
Digital Filter Width Register (PORTx_DFWR)............................................................................................ 707
34.7.4 Digital filter....................................................................................................................................................710
Chapter 35
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General-Purpose Input/Output (GPIO)
35.1 Chip-specific information for this module....................................................................................................................713
35.1.1 Instantiation Information................................................................................................................................713
35.1.2 GPIO accessibility in the memory map......................................................................................................... 713
35.2 Introduction...................................................................................................................................................................713
35.2.1 Features.......................................................................................................................................................... 714
35.2.2 Modes of operation........................................................................................................................................ 714
35.2.3 GPIO signal descriptions............................................................................................................................... 714
35.3 Memory map and register definition.............................................................................................................................715
35.3.1
35.3.2
35.3.3
35.3.4
35.3.5
35.3.6
35.4 FGPIO memory map and register definition................................................................................................................ 720
35.4.1
35.4.2
35.4.3
35.4.4
35.4.5
35.4.6
35.5 Functional description...................................................................................................................................................725
Port Data Output Register (GPIOx_PDOR)...................................................................................................717
Port Set Output Register (GPIOx_PSOR)......................................................................................................718
Port Clear Output Register (GPIOx_PCOR)..................................................................................................718
Port Toggle Output Register (GPIOx_PTOR)............................................................................................... 719
Port Data Input Register (GPIOx_PDIR).......................................................................................................719
Port Data Direction Register (GPIOx_PDDR)...............................................................................................720
Port Data Output Register (FGPIOx_PDOR)................................................................................................ 722
Port Set Output Register (FGPIOx_PSOR)................................................................................................... 722
Port Clear Output Register (FGPIOx_PCOR)............................................................................................... 723
Port Toggle Output Register (FGPIOx_PTOR).............................................................................................723
Port Data Input Register (FGPIOx_PDIR).....................................................................................................724
Port Data Direction Register (FGPIOx_PDDR)............................................................................................ 724
35.5.1 General-purpose input....................................................................................................................................725
35.5.2 General-purpose output..................................................................................................................................725
35.5.3 IOPORT......................................................................................................................................................... 725
Chapter 36
Analog-to-Digital Converter (ADC)
36.1 Chip-specific information for this module....................................................................................................................727
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36.1.1 Instantiation information................................................................................................................................727
36.1.2 ADC Clocking Information........................................................................................................................... 729
36.1.3 Inter-connectivity Information.......................................................................................................................730
36.1.4 Application-related Information.................................................................................................................... 731
36.2 Introduction...................................................................................................................................................................736
36.2.1 Features.......................................................................................................................................................... 736
36.2.2 Block diagram................................................................................................................................................737
36.3 ADC signal descriptions...............................................................................................................................................738
36.3.1 Analog Power (VDDA)................................................................................................................................. 739
36.3.2 Analog Ground (VSSA).................................................................................................................................739
36.3.3 Voltage Reference Select...............................................................................................................................739
36.3.4 Analog Channel Inputs (ADx)....................................................................................................................... 740
36.4 Memory map and register definitions...........................................................................................................................740
36.4.1
36.4.2
36.4.3
36.4.4
36.4.5
36.4.6
36.4.7
36.4.8
36.4.9
36.4.10
36.4.11
36.4.12
36.4.13
ADC Status and Control Register 1 (ADCx_SC1n)...................................................................................... 742
ADC Configuration Register 1 (ADCx_CFG1).............................................................................................745
ADC Configuration Register 2 (ADCx_CFG2).............................................................................................746
ADC Data Result Registers (ADCx_Rn).......................................................................................................747
Compare Value Registers (ADCx_CVn)....................................................................................................... 748
Status and Control Register 2 (ADCx_SC2)..................................................................................................749
Status and Control Register 3 (ADCx_SC3)..................................................................................................751
BASE Offset Register (ADCx_BASE_OFS).................................................................................................752
ADC Offset Correction Register (ADCx_OFS).............................................................................................752
USER Offset Correction Register (ADCx_USR_OFS).................................................................................753
ADC X Offset Correction Register (ADCx_XOFS)......................................................................................754
ADC Y Offset Correction Register (ADCx_YOFS)......................................................................................754
ADC Gain Register (ADCx_G)..................................................................................................................... 754
36.4.14
36.4.15
36.4.16
ADC User Gain Register (ADCx_UG)..........................................................................................................755
ADC General Calibration Value Register S (ADCx_CLPS).........................................................................755
ADC Plus-Side General Calibration Value Register 3 (ADCx_CLP3)......................................................... 756
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36.4.17
36.4.18
36.4.19
36.4.20
36.4.21
36.4.22
36.4.23
36.4.24
36.4.25
36.4.26
36.4.27
36.4.28
36.5 Functional description...................................................................................................................................................763
36.5.1 Clock select and divide control......................................................................................................................763
ADC Plus-Side General Calibration Value Register 2 (ADCx_CLP2)......................................................... 757
ADC Plus-Side General Calibration Value Register 1 (ADCx_CLP1)......................................................... 757
ADC Plus-Side General Calibration Value Register 0 (ADCx_CLP0)......................................................... 758
ADC Plus-Side General Calibration Value Register X (ADCx_CLPX)....................................................... 758
ADC Plus-Side General Calibration Value Register 9 (ADCx_CLP9)......................................................... 759
ADC General Calibration Offset Value Register S (ADCx_CLPS_OFS).....................................................760
ADC Plus-Side General Calibration Offset Value Register 3 (ADCx_CLP3_OFS).....................................760
ADC Plus-Side General Calibration Offset Value Register 2 (ADCx_CLP2_OFS).....................................761
ADC Plus-Side General Calibration Offset Value Register 1 (ADCx_CLP1_OFS).....................................761
ADC Plus-Side General Calibration Offset Value Register 0 (ADCx_CLP0_OFS).....................................761
ADC Plus-Side General Calibration Offset Value Register X (ADCx_CLPX_OFS)...................................762
ADC Plus-Side General Calibration Offset Value Register 9 (ADCx_CLP9_OFS).....................................762
36.5.2 Voltage reference selection............................................................................................................................764
36.5.3 Hardware trigger and channel selects............................................................................................................ 764
36.5.4 Conversion control.........................................................................................................................................765
36.5.5 Automatic compare function..........................................................................................................................769
36.5.6 Calibration function....................................................................................................................................... 770
36.5.7 User-defined offset function.......................................................................................................................... 771
36.5.8 MCU wait mode operation.............................................................................................................................772
36.5.9 MCU Normal Stop mode operation...............................................................................................................773
36.6 Usage Guide..................................................................................................................................................................773
36.6.1 ADC module initialization sequence............................................................................................................. 773
36.6.2 Pseudo-code example.....................................................................................................................................774
36.6.3 Calibration......................................................................................................................................................775
36.6.4 Application hints............................................................................................................................................776
36.6.5 DMA Support on ADC.................................................................................................................................. 776
36.6.6 ADC low-power modes................................................................................................................................. 776
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36.6.7 ADC Trigger Concept – Use Case.................................................................................................................777
36.6.8 ADC self-test and calibration scheme............................................................................................................778
Chapter 37
Comparator (CMP)
37.1 Chip-specific information for this module....................................................................................................................779
37.1.1 Instantiation information................................................................................................................................779
37.1.2 CMP Clocking Information........................................................................................................................... 780
37.1.3 Inter-connectivity Information.......................................................................................................................781
37.1.4 Application-related Information.................................................................................................................... 782
37.2 Introduction...................................................................................................................................................................784
37.3 Features.........................................................................................................................................................................784
37.3.1 CMP features..................................................................................................................................................784
37.3.2 8-bit DAC key features.................................................................................................................................. 785
37.3.3 ANMUX key features.................................................................................................................................... 785
37.4 CMP, DAC, and ANMUX diagram..............................................................................................................................786
37.5 CMP block diagram......................................................................................................................................................787
37.6 CMP pin descriptions....................................................................................................................................................788
37.6.1 External pins.................................................................................................................................................. 788
37.7 CMP functional modes................................................................................................................................................. 789
37.7.1 Disabled mode (# 1).......................................................................................................................................791
37.7.2 Continuous mode (#s 2A & 2B).................................................................................................................... 791
37.7.3 Sampled, Non-Filtered mode (#s 3A & 3B).................................................................................................. 792
37.7.4 Sampled, Filtered mode (#s 4A & 4B).......................................................................................................... 793
37.7.5 Windowed mode (#s 5A & 5B)..................................................................................................................... 795
37.7.6 Windowed/Resampled mode (# 6).................................................................................................................797
37.7.7 Windowed/Filtered mode (#7).......................................................................................................................798
37.8 Memory map/register definitions..................................................................................................................................799
37.8.1
37.8.2
CMP Control Register 0 (CMPx_C0)............................................................................................................ 799
CMP Control Register 1 (CMPx_C1)............................................................................................................ 803
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37.8.3
37.9 CMP functional description..........................................................................................................................................808
37.9.1 Initialization................................................................................................................................................... 809
37.9.2 Low-pass filter............................................................................................................................................... 809
37.10 Interrupts.......................................................................................................................................................................811
37.11 DMA support................................................................................................................................................................812
37.12 DAC functional description..........................................................................................................................................812
37.12.1 Digital-to-analog converter block diagram....................................................................................................812
37.12.2 DAC resets..................................................................................................................................................... 813
37.12.3 DAC clocks....................................................................................................................................................813
37.12.4 DAC interrupts...............................................................................................................................................813
37.13 Trigger mode.................................................................................................................................................................813
37.14 Usage Guide..................................................................................................................................................................816
37.14.1 Zero Crossing Detection................................................................................................................................ 816
CMP Control Register 2 (CMPx_C2)............................................................................................................ 806
37.14.2 Window Mode................................................................................................................................................817
37.14.3 Round Robin Mode........................................................................................................................................817
Chapter 38
Programmable Delay Block (PDB)
38.1 Chip-specific Information for this Module...................................................................................................................821
38.1.1 Instantiation Information................................................................................................................................821
38.1.2 PDB Clocking Information............................................................................................................................ 821
38.1.3 Inter-connectivity Information.......................................................................................................................822
38.2 Introduction...................................................................................................................................................................824
38.2.1 Features.......................................................................................................................................................... 824
38.2.2 Implementation.............................................................................................................................................. 825
38.2.3 Back-to-back acknowledgment connections..................................................................................................825
38.2.4 Block diagram................................................................................................................................................825
38.2.5 Modes of operation........................................................................................................................................ 827
38.3 PDB signal descriptions................................................................................................................................................827
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38.4 Memory map and register definition.............................................................................................................................827
38.4.1
38.4.2
38.4.3
38.4.4
38.4.5
38.4.6
38.4.7
38.4.8
38.4.9
38.4.10
38.5 Functional description...................................................................................................................................................837
38.5.1 PDB pre-trigger and trigger outputs...............................................................................................................837
38.5.2 PDB trigger input source selection................................................................................................................ 839
38.5.3 Pulse-Out's..................................................................................................................................................... 840
Status and Control register (PDBx_SC).........................................................................................................829
Modulus register (PDBx_MOD)....................................................................................................................832
Counter register (PDBx_CNT).......................................................................................................................832
Interrupt Delay register (PDBx_IDLY)......................................................................................................... 833
Channel n Control register 1 (PDBx_CHnC1)...............................................................................................833
Channel n Status register (PDBx_CHnS).......................................................................................................834
Channel n Delay 0 register (PDBx_CHnDLY0)............................................................................................835
Channel n Delay 1 register (PDBx_CHnDLY1)............................................................................................836
Pulse-Out n Enable register (PDBx_POEN)..................................................................................................836
Pulse-Out n Delay register (PDBx_POnDLY)...............................................................................................837
38.5.4 Updating the delay registers...........................................................................................................................841
38.5.5 Interrupts........................................................................................................................................................ 843
38.5.6 DMA.............................................................................................................................................................. 843
38.6 Application information................................................................................................................................................843
38.6.1 Impact of using the prescaler and multiplication factor on timing resolution............................................... 843
38.7 Usage Guide..................................................................................................................................................................844
38.7.1 Using PDB to precisely control ADC conversion......................................................................................... 844
Chapter 39
FlexTimer Module (FTM)
39.1 Chip-specific information for this module....................................................................................................................845
39.1.1 Instantiation Information................................................................................................................................845
39.1.2 FTM Clocking Information............................................................................................................................845
39.1.3 Inter-connectivity Information.......................................................................................................................846
39.2 Introduction...................................................................................................................................................................850
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39.2.1 FlexTimer philosophy....................................................................................................................................850
39.2.2 Features.......................................................................................................................................................... 851
39.2.3 Modes of operation........................................................................................................................................ 853
39.2.4 Block Diagram............................................................................................................................................... 853
39.3 FTM signal descriptions............................................................................................................................................... 855
39.4 Memory map and register definition.............................................................................................................................855
39.4.1 Memory map..................................................................................................................................................855
39.4.2 Register descriptions......................................................................................................................................856
39.4.3
39.4.4
39.4.5
39.4.6
39.4.7
39.4.8
39.4.9
39.4.10
39.4.11
39.4.12
39.4.13
39.4.14
39.4.15
39.4.16
Status And Control (FTMx_SC).................................................................................................................... 862
Counter (FTMx_CNT)................................................................................................................................... 865
Modulo (FTMx_MOD)..................................................................................................................................865
Channel (n) Status And Control (FTMx_CnSC)............................................................................................867
Channel (n) Value (FTMx_CnV)...................................................................................................................869
Counter Initial Value (FTMx_CNTIN)..........................................................................................................869
Capture And Compare Status (FTMx_STATUS)..........................................................................................870
Features Mode Selection (FTMx_MODE).................................................................................................... 872
Synchronization (FTMx_SYNC)................................................................................................................... 874
Initial State For Channels Output (FTMx_OUTINIT)...................................................................................876
Output Mask (FTMx_OUTMASK)............................................................................................................... 878
Function For Linked Channels (FTMx_COMBINE).....................................................................................880
Deadtime Configuration (FTMx_DEADTIME)............................................................................................ 884
FTM External Trigger (FTMx_EXTTRIG)................................................................................................... 885
39.4.17
39.4.18
39.4.19
39.4.20
39.4.21
39.4.22
39.4.23
NXP Semiconductors 29
Channels Polarity (FTMx_POL)....................................................................................................................887
Fault Mode Status (FTMx_FMS)...................................................................................................................890
Input Capture Filter Control (FTMx_FILTER)............................................................................................. 892
Fault Control (FTMx_FLTCTRL)................................................................................................................. 893
Quadrature Decoder Control And Status (FTMx_QDCTRL)........................................................................896
Configuration (FTMx_CONF).......................................................................................................................898
FTM Fault Input Polarity (FTMx_FLTPOL).................................................................................................899
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39.4.24
39.4.25
39.4.26
39.4.27
39.4.28
39.4.29
39.4.30
39.5 Functional description...................................................................................................................................................909
39.5.1 Clock source...................................................................................................................................................910
39.5.2 Prescaler.........................................................................................................................................................911
39.5.3 Counter...........................................................................................................................................................911
39.5.4 Channel Modes.............................................................................................................................................. 917
39.5.5 Input Capture mode........................................................................................................................................919
39.5.6 Output Compare mode...................................................................................................................................922
Synchronization Configuration (FTMx_SYNCONF)....................................................................................900
FTM Inverting Control (FTMx_INVCTRL)..................................................................................................902
FTM Software Output Control (FTMx_SWOCTRL)....................................................................................903
FTM PWM Load (FTMx_PWMLOAD)....................................................................................................... 906
Half Cycle Register (FTMx_HCR)................................................................................................................908
Mirror of Modulo Value (FTMx_MOD_MIRROR)......................................................................................908
Mirror of Channel (n) Match Value (FTMx_CnV_MIRROR)......................................................................909
39.5.7 Edge-Aligned PWM (EPWM) mode............................................................................................................. 924
39.5.8 Center-Aligned PWM (CPWM) mode.......................................................................................................... 925
39.5.9 Combine mode............................................................................................................................................... 927
39.5.10 Complementary Mode....................................................................................................................................935
39.5.11 Registers updated from write buffers.............................................................................................................936
39.5.12 PWM synchronization....................................................................................................................................938
39.5.13 Inverting.........................................................................................................................................................954
39.5.14 Software Output Control Mode......................................................................................................................955
39.5.15 Deadtime insertion......................................................................................................................................... 957
39.5.16 Output mask................................................................................................................................................... 960
39.5.17 Fault control................................................................................................................................................... 960
39.5.18 Polarity Control..............................................................................................................................................964
39.5.19 Initialization................................................................................................................................................... 965
39.5.20 Features priority............................................................................................................................................. 965
39.5.21 External Trigger............................................................................................................................................. 966
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39.5.22 Channel trigger output................................................................................................................................... 967
39.5.23 Initialization trigger........................................................................................................................................968
39.5.24 Capture Test Mode.........................................................................................................................................971
39.5.25 DMA.............................................................................................................................................................. 972
39.5.26 Dual Edge Capture mode............................................................................................................................... 973
39.5.27 Quadrature Decoder mode............................................................................................................................. 980
39.5.28 Debug mode................................................................................................................................................... 985
39.5.29 Reload Points................................................................................................................................................. 986
39.5.30 Global Load....................................................................................................................................................989
39.5.31 Global time base (GTB).................................................................................................................................990
39.5.32 Output Logic.................................................................................................................................................. 991
39.5.33 Dithering........................................................................................................................................................ 992
39.6 Reset overview..............................................................................................................................................................1001
39.7 FTM Interrupts..............................................................................................................................................................1003
39.7.1 Timer Overflow Interrupt...............................................................................................................................1003
39.7.2 Reload Point Interrupt....................................................................................................................................1003
39.7.3 Channel (n) Interrupt......................................................................................................................................1003
39.7.4 Fault Interrupt................................................................................................................................................ 1003
39.8 Initialization Procedure.................................................................................................................................................1004
39.9 Usage Guide..................................................................................................................................................................1005
39.9.1 FTM Interrupts...............................................................................................................................................1005
39.9.2 FTM Hall sensor support............................................................................................................................... 1005
39.9.3 FTM Modulation Implementation................................................................................................................. 1006
39.9.4 FTM Global Time Base................................................................................................................................. 1007
39.9.5 FTM BDM and debug halt mode...................................................................................................................1008
Chapter 40
Low-power Periodic Interrupt Timer (LPIT)
40.1 Chip-specific Information for this Module...................................................................................................................1009
40.1.1 Instantiation Information................................................................................................................................1009
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40.1.2 LPIT Clocking Information........................................................................................................................... 1009
40.1.3 Inter-connectivity Information.......................................................................................................................1009
40.2 Introduction...................................................................................................................................................................1010
40.2.1 Overview........................................................................................................................................................1010
40.2.2 Block Diagram............................................................................................................................................... 1011
40.3 Modes of operation.......................................................................................................................................................1012
40.4 Memory Map and Registers..........................................................................................................................................1013
40.4.1
40.4.2
40.4.3
40.4.4
40.4.5
40.4.6
40.4.7
40.4.8
40.4.9
40.4.10
40.5 Functional description...................................................................................................................................................1023
40.5.1 Initialization................................................................................................................................................... 1023
40.5.2 Timer Modes..................................................................................................................................................1024
40.5.3 Trigger Control for Timers............................................................................................................................ 1025
Version ID Register (LPITx_VERID)........................................................................................................... 1014
Parameter Register (LPITx_PARAM)...........................................................................................................1014
Module Control Register (LPITx_MCR).......................................................................................................1015
Module Status Register (LPITx_MSR)..........................................................................................................1016
Module Interrupt Enable Register (LPITx_MIER)........................................................................................1017
Set Timer Enable Register (LPITx_SETTEN)...............................................................................................1018
Clear Timer Enable Register (LPITx_CLRTEN).......................................................................................... 1019
Timer Value Register (LPITx_TVALn)........................................................................................................ 1020
Current Timer Value (LPITx_CVALn)......................................................................................................... 1021
Timer Control Register (LPITx_TCTRLn)....................................................................................................1022
40.5.4 Channel Chaining...........................................................................................................................................1026
40.6 Usage Guide..................................................................................................................................................................1026
40.6.1 Periodic timer/counter....................................................................................................................................1026
40.6.2 LPIT/ADC Trigger.........................................................................................................................................1027
Chapter 41
Pulse Width Timer (PWT)
41.1 Chip-specific information for this module....................................................................................................................1031
41.1.1 Instantiation Information................................................................................................................................1031
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41.1.2 PWT Clocking Information........................................................................................................................... 1031
41.1.3 Inter-connectivity Information.......................................................................................................................1032
41.2 Introduction...................................................................................................................................................................1033
41.2.1 Features.......................................................................................................................................................... 1033
41.2.2 Modes of operation........................................................................................................................................ 1034
41.2.3 Block diagram................................................................................................................................................1034
41.3 External signal description............................................................................................................................................1035
41.3.1 Overview........................................................................................................................................................1035
41.3.2 PWTIN[3:0] — pulse width timer capture inputs..........................................................................................1036
41.3.3 ALTCLK— alternative clock source for counter.......................................................................................... 1036
41.4 Memory Map and Register Descriptions......................................................................................................................1036
41.4.1 Pulse Width Timer Control and Status Register (PWT_CS)......................................................................... 1037
41.4.2 Pulse Width Timer Control Register (PWT_CR).......................................................................................... 1038
41.4.3 Pulse Width Timer Positive Pulse Width Register: High (PWT_PPH).........................................................1039
41.4.4 Pulse Width Timer Positive Pulse Width Register: Loq (PWT_PPL)...........................................................1039
41.4.5 Pulse Width Timer Negative Pulse Width Register: High (PWT_NPH).......................................................1040
41.4.6 Pulse Width Timer Negative Pulse Width Register: Low (PWT_NPL)........................................................1040
41.4.7 Pulse Width Timer Counter Register: High (PWT_CNTH)..........................................................................1041
41.4.8 Pulse Width Timer Counter Register: Low (PWT_CNTL)...........................................................................1041
41.5 Functional description...................................................................................................................................................1041
41.5.1 PWT counter and PWT clock pre-scaler........................................................................................................1041
41.5.2 Edge detection and capture control................................................................................................................1042
41.6 Reset overview..............................................................................................................................................................1046
41.6.1 Description of reset operation........................................................................................................................1046
41.7 Interrupts.......................................................................................................................................................................1047
41.7.1 Description of interrupt operation..................................................................................................................1047
41.7.2 Application examples.....................................................................................................................................1048
41.8 Initialization/Application information..........................................................................................................................1049
41.9 Usage Guide..................................................................................................................................................................1050
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41.9.1 Edge detection, capture control and period measurement............................................................................. 1050
Chapter 42
Low Power Timer (LPTMR)
42.1 Chip-specific information for this module....................................................................................................................1053
42.1.1 Instantiation Information................................................................................................................................1053
42.1.2 LPTMR Clocking Information.......................................................................................................................1053
42.1.3 Inter-connectivity Information.......................................................................................................................1054
42.2 Introduction...................................................................................................................................................................1055
42.2.1 Features.......................................................................................................................................................... 1055
42.2.2 Modes of operation........................................................................................................................................ 1055
42.3 LPTMR signal descriptions.......................................................................................................................................... 1056
42.3.1 Detailed signal descriptions........................................................................................................................... 1056
42.4 Memory map and register definition.............................................................................................................................1056
42.4.1
42.4.2
42.4.3
42.4.4
42.5 Functional description...................................................................................................................................................1060
42.5.1 LPTMR power and reset................................................................................................................................1061
42.5.2 LPTMR clocking............................................................................................................................................1061
42.5.3 LPTMR prescaler/glitch filter........................................................................................................................1061
42.5.4 LPTMR compare............................................................................................................................................1063
42.5.5 LPTMR counter............................................................................................................................................. 1063
42.5.6 LPTMR hardware trigger...............................................................................................................................1064
42.5.7 LPTMR interrupt............................................................................................................................................1064
42.6 Usage Guide..................................................................................................................................................................1064
42.6.1 Time Counter mode....................................................................................................................................... 1064
Low Power Timer Control Status Register (LPTMRx_CSR)........................................................................1057
Low Power Timer Prescale Register (LPTMRx_PSR)..................................................................................1058
Low Power Timer Compare Register (LPTMRx_CMR)...............................................................................1060
Low Power Timer Counter Register (LPTMRx_CNR)................................................................................. 1060
42.6.2 Pulse Counter mode....................................................................................................................................... 1065
Chapter 43
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Real Time Clock (SRTC)
43.1 Chip-specific information for this module....................................................................................................................1067
43.1.1 RTC Instantiation...........................................................................................................................................1067
43.1.2 RTC Clocking Information............................................................................................................................ 1067
43.1.3 Inter-connectivity Information.......................................................................................................................1068
43.2 Introduction...................................................................................................................................................................1069
43.2.1 Features.......................................................................................................................................................... 1069
43.2.2 Modes of operation........................................................................................................................................ 1070
43.2.3 RTC signal descriptions.................................................................................................................................1070
43.3 Register definition.........................................................................................................................................................1070
43.3.1 RTC Time Seconds Register (RTC_TSR).....................................................................................................1071
43.3.2 RTC Time Prescaler Register (RTC_TPR)....................................................................................................1071
43.3.3 RTC Time Alarm Register (RTC_TAR)....................................................................................................... 1072
43.3.4 RTC Time Compensation Register (RTC_TCR)...........................................................................................1072
43.3.5 RTC Control Register (RTC_CR)..................................................................................................................1074
43.3.6 RTC Status Register (RTC_SR).................................................................................................................... 1076
43.3.7 RTC Lock Register (RTC_LR)......................................................................................................................1077
43.3.8 RTC Interrupt Enable Register (RTC_IER)...................................................................................................1078
43.3.9 RTC Write Access Register (RTC_WAR).................................................................................................... 1080
43.3.10 RTC Read Access Register (RTC_RAR)...................................................................................................... 1081
43.4 Functional description...................................................................................................................................................1082
43.4.1 Power, clocking, and reset............................................................................................................................. 1082
43.4.2 Time counter.................................................................................................................................................. 1083
43.4.3 Compensation.................................................................................................................................................1084
43.4.4 Time alarm..................................................................................................................................................... 1085
43.4.5 Update mode.................................................................................................................................................. 1085
43.4.6 Register lock.................................................................................................................................................. 1085
43.4.7 Access control................................................................................................................................................1086
43.4.8 Interrupt..........................................................................................................................................................1086
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43.5 Usage Guide..................................................................................................................................................................1086
43.5.1 Clock source information...............................................................................................................................1086
43.5.2 Usage examples..............................................................................................................................................1086
43.5.3 RTC_CLKOUT signal................................................................................................................................... 1088
Chapter 44
Low Power Serial Peripheral Interface (LPSPI)
44.1 Chip-specific information for this module....................................................................................................................1089
44.1.1 Instantiation Information................................................................................................................................1089
44.1.2 Module Clocking Information for LPUART, LPSPI, LPI2C, FlexIO and LPIT...........................................1089
44.1.3 Inter-connectivity Information.......................................................................................................................1090
44.2 Introduction...................................................................................................................................................................1091
44.2.1 Overview........................................................................................................................................................1091
44.2.2 Features.......................................................................................................................................................... 1091
44.2.3 Block Diagram............................................................................................................................................... 1092
44.2.4 Modes of operation........................................................................................................................................ 1092
44.2.5 Signal Descriptions........................................................................................................................................ 1093
44.3 Memory Map and Registers..........................................................................................................................................1094
44.3.1
44.3.2
44.3.3
44.3.4
44.3.5
44.3.6
44.3.7
44.3.8
44.3.9
44.3.10
Version ID Register (LPSPIx_VERID)......................................................................................................... 1095
Parameter Register (LPSPIx_PARAM).........................................................................................................1096
Control Register (LPSPIx_CR)......................................................................................................................1097
Status Register (LPSPIx_SR).........................................................................................................................1098
Interrupt Enable Register (LPSPIx_IER).......................................................................................................1100
DMA Enable Register (LPSPIx_DER)..........................................................................................................1101
Configuration Register 0 (LPSPIx_CFGR0)..................................................................................................1102
Configuration Register 1 (LPSPIx_CFGR1)..................................................................................................1103
Data Match Register 0 (LPSPIx_DMR0).......................................................................................................1105
Data Match Register 1 (LPSPIx_DMR1).......................................................................................................1105
44.3.11
44.3.12
Clock Configuration Register (LPSPIx_CCR).............................................................................................. 1106
FIFO Control Register (LPSPIx_FCR)..........................................................................................................1107
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44.3.13
44.3.14
44.3.15
44.3.16
44.3.17
44.4 Functional description...................................................................................................................................................1113
44.4.1 Clocking and Resets.......................................................................................................................................1113
44.4.2 Master Mode.................................................................................................................................................. 1114
44.4.3 Slave Mode.................................................................................................................................................... 1119
44.4.4 Interrupts and DMA Requests........................................................................................................................1121
44.4.5 Peripheral Triggers.........................................................................................................................................1121
FIFO Status Register (LPSPIx_FSR).............................................................................................................1107
Transmit Command Register (LPSPIx_TCR)................................................................................................1108
Transmit Data Register (LPSPIx_TDR)........................................................................................................ 1111
Receive Status Register (LPSPIx_RSR)........................................................................................................ 1112
Receive Data Register (LPSPIx_RDR)..........................................................................................................1113
Chapter 45
Low Power Inter-Integrated Circuit (LPI2C)
45.1 Chip-specific information for this module....................................................................................................................1123
45.1.1 Instantiation Information................................................................................................................................1123
45.1.2 Module Clocking Information for LPUART, LPSPI, LPI2C, FlexIO and LPIT...........................................1123
45.1.3 Inter-connectivity Information.......................................................................................................................1124
45.2 Introduction...................................................................................................................................................................1125
45.2.1 Overview........................................................................................................................................................1125
45.2.2 Features.......................................................................................................................................................... 1125
45.2.3 Block Diagram............................................................................................................................................... 1127
45.2.4 Modes of operation........................................................................................................................................ 1127
45.2.5 Signal Descriptions........................................................................................................................................ 1128
45.3 Memory Map and Registers..........................................................................................................................................1128
45.3.1
45.3.2
45.3.3
45.3.4
Version ID Register (LPI2Cx_VERID)......................................................................................................... 1131
Parameter Register (LPI2Cx_PARAM).........................................................................................................1131
Master Control Register (LPI2Cx_MCR)......................................................................................................1132
Master Status Register (LPI2Cx_MSR).........................................................................................................1133
45.3.5
NXP Semiconductors 37
Master Interrupt Enable Register (LPI2Cx_MIER).......................................................................................1135
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45.3.6
45.3.7
45.3.8
45.3.9
45.3.10
45.3.11
45.3.12
45.3.13
45.3.14
45.3.15
45.3.16
45.3.17
45.3.18
45.3.19
Master DMA Enable Register (LPI2Cx_MDER).......................................................................................... 1137
Master Configuration Register 0 (LPI2Cx_MCFGR0)..................................................................................1138
Master Configuration Register 1 (LPI2Cx_MCFGR1)..................................................................................1139
Master Configuration Register 2 (LPI2Cx_MCFGR2)..................................................................................1141
Master Configuration Register 3 (LPI2Cx_MCFGR3)..................................................................................1142
Master Data Match Register (LPI2Cx_MDMR)............................................................................................1142
Master Clock Configuration Register 0 (LPI2Cx_MCCR0)..........................................................................1143
Master Clock Configuration Register 1 (LPI2Cx_MCCR1)..........................................................................1144
Master FIFO Control Register (LPI2Cx_MFCR).......................................................................................... 1145
Master FIFO Status Register (LPI2Cx_MFSR).............................................................................................1145
Master Transmit Data Register (LPI2Cx_MTDR).........................................................................................1146
Master Receive Data Register (LPI2Cx_MRDR)..........................................................................................1147
Slave Control Register (LPI2Cx_SCR)..........................................................................................................1148
Slave Status Register (LPI2Cx_SSR)............................................................................................................ 1149
45.3.20
45.3.21
45.3.22
45.3.23
45.3.24
45.3.25
45.3.26
45.3.27
45.3.28
45.4 Functional description...................................................................................................................................................1161
45.4.1 Clocking and Resets.......................................................................................................................................1161
45.4.2 Master Mode.................................................................................................................................................. 1162
45.4.3 Slave Mode.................................................................................................................................................... 1167
45.4.4 Interrupts and DMA Requests........................................................................................................................1170
Slave Interrupt Enable Register (LPI2Cx_SIER)...........................................................................................1152
Slave DMA Enable Register (LPI2Cx_SDER)..............................................................................................1153
Slave Configuration Register 1 (LPI2Cx_SCFGR1)..................................................................................... 1154
Slave Configuration Register 2 (LPI2Cx_SCFGR2)..................................................................................... 1156
Slave Address Match Register (LPI2Cx_SAMR)..........................................................................................1157
Slave Address Status Register (LPI2Cx_SASR)........................................................................................... 1158
Slave Transmit ACK Register (LPI2Cx_STAR)........................................................................................... 1159
Slave Transmit Data Register (LPI2Cx_STDR)............................................................................................ 1159
Slave Receive Data Register (LPI2Cx_SRDR)............................................................................................. 1160
45.4.5 Peripheral Triggers.........................................................................................................................................1172
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45.5 Usage Guide..................................................................................................................................................................1173
Chapter 46
Low Power Universal Asynchronous Receiver/Transmitter (LPUART)
46.1 Chip-specific information for this module....................................................................................................................1175
46.1.1 Instantiation Information................................................................................................................................1175
46.1.2 Module Clocking Information for LPUART, LPSPI, LPI2C, FlexIO and LPIT...........................................1175
46.1.3 Inter-connectivity Information.......................................................................................................................1176
46.2 Introduction...................................................................................................................................................................1177
46.2.1 Features.......................................................................................................................................................... 1177
46.2.2 Modes of operation........................................................................................................................................ 1178
46.2.3 Signal Descriptions........................................................................................................................................ 1179
46.2.4 Block diagram................................................................................................................................................1179
46.3 Register definition.........................................................................................................................................................1181
46.3.1 LPUART Register Descriptions.....................................................................................................................1181
46.4 Functional description...................................................................................................................................................1205
46.4.1 Baud rate generation...................................................................................................................................... 1205
46.4.2 Transmitter functional description.................................................................................................................1206
46.4.3 Receiver functional description..................................................................................................................... 1209
46.4.4 Additional LPUART functions...................................................................................................................... 1216
46.4.5 Infrared interface............................................................................................................................................1218
46.4.6 Interrupts and status flags.............................................................................................................................. 1219
Chapter 47
Flexible I/O (FlexIO)
47.1 Chip-specific Information for this Module...................................................................................................................1221
47.1.1 Instantiation Information................................................................................................................................1221
47.1.2 FlexIO Clocking Information.........................................................................................................................1221
47.1.3 Inter-connectivity Information.......................................................................................................................1222
47.2 Introduction...................................................................................................................................................................1223
47.2.1 Overview........................................................................................................................................................1223
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47.2.2 Features.......................................................................................................................................................... 1224
47.2.3 Block Diagram............................................................................................................................................... 1224
47.2.4 Modes of operation........................................................................................................................................ 1225
47.2.5 FlexIO Signal Descriptions............................................................................................................................1225
47.3 Memory Map/Register Definition.................................................................................................................................1226
47.3.1 Version ID Register (FLEXIO_VERID)....................................................................................................... 1228
47.3.2 Parameter Register (FLEXIO_PARAM).......................................................................................................1229
47.3.3 FlexIO Control Register (FLEXIO_CTRL)...................................................................................................1229
47.3.4 Pin State Register (FLEXIO_PIN).................................................................................................................1230
47.3.5 Shifter Status Register (FLEXIO_SHIFTSTAT)...........................................................................................1231
47.3.6 Shifter Error Register (FLEXIO_SHIFTERR).............................................................................................. 1232
47.3.7 Timer Status Register (FLEXIO_TIMSTAT)................................................................................................1232
47.3.8 Shifter Status Interrupt Enable (FLEXIO_SHIFTSIEN)...............................................................................1233
47.3.9 Shifter Error Interrupt Enable (FLEXIO_SHIFTEIEN)................................................................................ 1234
47.3.10 Timer Interrupt Enable Register (FLEXIO_TIMIEN)...................................................................................1234
47.3.11 Shifter Status DMA Enable (FLEXIO_SHIFTSDEN).................................................................................. 1235
47.3.12
47.3.13
47.3.14
47.3.15
47.3.16
47.3.17
47.3.18
47.3.19
47.3.20
47.4 Functional description...................................................................................................................................................1245
Shifter Control N Register (FLEXIO_SHIFTCTLn).....................................................................................1235
Shifter Configuration N Register (FLEXIO_SHIFTCFGn).......................................................................... 1237
Shifter Buffer N Register (FLEXIO_SHIFTBUFn)...................................................................................... 1238
Shifter Buffer N Bit Swapped Register (FLEXIO_SHIFTBUFBISn)...........................................................1239
Shifter Buffer N Byte Swapped Register (FLEXIO_SHIFTBUFBYSn)...................................................... 1239
Shifter Buffer N Bit Byte Swapped Register (FLEXIO_SHIFTBUFBBSn).................................................1240
Timer Control N Register (FLEXIO_TIMCTLn)..........................................................................................1240
Timer Configuration N Register (FLEXIO_TIMCFGn)............................................................................... 1242
Timer Compare N Register (FLEXIO_TIMCMPn)...................................................................................... 1244
47.4.1 Shifter operation.............................................................................................................................................1245
47.4.2 Timer operation..............................................................................................................................................1247
47.4.3 Pin operation.................................................................................................................................................. 1249
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47.5 Application Information................................................................................................................................................1250
47.5.1 UART Transmit............................................................................................................................................. 1250
47.5.2 UART Receive...............................................................................................................................................1251
47.5.3 SPI Master......................................................................................................................................................1253
47.5.4 SPI Slave........................................................................................................................................................1255
47.5.5 I2C Master......................................................................................................................................................1257
47.5.6 I2S Master......................................................................................................................................................1259
47.5.7 I2S Slave........................................................................................................................................................ 1260
47.6 Usage Guide..................................................................................................................................................................1261
Chapter 48
Touch Sensing Input (TSI)
48.1 Chip-specific information for this module....................................................................................................................1269
48.1.1 Instantiation Information................................................................................................................................1269
48.1.2 TSI Clocking Information..............................................................................................................................1270
48.1.3 Inter-connectivity Information.......................................................................................................................1270
48.2 Introduction...................................................................................................................................................................1271
48.2.1 Features.......................................................................................................................................................... 1272
48.2.2 Modes of operation........................................................................................................................................ 1272
48.2.3 Block diagram................................................................................................................................................1272
48.3 External signal description............................................................................................................................................1273
48.3.1 TSI[24:0]........................................................................................................................................................1274
48.4 Register definition.........................................................................................................................................................1274
48.4.1 TSI General Control and Status Register (TSI_GENCS).............................................................................. 1275
48.4.2 TSI DATA Register (TSI_DATA)................................................................................................................ 1278
48.4.3 TSI Threshold Register (TSI_TSHD)............................................................................................................1279
48.4.4 TSI MODE Register (TSI_MODE)............................................................................................................... 1280
48.4.5 TSI MUTUAL-CAP Register 0 (TSI_MUL0)...............................................................................................1282
48.4.6 TSI MUTUAL-CAP Register 1 (TSI_MUL1)...............................................................................................1285
48.4.7 TSI SINC filter Register (TSI_SINC)............................................................................................................1288
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48.4.8 TSI SSC Register 0 (TSI_SSC0)................................................................................................................... 1292
48.4.9 TSI SSC Register 0 (TSI_SSC1)................................................................................................................... 1294
48.4.10 TSI SSC Register 2 (TSI_SSC2)................................................................................................................... 1295
48.5 Functional description...................................................................................................................................................1296
48.5.1 Touch Sensor..................................................................................................................................................1297
48.5.2 Brief timing and Operation of TSI.................................................................................................................1298
48.5.3 Self-cap sensing mode................................................................................................................................... 1299
48.5.4 Mutual-cap sensing mode.............................................................................................................................. 1301
48.5.5 Enable TSI module.........................................................................................................................................1303
48.5.6 Software and hardware trigger.......................................................................................................................1303
48.5.7 Scan times...................................................................................................................................................... 1303
48.5.8 Clock setting.................................................................................................................................................. 1304
48.5.9 Reference voltage...........................................................................................................................................1305
48.5.10 End of scan.....................................................................................................................................................1305
48.5.11 Out-of-range interrupt....................................................................................................................................1306
48.5.12 Wake up MCU from low power modes.........................................................................................................1306
48.5.13 DMA function support...................................................................................................................................1306
48.5.14 Spread spectrum clocking.............................................................................................................................. 1306
48.6 Usage Guide..................................................................................................................................................................1309
48.6.1 TSI Interrupts................................................................................................................................................. 1309
48.6.2 How to use TSI module................................................................................................................................. 1309
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Chapter 1 About This Manual

1.1 Audience

This reference manual is intended for system software and hardware developers and applications programmers who want to develop products with this device. It assumes that the reader understands operating systems, microprocessor system design, and basic principles of software and hardware.
1.2
This manual has two main sets of chapters.
1. Chapters in the first set contain information that applies to all components on the
2. Chapters in the second set are organized into functional groupings that detail
1.3
Each module chapter has two main parts:

Organization

chip.
particular areas of functionality.
• Examples of these groupings are clocking, timers, and communication interfaces.
• Each grouping includes chapters that provide a technical description of individual modules.

Module descriptions

•
Chip-specific: The first section, Chip-specific [module name] information, includes the number of module instances on the chip and possible implementation differences between the module instances, such as differences in FIFO depths or the number of
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Chapter 49 Enhanced Serial Communication Interface (eSCI)
49.1 Chip-specific eSCI information
This chip has six instances of the eSCI module. Some feature details vary between the instances.
The following table summarizes the feature differences. The table does not list feature details that the instances share.
Table 49-1. eSCI instance feature differences
Instance DMA support
eSCI_A and eSCI_B Yes eSCI_C, eSCI_D, eSCI_E, and eSCI_F No: descriptions of eSCI DMA functionality do not apply to
these instances
NOTE
For eSCI_D, the single wire feature does not appl y for TX/RX via PCSA3 because this pad works only as an output.
49.2 Introduction
The eSCI block is an enhanced SCI block wi th a LIN master interface layer and DMA support. The LIN master layer complies with the specifications LI N 1.3, LIN 2.0, LIN
2.1, and SAE J2602/1.
49.2.1 Bibliography
• LIN Specification Package Revision 1.3; December 12, 2002
• LIN Specification Package Revision 2.0; September 23, 2003
Sample Reference Manual
EXAMPLE
Chip-specific information that should be read first
Beginning of general module information
Module descriptions
channels supported. It may also include functional connections between the module instances and other modules. Read this section first because its content is crucial to understanding the information in other sections of the chapter.
• General: The subsequent sections provide general information about the module,
including its signals, registers, and functional description.
NOTE
If there is a conflict between the chip-specific module information (first section) and the general module information (subsequent sections), the chip-specific information supersedes the general information.
Figure 1-1. Example: chapter chip-specific information and general module information
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Chapter 34 Software Watchdog Timer (SWT)
34.1 Chip-specific SWT information
This chip has two instances of the SWT module: SWT_A and SWT_B.
34.1.1 SWT register reset values
The foll owi ng tabl e identi fies chip-specific reset values of SWT registers.
Table 34-1. Chip-specific SWT register reset values
Register SWT_A SWT_B
CR FF00_010Bh FF00_010Ah TO 0005_FCD0h 0005_FCD0h
34.2 Introduction
Sample Reference Manual
This section provides an overvi ew, list of features, and modes of operation for the SWT.
The Software Watchdog Timer (SWT) is a peripheral modul e that can prevent system lockup in situations such as software getti ng trapped in a loop or if a bus transaction fai ls to terminate. When enabled, the SWT requires periodi c execution of a watchdog servicing operation. The servicing operation resets the timer to a speci fied time-out peri od. I f this servicing action does not occur before the timer expires the SWT generates an interrupt or hardware reset. The SWT can be configured to generate a reset or interrupt on an initi al time-out. A reset is always generated on a second consecutive ti me-out.
34.2.1 Overview
accesses by masters without permission. If the RIA bit in the SWT_CR is set then the SWT generates a system reset on an invalid access otherwise a bus error is generated. If either the HLK or SLK bits in the SWT_CR are set, then the SWT_CR, SWT_TO, SWT_WN, and SWT_SK registers are read-only.
The SWT memory map is shown in the following table.
SWT memory map
Address
offset (hex)
Register name
Width
(in bits)
Access Reset value
Section/
page
0 SWT Control Register (SWT_CR) 32 R/W See section 34.4.1/1331 4 SWT Interrupt Register (SWT_IR) 32 R/W 0000_0000h 34.4.2/1334 8 SWT Time-out Register (SWT_TO) 32 R/W See section 34.4.3/1334
C SWT Window Register (SWT_WN) 32 R/W 0000_0000h 34.4.4/1335 10 SWT Service Register (SWT_SR) 32 W 0000_0000h 34.4.5/1335 14 SWT Counter Output Register (SWT_CO) 32 R 0000_0000h 34.4.6/1336 18 SWT Service Key Register (SWT_SK) 32 R/W 0000_0000h 34.4.7/1336
34.4.1 SWT Control Register (SWT_CR)
NOTE
The reset val ue for the SWT_CR is impl ementation specif ic.
See the confi guration information. The SWT_CR contains fields for configuring and controll ing the SWT. This regi ster is read-only if either the SWT_CR[HLK] or SWT_CR[SL K] bits are set.
Address: 0h base + 0h offset = 0h
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
MAP0
MAP1
MAP2
MAP3
MAP4
MAP5
MAP6
MAP7
0
W
Reset
0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0*
Bit
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
0
SMD RIA WND ITR HLK SLK CSL STP FRZ WEN
W
Reset
0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0*
* Notes:
The reset value for the SWT_CR is implementation specific. See the configuration information.•
Chapter 34 Software Watchdog Timer (SWT)
Sample Reference Manual
EXAMPLE
Chapter 1 About This Manual
1.3.1 Example: chip-specific information that supersedes content in the same chapter
The example below shows chip-specific information that supersedes general module information presented later in the chapter. In this case, the chip-specific register reset values supersede the reset values that appear in the register diagram.
Figure 1-2. Example: chip-specific information that supersedes content in the same
1.3.2
Example: chip-specific information that refers to a different chapter
The chip-specific information below refers to another chapter's chip-specific information. In this case, read both sets of chip-specific information before reading further in the chapter.
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chapter
Page 46
Chapter 10 Crossbar Integrity Checker (XBIC)
10.1 Chip-specific XBIC information
This chip has one instance of the XBIC module.
10.1.1 XBIC master and slave assignments
The XBI C identifies each XBAR master and slave in terms of the master or slave's physical port number. See the "Physical master port" assignments in Table 9-1 and the "Slave port" assignments in Tabl e 9-2.
10.1.2 Unimplemented MCR and ESR fields
10.2 Overview
Sample Reference Manual
Chapter 9 Crossbar Switch (XBAR)
9.1 Chip-specific XBAR information
This chip has one instance of the XBAR module.
9.1.1 XBAR master and slave assignments
The foll owing table l ists the XBAR physical port numbers and l ogical IDs for al l master ports on this SoC.
• Each port number matches the def ault priority assigned to the correspondi ng physical master port. This default pri ori ty equals the reset value of the priority fiel d for each master port in the PRS
n registers.
• A priority value of 0 is the highest priority. There is no "disabled" value for the priority.
• A Nexus_3 module and core data bus share the same physical master port for each core.
The logical master ID corresponds to the logical address provided by the master module and is unique f or each module. The logi cal master IDs are used by the bus masters connected to the XBAR. The Nexus master is identifi ed by setting the MSB in the 4-bi t field that supplies the master ID number.
Table 9-1. XBAR master ports and logical master IDs
Module Physical master port Logical master ID Comment
Core0 instruction 0 0 Core0 data
1
0 Nexus_3_0 8 Nexus_3_0 arbitrates with Core0 data for XBAR port 1 Core1 instruction 2 1 Core1 data
3
1 Nexus_3_1 9 Nexus_3_1 arbitrates with Core1 data for XBAR port 3
Table continues on the next page...
Sample Reference Manual
The Crossbar Integrity Checker (X BIC) verifies the i ntegrity of the crossbar transfers. For f orward signals (master to slave), it is done by verif ying the integrity of the attribute information using an 8-bit Error Detection Code (EDC). The EDC detects any single- or double-bit errors in the attribute information and signals the Fault Collection and Control Unit (FCCU) when an error is detected. For feedback signals (slave to master), it is done by comparing the consistency of the signal s during the AHB dataphase.There are three signals from slave to master, hready, hresp0, and hresp2. If any of the master signals is different from the slave signals during dataphase, the error will be reported in the Error Status Register.
On this chi p, the MCR[SE5] and ESR[DPSE5] fields are not implemented. In X BIC
Module Control Register (XBI C_MCR) and XBIC Error Status Regi ster (XBIC_ESR),
these fields are reserved.
EXAMPLE

Register descriptions

Figure 1-3. Example: chip-specific information that refers to a different chapter
1.4
Register descriptions
Module chapters present register information in:
• Memory maps including:
• Addresses
• The name and acronym/abbreviation of each register
• The width of each register (in bits)
• Each register's reset value
• The page number on which each register is described
• Register figures
• Field-description tables
• Associated text
The register figures show the field structure using the conventions in the following figure.
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R
W
Reserved
Reserved,
unimplemented
R
W
1
Write-only one
0
R
W
Write-only zero
R
W
1
Read-only one
0
R
W
Read-only zero
R
W
Mnemonic
0
Read-only
writes zero
R
W
Mnemonic
1
Read-only writes one
R
W
Mnemonic
Read-only
writes undefined
R
W
Mnemonic
Write-only
reads undefined
R
W
Mnemonic
w1c
Write one to clear
R
W
Mnemonic
Read/write
R
W
Mnemonic
Read-only
R
W
Mnemonic
Write-only
R
W
Mnemonic
0
Write-only reads zero
R
W
Mnemonic
1
Write-only reads one
Figure 1-4. Register figure conventions
Chapter 1 About This Manual
1.5
1.5.1
The following suffixes identify different numbering systems:
b Binary number. For example, the binary equivalent of the number 5 is written 101b. In some cases,
d Decimal number. Decimal numbers are followed by this suffix only when the possibility of confusion
h Hexadecimal number. For example, the hexadecimal equivalent of the number 60 is written 3Ch. In
1.5.2 Typographic notation
The following typographic notation is used throughout this document:
placeholder, x Items in italics are placeholders for information that you provide. Italicized text is also used for
code

Conventions

Numbering systems
This suffix Identifies a
binary numbers are shown with the prefix 0b.
exists. In general, decimal numbers are shown without a suffix.
some cases, hexadecimal numbers are shown with the prefix 0x.
Example Description
the titles of publications and for emphasis. Plain lowercase letters are also used as placeholders for single letters and numbers.
Fixed-width type indicates text that must be typed exactly as shown. It is used for instruction mnemonics, directives, symbols, subcommands, parameters, and operators. Fixed-width type
Table continues on the next page...
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Conventions
Example Description
is also used for example code. Instruction mnemonics and directives in text and tables are shown in all caps; for example, BSR.
SR[SCM] A mnemonic in brackets represents a named field in a register. This example refers to the
Scaling Mode (SCM) field in the Status Register (SR).
REVNO[6:4], XAD[7:0] Numbers in brackets and separated by a colon represent either:
• A subset of a register's named field For example, REVNO[6:4] refers to bits 6–4 that are part of the COREREV field that
occupies bits 6–0 of the REVNO register.
• A continuous range of individual signals of a bus For example, XAD[7:0] refers to signals 7–0 of the XAD bus.
1.5.3 Special terms
The following terms have special meanings:
Term Meaning
asserted Refers to the state of a signal as follows:
• An active-high signal is asserted when high (1).
• An active-low signal is asserted when low (0).
deasserted Refers to the state of a signal as follows:
• An active-high signal is deasserted when low (0).
• An active-low signal is deasserted when high (1).
In some cases, deasserted signals are described as negated.
reserved Refers to a memory space, register, field, or programming setting. Writes to a reserved location can
result in unpredictable functionality or behavior.
• Do not modify the default value of a reserved programming setting, such as the reset value of a reserved register field.
• Consider undefined locations in memory to be reserved.
w1c Write 1 to clear: Refers to a register bitfield that must be written as 1 to be "cleared."
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Chapter 2 Introduction

2.1 Overview

Information found here provides an overview of this MCU, which is a part of Kinetis E­series of ARM® Cortex®-M0+ MCUs and product family. It also presents high-level descriptions of the modules available on the device covered by this document.
2.2
The following figure shows a top-level block diagram of the MCU superset device.

Block Diagram

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Page 50

Module Functional Categories

Kinetis KE1xZ Sub-Family
®
Debug
interfaces
Interrupt
controller
and Integrity
CRC
FAC
CortexARM
Core
®
-M0+
MMDVSQ
Analog
12-bit ADC
x2
CMP x2
System
eDMA
DMAMUX
TRGMUX
WDOG
EWM
Timers
FlexTimer
8ch x1 4ch x2
PDB x1
Memories and Memory Interfaces
Program
flash
FlexMemory
RAM
Boot ROM
Communication InterfacesSecurity
2
LPI C
x2
LPUART
x3
Clocks
OSC
FIRC
SIRC
LPFLL
OSC32
LPO
Human-Machine
Interface (HMI)
GPIO
upto 58
High drive
I/O (8 pins)
8-bit DAC x1
(within CMP0,
output capable)
PMC
LPIT, 4ch
LPTMR
SRTC
PWT
LPSPI
x2
FlexIO
Digital filters
(port E)
TSI, 36ch (optional)
Figure 2-1. MCU block diagram
2.3
Module Functional Categories
The modules on this device are grouped into functional categories. The following sections describe the modules assigned to each category in more detail.
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Chapter 2 Introduction
Table 2-1. Module functional categories
Module category Description
ARM® Cortex®-M0+ core and related modules
System modules • System integration module (SIM)
Memories and memory interfaces • Internal memories include:
Clocks • System clock generator (SCG)
Security and integrity modules • Cyclic Redundancy Check (CRC) module for error detection
Analog modules • High speed analog-to-digital converter (ADC)
Timer modules • Programmable delay block (PDB)
Communication interfaces • Low-power Serial peripheral interface (LPSPI)
Human-machine interfaces (HMI) • General purpose input/output controller (GPIO)
• 32-bit MCU core from ARM's Cortex-M class, 1.77 CoreMark®/MHz from single-cycle access memories, 72 MHz CPU frequency
• Debug interfaces
• Serial Wire Debug (SWD)
• Micro Trace Buffer (MTB)
• MMDVSQ
• System mode controller (SMC)
• Miscellaneous control module (MCM)
• Crossbar switch (AXBS-Lite)
• Bit manipulation engine (BME)
• Peripheral bridge (AIPS-Lite)
• Direct memory access (DMA) controller with multiplexer (DMAMUX) to increase available DMA requests. DMA can now handle transfers in VLPS mode
• Watchdog (WDOG)
• External watchdog monitor (EWM)
• Program flash memory
• FlexMemory
• FlexNVM
• FlexRAM
• SRAM
• Boot ROM
• Low-Power-Frequency-locked loop (LPFLL)
• Fast internal reference clock (FIRC)
• Slow internal reference clock (SIRC)
• System oscillator (OSC)
• Low Power Oscillator (LPO)
• Peripheral Clock Control (PCC)
• Flash Access Control (FAC)
• 128-bit unique identification (ID) number
• ADC self-test and calibration feature
• Comparator (CMP)
• Bandgap voltage reference (1V reference voltage)
• Power management controllers (PMC)
• Multiple power modes available based on run, wait, stop, and power­down modes
• FlexTimers (FTM)
• Low-power periodic interrupt timer (LPIT)
• Low power timer (LPTMR)
• Independent real time clock (RTC)
• Low-power Inter-integrated circuit (LPI2C)
• Low-power UART (LPUART)
• FlexIO
• Capacitive touch sense input (TSI) interface enabled in hardware
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Module Functional Categories
Module category Description
Table 2-1. Module functional categories
• High drive I/O pins, see Pin properties.
• Digital filters, see "Ports summary" table in Port control and interrupt module
features.
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Chapter 3 Core Overview

3.1 ARM Cortex-M0+

The ARM Cortex-M0+ is the member of the Cortex-M Series of processors targeting the micro-controller market. It is an entry-level 32-bit processor designed for very cost sensitive, low power applications. The Cortex-M0+ has a 2-stage pipeline von Neumann architecture. The processor delivers exceptional energy efficiency through extensively optimized design and provides high-end processing hardware including a single-cycle multiplier. It also has an I/O port which supports single cycle loads and stores to tightly­coupled peripherals (e.g. GPIO).
The Cortex-M0+ processor implements the ARMv6-M architecture, which is upward compatible with other Cortex-M profile processors. It is based on the 16-bit Thumb instruction set and includes Thumb-2 technology (including all but three 16-bit Thumb opcodes plus seven 32-bit instructions). The Cortex-M0+ instruction set provides the exceptional performance expected of a modern 32-bit architecture, with a higher code density than 8-bit and 16-bit microcontrollers.
®
Cortex-M0+ Processor Features
• Thumb instruction set with Thumb-2 technology
• Nested Vectored Interrupt Controller (NVIC)
• Single-cycle 32-bit hardware multiplier
• Single-cycle I/O port
• Serial-Wire Debug port (SWD)
• Breakpoint & Watchpoint Units
• Micro Trace Buffer (MTB)
• 24-bit system tick timer (SysTick)
The detailed architecture and programming model of Cortex-M0+ processor are discussed in the following documents from ARM.
• Cortex-M0+ Devices Generic User Guide
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Optional Debug
Cortex-M0+ components
Cortex-M0+ processor
Nested Vectored
Interrupt Controller
(NVIC)
Cortex-M0+
processor core
Opertional
Memory Protection
Unit (MPU)
Bus Matrix
Debugger
interface
Breakpoint &
Watchpoint
Unit
Optional
Micro Trace
Buffer (MTB)
Optional
Debug Access
Port
Optional
Wakeup Interrupt
Controller (WIC)
Interrupts
AHB-Lite interface
to system
Optional
single-cycle
IO port
Optional
Serial-Wire or JTAG
debug port

Core Buses and Interfaces

• Cortex-M0+ Technical Reference Manual
• ARMv6-M Architecture Reference Manual
3.2 Core Buses and Interfaces
The Cortex-M0+ processor provides a single system-level interface using AMBA
®
technology to provide memory and peripheral accesses, a single-cycle I/O port for high speed access to tightly-coupled peripherals (such as GPIO), a NVIC interface for interrupt handling, a Debug Access Port (DAP) for SWD debug and a Micro Trace Buffer (MTB) interface for trace.
The following interfaces are implemented on the Cortex-M0+ processor of this device.
• A single AHB-Lite bus
• A single-cycle IO port
• PPB bus
• NVIC interface
• MTB interface
• Debug port interface
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Chapter 3 Core Overview

3.3 Core Component Configuration

The processor supports optional tightly-coupled system components. The following table lists the specific configuration of the Cortex-M0+ core on this device.
Component name Present on this device Note
Single-cycle Multiplier YES Single-cycle IO Port YES SysTick YES Halting debug YES Watchpoint YES Include 2 comparators Breakpoint YES Include 2 comparators MTB YES WIC YES Vector Table Offset Support YES Unprivileged/Privileged Support YES SWD YES MPU Not present

3.4 SysTick Clock Configuration

The System Tick Timer's clock source is always the core clock (CORE_CLK) on this device. This results in the following:
• The CLKSOURCE bit in SysTick Control and Status Register (SYST_CSR) is always set to select the core clock.
• Because the timing reference (CORE_CLK) is a variable frequency, the TENMS bit in the SysTick Calibration Value Register (SYST_CALIB) is always zero.
• The NOREF bit in SysTick Calibration Value Register (SYST_CALIB) is always set, implying that CORE_CLK is the only available source of reference timing.
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SysTick Clock Configuration
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Chapter 4 Interrupts

4.1 Introduction

The ARM Cortex-M0+ processor includes an interrupt controller called the Nested Vectored Interrupt Controller (NVIC). It is closely coupled to the processor core to provide outstanding interrupt handling abilities and low latency interrupt processing. The NVIC supports nested interrupt, dynamic priority changes, interrupt masking and interrupt tail-chaining. In addition, the NVIC also supports re-locatable vector table and an external Nonmaskable Interrupt (NMI).
The NVIC registers are located within the processor's internal System Control Space (SCS) with base address of 0xE000E000. Most of the NVIC registers are accessible only in privileged mode. The detailed NVIC functionalities and registers descriptions are discussed in the following documents from ARM web.
• Cortex-M0+ Devices Generic User Guide
• Cortex-M0+ Technical Reference Manual
4.2
The NVIC supports configurable interrupt number and level of priority. The following sections speficy the exact priority level and interrupt vectors implemented on this device.
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NVIC configuration

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Interrupt channel assignments

4.2.1 Interrupt priority levels
The NVIC on this device supports 4 interrupt priority levels. Therefore, the NVIC_IPR registers contains 2 bits for each interrupt request (IRQ). For example, NVIC_IPR0 is shown below:
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
W
R
IRQ3
0 0 0 0 0 0
IRQ2
0 0 0 0 0 0
IRQ1
0 0 0 0 0 0
IRQ0
0 0 0 0 0 0
4.2.2 Non-maskable interrupt
This device supports non-maskable interrupt (NMI) to the NVIC. It is controlled by the external NMI signal from the pin. The pin which the NMI signal is multiplexed on, must be configured for the NMI function to generate the non-maskable interrupt request.
4.3
Interrupt channel assignments
The interrupt source assignments are defined in the following table.
• Vector number — the value stored on the stack when an interrupt is serviced.
• IRQ number — non-core interrupt source count, which is the vector number minus
16.
The IRQ number is used within ARM's NVIC documentation.
Table 4-2. Interrupt vector assignments
Address Vector IRQ
ARM Core System Handler Vectors
0x0000_0000 0 – – ARM core Initial Stack Pointer 0x0000_0004 1 – – ARM core Initial Program Counter 0x0000_0008 2 – – ARM core Non-maskable Interrupt (NMI) 0x0000_000C 3 – – ARM core Hard Fault 0x0000_0010 4 – – — — 0x0000_0014 5 – – — — 0x0000_0018 6 – – — — 0x0000_001C 7 – – — —
1
NVIC
IPR
register
number
Source module Source description
2
Table continues on the next page...
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Chapter 4 Interrupts
Table 4-2. Interrupt vector assignments (continued)
Address Vector IRQ
0x0000_0020 8 – – — — 0x0000_0024 9 – – — — 0x0000_0028 10 – – — — 0x0000_002C 11 – – ARM core Supervisor call (SVCall) 0x0000_0030 12 – – — — 0x0000_0034 13 – – — — 0x0000_0038 14 – – ARM core Pendable request for system service
0x0000_003C 15 – – ARM core System tick timer (SysTick)
Non-Core Vectors
0x0000_0040 16 0 0 DMA DMA channel 0 or 4 transfer complete 0x0000_0044 17 1 0 DMA DMA channel 1 or 5 transfer complete 0x0000_0048 18 2 0 DMA DMA channel 2 or 6 transfer complete 0x0000_004C 19 3 0 DMA DMA channel 3 or 7 transfer complete 0x0000_0050 20 4 1 DMA DMA error interrupt channels 0-7 0x0000_0054 21 5 1 Flash memory Single interrupt vector for all sources 0x0000_0058 22 6 1 PMC Low-voltage detect, low-voltage warning 0x0000_005C 23 7 1 Port control module Pin detect (Port A, E) 0x0000_0060 24 8 2 LPI2C0 Single interrupt vector for all sources 0x0000_0064 25 9 2 LPI2C1 — 0x0000_0068 26 10 2 LPSPI0 Single interrupt vector for all sources 0x0000_006C 27 11 2 LPSPI1 Single interrupt vector for all sources 0x0000_0070 28 12 3 LPUART0 Single interrupt vector for all sources 0x0000_0074 29 13 3 LPUART1 Single interrupt vector for all sources 0x0000_0078 30 14 3 LPUART2 Single interrupt vector for all sources 0x0000_007C 31 15 3 ADC0 — 0x0000_0080 32 16 4 CMP0 — 0x0000_0084 33 17 4 FTM0 Single interrupt vector for all sources 0x0000_0088 34 18 4 FTM1 Single interrupt vector for all sources 0x0000_008C 35 19 4 FTM2 Single interrupt vector for all sources 0x0000_0090 36 20 5 RTC Single interrupt vector for all sources 0x0000_0094 37 21 5 CMP1 — 0x0000_0098 38 22 5 LPIT LPIT channel 0-3 0x0000_009C 39 23 5 FlexIO — 0x0000_00A0 40 24 6 TSI — 0x0000_00A4 41 25 6 PDB0 — 0x0000_00A8 42 26 6 Port control module Pin detect (Port B, C, D)
1
NVIC
IPR
register
number
Source module Source description
2
(PendableSrvReq)
Table continues on the next page...
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Interrupt channel assignments
Table 4-2. Interrupt vector assignments (continued)
Address Vector IRQ
0x0000_00AC 43 27 6 SCG — 0x0000_00B0 44 28 7 WDOG or EWM Both watchdog modules share this interrupt. 0x0000_00B4 45 29 7 PWT or LPTMR Single interrupt vector for all sources 0x0000_00B8 46 30 7 ADC1 Single interrupt vector for all sources 0x0000_00BC 47 31 7 RCM Single interrupt vector for all sources
1. Indicates the NVIC's interrupt source number.
2. Indicates the NVIC's IPR register number used for this IRQ. The equation to calculate this value is: IRQ div 4
1
NVIC
IPR
register
number
Source module Source description
2
4.3.1 Determining the bitfield and register location for configuring a particular interrupt
Suppose you need to configure the low-power timer (LPTMR) interrupt. The following table is an excerpt of the LPTMR row from Interrupt channel assignments (value number as example only).
Table 4-3. LPTMR interrupt vector assignment (example only)
Address Vector IRQ
0x0000_0128 74 58 1 14 Low Power Timer —
1. Indicates the NVIC's interrupt source number.
2. Indicates the NVIC's ISER, ICER, ISPR, ICPR, and IABR register number used for this IRQ. The equation to calculate this
value is: IRQ div 32
3. Indicates the NVIC's IPR register number used for this IRQ. The equation to calculate this value is: IRQ div 4
1
NVIC
non-IPR
register
number
2
NVIC IPR
register
number
Source module Source description
3
• The NVIC registers you would use to configure the interrupt are:
• NVIC_ISER1
• NVIC_ICER1
• NVIC_ISPR1
• NVIC_ICPR1
• NVIC_IABR1
• NVIC_IPR14
• To determine the particular IRQ's bitfield location within these particular registers:
• NVIC_ISER1, NVIC_ICER1, NVIC_ISPR1, NVIC_ICPR1, NVIC_IABR1 bit location = IRQ mod 32 = 26
• NVIC_IPR14 bitfield starting location = 8 × (IRQ mod 4) + 4 = 20
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Chapter 4 Interrupts
Since the NVIC_IPR bitfields are 2-bit wide (4 priority levels), the NVIC_IPR14 bitfield range is 20-21
Therefore, the following bitfield locations are used to configure the LPTMR interrupts:
• NVIC_ISER1[26]
• NVIC_ICER1[26]
• NVIC_ISPR1[26]
• NVIC_ICPR1[26]
• NVIC_IABR1[26]
• NVIC_IPR14[21:20]
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Interrupt channel assignments
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Chapter 5 System Integration Module (SIM)

5.1 Introduction

The System Integration Module (SIM) provides system control and chip configuration registers.
5.1.1
Features of the SIM include:
• System clocking configuration
• Flash and system RAM size configuration
• FlexTimer clock and channel selection and configuration
• ADC trigger selection
• Flash configuration
• System device unique identification (UID)
• LPUART pseudo open drain control
5.2
Features

Memory map and register definition

NOTE
The SIM registers can only be written in the supervisor mode. In the user mode, write accesses are blocked and will result in a bus error.
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Memory map and register definition
SIM memory map
Absolute
address
(hex)
4004_8004 Chip Control register (SIM_CHIPCTL) 32 R/W 0000_0000h 5.2.1/64
4004_800C FTM Option Register 0 (SIM_FTMOPT0) 32 R/W 0000_0000h 5.2.2/66
4004_8018 ADC Options Register (SIM_ADCOPT) 32 R/W 0000_0000h 5.2.3/67
4004_801C FTM Option Register 1 (SIM_FTMOPT1) 32 R/W 0000_0000h 5.2.4/69
4004_8024 System Device Identification Register (SIM_SDID) 32 R See section 5.2.5/71
4004_804C Flash Configuration Register 1 (SIM_FCFG1) 32 R See section 5.2.6/72
4004_8050 Flash Configuration Register 2 (SIM_FCFG2) 32 R See section 5.2.7/74 4004_8054 Unique Identification Register High (SIM_UIDH) 32 R See section 5.2.8/75 4004_8058 Unique Identification Register Mid-High (SIM_UIDMH) 32 R See section 5.2.9/75
4004_805C Unique Identification Register Mid Low (SIM_UIDML) 32 R See section 5.2.10/76
4004_8060 Unique Identification Register Low (SIM_UIDL) 32 R See section 5.2.11/76
4004_806C Miscellaneous Control register (SIM_MISCTRL) 32 R/W 0000_0000h 5.2.12/77
Register name
Width
(in bits)
Access Reset value
Section/
page
5.2.1 Chip Control register (SIM_CHIPCTL)
SIM_CHIPCTL contains the controls for selecting PWT alternative clock source, ADC COCO trigger, trace clock, clock out source, PDB back-to-back mode and ADC interleave channel.
Address:
Reset
Reset
4004_8000h base + 4h offset = 4004_8004h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
W
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bit
R
0 0
W
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
PDB_
BB_ SEL
0 0
0
EL
RTC32KCLKS
0
INTERLEAV
CLKOUTSEL
CLKOUTDIV
SIM_CHIPCTL field descriptions
Field Description
31–20
Reserved
This field is reserved. This read-only field is reserved and always has the value 0.
PWTCLKSEL
ADC_
E_EN
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SIM_CHIPCTL field descriptions (continued)
Field Description
19–18
RTC32KCLKSEL
17–16
PWTCLKSEL
15
Reserved
14
Reserved
13
PDB_BB_SEL
RTC 32K clock input select
00 OSC32 clock output 01 RTC_CLKIN 10 Reserved 11 Reserved
PWT clock source select
00 PWT alternative clock is from the TCLK0 pin. 01 PWT alternative clock is from the TCLK1 pin. 10 PWT alternative clock is from the TCLK2 pin. 11 Reserved
This field is reserved. This read-only field is reserved and always has the value 0.
This field is reserved. This read-only field is reserved and always has the value 0.
PDB back-to-back select
Selects ADC COCO source as pdb back-to-back mode, see Back-to-back acknowledge connectivity in PDB Inter-connectivity Information for details.
Chapter 5 System Integration Module (SIM)
12–11
Reserved
10–8
Reserved
7–6
CLKOUTSEL
5–4
CLKOUTDIV
3–2
Reserved
ADC_
INTERLEAVE_
EN
0 PDB0 channel 0 back-to-back operation with ADC0 COCO[1:0] and PDB0 channel 1 back-to-back
operation with ADC1 COCO[1:0]
1 PDB0 Channel 0 back-to-back operation with COCO[0] of ADC0 and COCO[1] of ADC1 ; PDB0
Channel 1 back-to-back operation with COCO[0] of ADC1 and COCO[1] of ADC0
This field is reserved. This read-only field is reserved and always has the value 0.
This field is reserved. This read-only field is reserved and always has the value 0.
CLKOUT Select
Selects the clock to output on the CLKOUT pin.
00 Reseved 01 SCGCLKOUT(SIRC/FIRC/SOSC/LPFLL), see SCG_CLKOUTCNFG register. 10 RTC oscillator (OSC32) clock (32 kHz) 11 LPO clock (128 kHz)
CLKOUT divider ratio
00 Divided by 1 01 Divided by 2 10 Divided by 4 11 Divided by 8
This field is reserved. This read-only field is reserved and always has the value 0.
ADC interleave channel enable
Select ADC interleave pins. Bit 1 to 0 are for PTB1 and PTB0 respectively.
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Memory map and register definition
SIM_CHIPCTL field descriptions (continued)
Field Description
00 No interleave channel Bit 1: PTB1 to ADC0_SE5 and ADC1_SE15 Bit 0: PTB0 to ADC0_SE4 and ADC1_SE14
5.2.2 FTM Option Register 0 (SIM_FTMOPT0)
Address: 4004_8000h base + Ch offset = 4004_800Ch
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
W
Reset
Bit
R
W
Reset
0 FTM2CLKSELFTM1CLKSELFTM0CLKSE
0
L
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0
FTM0FLTxSEL
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SIM_FTMOPT0 field descriptions
Field Description
31–30
Reserved
29–28
FTM2CLKSEL
27–26
FTM1CLKSEL
25–24
FTM0CLKSEL
This field is reserved. This read-only field is reserved and always has the value 0.
FTM2 External Clock Pin Select
Selects the external pin used to drive the clock to the FTM2 module.
NOTE:
The selected pin must also be configured for the FTM external clock function through the appropriate Pin Control Register in the Port Control module.
00 FTM2 external clock driven by TCLK0 pin. 01 FTM2 external clock driven by TCLK1 pin. 10 FTM2 external clock driven by TCLK2 pin. 11 No clock input
FTM1 External Clock Pin Select
Selects the external pin used to drive the clock to the FTM1 module.
NOTE:
The selected pin must also be configured for the FTM external clock function through the appropriate Pin Control Register in the Port Control module.
00 FTM1 external clock driven by TCLK0 pin. 01 FTM1 external clock driven by TCLK1 pin. 10 FTM1 external clock driven by TCLK2 pin. 11 No clock input
FTM0 External Clock Pin Select
Selects the external pin used to drive the clock to the FTM0 module.
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SIM_FTMOPT0 field descriptions (continued)
Field Description
NOTE:
00 FTM0 external clock driven by TCLK0 pin. 01 FTM0 external clock driven by TCLK1 pin. 10 FTM0 external clock driven by TCLK2 pin. 11 No clock input
23–3
Reserved
This field is reserved. This read-only field is reserved and always has the value 0.
FTM0FLTxSEL FTM0 Fault x Select
Selects the source of FTM0 fault. Every bit means one fault input respectively.
The selected pin must also be configured for the FTM external clock function through the appropriate Pin Control Register in the Port Control module.
Chapter 5 System Integration Module (SIM)
NOTE:
The pin source for fault must be configured for the FTM module fault function through the appropriate pin control register in the port control module when it comes from external fault pin.
TRGMUX_FTM0 SELx is corresponding to FTM0 Fault x input.
Bit value = 0: FTM0_FLTx pin Bit value = 1: TRGMUX_FTM0 out
5.2.3 ADC Options Register (SIM_ADCOPT)
Address: 4004_8000h base + 18h offset = 4004_8018h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reset
R
W
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bit
0 0
R
W
Reset
0
EL
ADC1PRETRGS
0
G
ADC1SWPRETR
ADC1TRGSEL
0
EL
ADC0PRETRGS
0
G
ADC0SWPRETR
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ADC0TRGSEL
SIM_ADCOPT field descriptions
Field Description
31–22
Reserved
NXP Semiconductors 67
This field is reserved. This read-only field is reserved and always has the value 0.
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SIM_ADCOPT field descriptions (continued)
Field Description
21–16
Reserved
15–14
Reserved
13–12
ADC1PRETRGSEL
11
Reserved
10–9
ADC1SWPRETRG
8
ADC1TRGSEL
This field is reserved. This read-only field is reserved and always has the value 0.
This field is reserved. This read-only field is reserved and always has the value 0.
ADC1 pre-trigger source select
Selects pre-trigger source for ADC1.
00 PDB output 01 TRGMUX output 10 ADC1 software pre-trigger 11 Reserved
This field is reserved. This read-only field is reserved and always has the value 0.
ADC1 software pre-trigger sources
00 disabled 01 software pre-trigger 0 10 software pre-trigger 1 11 disabled
ADC1 trigger source select
Selects trigger source for ADC1.
7–6
Reserved
5–4
ADC0PRETRGSEL
3
Reserved
2–1
ADC0SWPRETRG
0
ADC0TRGSEL
NOTE:
0 PDB output 1 TRGMUX output
This field is reserved. This read-only field is reserved and always has the value 0.
ADC0 pre-trigger source select
Selects pre-trigger source for ADC0.
00 PDB output 01 TRGMUX output 10 ADC0 software pre-trigger 11 Reserved
This field is reserved. This read-only field is reserved and always has the value 0.
ADC0 software pre-trigger sources
00 disabled 01 software pre-trigger 0 10 software pre-trigger 1 11 disabled
ADC0 trigger source select
Selects trigger source for ADC0.
Each PDB supports two ADC channels, and each channel is with 2 pre-triggers.
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Chapter 5 System Integration Module (SIM)
SIM_ADCOPT field descriptions (continued)
Field Description
NOTE:
Each PDB supports two ADC channels, and each channel is with 2 pre-triggers.
0 PDB output 1 TRGMUX output
5.2.4 FTM Option Register 1 (SIM_FTMOPT1)
Address: 4004_8000h base + 1Ch offset = 4004_801Ch
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reset
R
W
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bit
R
W
0
0
FTM2CH1SEL
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SIM_FTMOPT1 field descriptions
Field Description
31–24
Reserved
23–16
FTM0_OUTSEL
15–9
Reserved
8
FTM2CH1SEL
This field is reserved. This read-only field is reserved and always has the value 0.
FTM0 channel modulation select with FTM1_CH1
Bit 7 to 0 are for channel 7 to 0 respectively.
0 No modulation with FTM1_CH1 1 Modulation with FTM1_CH1
This field is reserved. This read-only field is reserved and always has the value 0.
FTM2 CH1 Select
Selects FTM2 CH1 input
FTM2CH0SEL
FTM0_OUTSEL
0
FTM1CH0SEL
FTM2SYNCBIT
FTM1SYNCBIT
FTM0SYNCBIT
0 FTM2_CH1 input 1 exclusive OR of FTM2_CH0, FTM2_CH1, and FTM1_CH1
7–6
FTM2 CH0 Select
FTM2CH0SEL
Selects FTM2 CH0 input
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Memory map and register definition
SIM_FTMOPT1 field descriptions (continued)
Field Description
00 FTM2_CH0 input 01 CMP0 output 10 CMP1 output 11 Reserved
5–4
FTM1CH0SEL
3
Reserved
2
FTM2SYNCBIT
1
FTM1SYNCBIT
FTM1 CH0 Select
Selects FTM1 CH0 input
00 FTM1_CH0 input 01 CMP0 output 10 CMP1 output 11 Reserved
This field is reserved. This read-only field is reserved and always has the value 0.
FTM2 Sync Bit
Software control for FTM2 hardware trigger synchronization
0 No effect. 1 Write 1 to assert the TRIG1 input to FTM2. Software must clear this bit to allow other trigger sources
to assert.
FTM1 Sync Bit
Software control for FTM1 hardware trigger synchronization
0
FTM0SYNCBIT
0 No effect. 1 Write 1 to assert the TRIG1 input to FTM1. Software must clear this bit to allow other trigger sources
to assert.
FTM0 Sync Bit
Software control for FTM0 hardware trigger synchronization
0 No effect. 1 Write 1 to assert the TRIG1 input to FTM0. Software must clear this bit to allow other trigger sources
to assert.
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Chapter 5 System Integration Module (SIM)
5.2.5 System Device Identification Register (SIM_SDID)
NOTE
Reset value loaded during System Reset from Flash IFR.
Address: 4004_8000h base + 24h offset = 4004_8024h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
FAMILYID SUBFAMID SERIESID RAMSIZE REVID PROJECTID PINID
W
Reset
x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* 0 0 0 1 0 x* x* x* x* x* x* x*
* Notes:
x = Undefined at reset.•
SIM_SDID field descriptions
Field Description
31–28
FAMILYID
Kinetis E-series Family ID
Specifies the Kinetis E-series family of the device.
0001 KE1x Family (Enhanced features)
27–24
SUBFAMID
23–20
SERIESID
19–16
RAMSIZE
15–12
REVID
11–7
PROJECTID
PINID Pin identification
Kinetis E-series Sub-Family ID
Specifies the Kinetis E-series sub-family of the device. Kinetis Series ID
Specifies the Kinetis series of the device.
0010 Kinetis E+ series RAM size
This field specifies the amount of system RAM available on the device.
0101 16 KB 0110 32 KB Others Reserved
Device revision number
Specifies the silicon implementation number for the device. Project ID
Specifies the silicon feature set identication number for the device. 00010 for this device.
Specifies the pin count of the device.
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SIM_SDID field descriptions (continued)
Field Description
0000111 64-pin 0001010 100-pin
5.2.6 Flash Configuration Register 1 (SIM_FCFG1)
NOTE
Reset values of NVMSIZE, PFSIZE, EEERAM_SIZE, DEPART are loaded during System Reset from Flash IFR.
NOTE
Reset values of EESIZE and DEPART are based on user programming in user IFR via the PGMPART flash command.
Address:
Reset
4004_8000h base + 4Ch offset = 4004_804Ch
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
W
Bit
R
W
NVMSIZE PFSIZE 0 EEERAMSIZE
x* x* x* x* x* x* x* x* 0 0 0 0 x* x* x* x*
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DEPART 0
FLASHDIS
FLASHDOZE
Reset
* Notes:
x = Undefined at reset.•
x* x* x* x* 0 0 0 0 0 0 0 0 0 0 0 0
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SIM_FCFG1 field descriptions
Field Description
31–28
NVMSIZE
27–24
PFSIZE
23–20
Reserved
19–16
EEERAMSIZE
15–12
DEPART
11–2
Reserved
1
FLASHDOZE
FlexNVM size
This field specifies the amount of FlexNVM memory available on the device. Undefined values are reserved.
0000 0 KB of FlexNVM 0011 32 KB of FlexNVM
Program flash size
This field specifies the amount of program flash memory available on the device . Undefined values are reserved.
0111 128 KB of program flash memory, 4 KB protection region 1001 256 KB of program flash memory, 8 KB protection region
This field is reserved. This read-only field is reserved and always has the value 0.
EEE SRAM SIZE
EEE SRAM data size .
0011 2 KB 0100 1 KB 0101 512 Bytes 0110 256 Bytes 0111 128 Bytes 1000 64 Bytes 1001 32 Bytes
FlexNVM partition
Data flash / EEPROM backup split . See DEPART bit description in FTFE chapter. This field is reserved.
This read-only field is reserved and always has the value 0. Flash Doze
When set, Flash memory is disabled for the duration of Doze mode. An attempt by the DMA or other bus master to access the Flash when the Flash is disabled will result in a bus error. This bit should be clear during VLP modes. The Flash will be automatically enabled again at the end of Doze mode so interrupt vectors do not need to be relocated out of Flash memory. The wakeup time from Doze mode is extended when this bit is set.
Chapter 5 System Integration Module (SIM)
0 Flash remains enabled during Doze mode 1 Flash is disabled for the duration of Doze mode
0
FLASHDIS
Flash Disable
Flash accesses are disabled (and generate a bus error) and the Flash memory is placed in a low power state. This bit should not be changed during VLP modes. Relocate the interrupt vectors out of Flash memory before disabling the Flash.
0 Flash is enabled 1 Flash is disabled
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Memory map and register definition
5.2.7 Flash Configuration Register 2 (SIM_FCFG2)
NOTE
Reset values of MAXADDR0 and MAXADDR1 are loaded during System Reset from Flash IFR.
Address: 4004_8000h base + 50h offset = 4004_8050h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
0 MAXADDR0 1 MAXADDR1
W
Reset
Reset
* Notes:
Reset value loaded during System Reset from Flash IFR.x = Undefined at reset.•
x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x*
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bit
R
W
x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x*
SIM_FCFG2 field descriptions
Field Description
31
Reserved
30–24
MAXADDR0
23
Reserved
22–16
MAXADDR1
Reserved This field is reserved.
This field is reserved. This read-only field is reserved and always has the value 0.
Max address block 0
This field concatenated with 13 trailing zeros indicates the first invalid address of program flash (block 0). For example, if MAXADDR0 = 0x10, the first invalid address of program flash (block 0) is 0x0002_0000.
This would be the MAXADDR0 value for a device with 128 KB program flash in flash block 0. This field is reserved.
This read-only field is reserved and always has the value 1. Max address block 1
This field concatenated with 13 trailing zeros indicates the first invalid address of data flash (block 1).
This read-only field is reserved and always has the value 0.
0
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Chapter 5 System Integration Module (SIM)
5.2.8 Unique Identification Register High (SIM_UIDH)
Address: 4004_8000h base + 54h offset = 4004_8054h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
Reset
0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0*
* Notes:
Reset value loaded during System Reset from Flash IFR.•
SIM_UIDH field descriptions
Field Description
UID127_96 Unique Identification
Unique identification for the device.
UID127_96
5.2.9 Unique Identification Register Mid-High (SIM_UIDMH)
Address: 4004_8000h base + 58h offset = 4004_8058h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
Reset
0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0*
* Notes:
Reset value loaded during System Reset from Flash IFR.•
SIM_UIDMH field descriptions
Field Description
UID95_64 Unique Identification
Unique identification for the device.
UID95_64
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5.2.10 Unique Identification Register Mid Low (SIM_UIDML)
Address: 4004_8000h base + 5Ch offset = 4004_805Ch
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
Reset
0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0*
* Notes:
Reset value loaded during System Reset from Flash IFR.•
SIM_UIDML field descriptions
Field Description
UID63_32 Unique Identification
Unique identification for the device.
UID63_32
5.2.11 Unique Identification Register Low (SIM_UIDL)
Address: 4004_8000h base + 60h offset = 4004_8060h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
Reset
0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0*
* Notes:
Reset value loaded during System Reset from Flash IFR.•
SIM_UIDL field descriptions
Field Description
UID31_0 Unique Identification
Unique identification for the device.
UID31_0
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Chapter 5 System Integration Module (SIM)
5.2.12 Miscellaneous Control register (SIM_MISCTRL)
Address: 4004_8000h base + 6Ch offset = 4004_806Ch
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reset
Bit
Reset
R
W
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0
SIM_MISCTRL field descriptions
Field Description
31–19
Reserved
18
UART2ODE
17
UART1ODE
16
UART0ODE
15–8
Reserved
7–4
DMA_INT_SEL
This field is reserved. This read-only field is reserved and always has the value 0.
UART2 Open Drain Enable
0 Open drain is disabled on UART2 1 Open drain is enabled on UART2
UART1 Open Drain Enable
0 Open drain is disabled on UART1 1 Open drain is enabled on UART1
UART0 Open Drain Enable
0 Open drain is disabled on UART0 1 Open drain is enabled on UART0
This field is reserved. This read-only field is reserved and always has the value 0.
DMA channel interrupt OR select
Bit 7 of
DMA channel 7 and channel 3 interrupt select bit (logic 1 is ch7 and logic 0 is ch3)
SIM_MISCTRL Bit 6 of
DMA channel 6 and channel 2 interrupt select bit (logic 1 is ch6 and logic 0 is ch2)
SIM_MISCTRL Bit 5 of
DMA channel 5 and channel 1 interrupt select bit (logic 1 is ch5 and logic 0 is ch1)
SIM_MISCTRL Bit 4 of
DMA channel 4 and channel 0 interrupt select bit (logic 1 is ch4 and logic 0 is ch0)
SIM_MISCTRL
DMA_INT_SEL
UART2ODE
UART1ODE
0
UART0ODE
SW_ TRG
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SIM_MISCTRL field descriptions (continued)
Field Description
3–1
Reserved
0
SW_TRG
This field is reserved. This read-only field is reserved and always has the value 0.
Software Trigger bit to TRGMUX
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Chapter 6 Memory-Mapped Divide and Square Root (MMDVSQ)

6.1 Chip-specific Information for this Module

In this block chapter, PBRIDGE stands for the Peripheral Bridge, with the same meaning as AIPS-Lite.
6.2
ARM processor cores in the Cortex-M family implementing the ARMv6-M instruction set architecture do not include hardware support for integer divide operations. The affected processors include the Cortex-M0+ core. However, in certain deeply embedded application spaces, hardware support for this class of arithmetic operation (along with an unsigned square root function) is important to maximize system performance and minimize device power dissipation. Accordingly, the MMDVSQ module is included in select microcontrollers, to serve as a memory-mapped co-processor located in a special address space (within the system memory map) that is accessible only to the processor core.
The MMDVSQ module supports execution of the integer divide operations defined in the ARMv7-M instruction set architecture, plus an unsigned integer square root operation. The supported integer divide operations include 32/32 signed (SDIV) and unsigned (UDIV) calculations.
6.2.1

Introduction

Features
The key features of the MMDVSQ include:
• Lightweight implementation of 32-bit integer divide and square root arithmetic operations
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Introduction
• Supports 32/32 signed and unsigned divide (or remainder) calculations
• Supports 32-bit unsigned square root calculations
• Simple programming model includes input data and result registers plus a control/ status register
• Programming model interface optimized for activation from inline code or software library call
• "Fast Start" configuration minimizes the memory-mapped register write overhead
• Supports two methods to determine when result is valid, including software polling
• Configurable divide-by-zero response
• Pipelined design processes 2 bits per cycle with early termination exit for minimum execution time
6.2.2
Block diagram
A generic block diagram of the processor core and platform for this class of ultra low-end microcontrollers is shown in Figure 6-1. The MMDVSQ module’s location as a memory­mapped co-processor is highlighted.
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AXBS
CM0+ Core Platform
FMC
LD/ST
Dbg
Cortex-M0+ Core
AHB Bus
AGU
RAM
Array
32
Dec
SHFT
ALU
DMA_4ch
NVM Array
PRAM
32
GPIO
PBRIDGE
BME
32
IO Port
Slave Peripherals
Alt-Master
-Lite
m0
s1
s2
s0
m3
m2
NVIC
Fetch
Rn
MUL
MTB Port
MTB
MCM
MMDVSQ
Chapter 6 Memory-Mapped Divide and Square Root (MMDVSQ)
Figure 6-1. Generic Cortex-M0+ Core Platform Block Diagram
Next, a block diagram of the internal structure of the MMDVSQ module is presented. See
Figure 6-2.
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HWDATA[31:0]
DEND,RCND
DSOR
CSR
<< 1
<< 1
ABS(x)
CNTL
-
-
HWDATA
RES
HRDATA[31:0]
Introduction
Figure 6-2. MMDVSQ Block Diagram
6.2.3
Modes of operation
The MMDVSQ module does not support any special modes of operation. As a memory­mapped device located on a crossbar slave AHB system bus port, MMDVSQ responds based strictly on memory addresses to its programming model.
All functionality associated with the MMDVSQ module resides in the core platform’s clock domain; this includes its connections with the crossbar slave port. To minimize power dissipation, the design supports an architectural clock gate for the entire module, that is, the MMDVSQ is only clocked when responding to bus requests to its programming model or is busy performing a calculation.
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6.3 External signal description

The MMDVSQ module does not directly support any external interfaces. The internal interface includes a standard 32-bit AHB bus as shown in Figure 6-1.

6.4 Memory map and register definition

The MMDVSQ module supports a small number of program-visible registers used for passing input operands and retrieving the output result plus a configuration/status register.
The programming model occupies the first 20 bytes of a standard 4 Kb address slot. It can only be accessed via word-sized (32 bit) accesses. Attempted accesses using smaller data sizes, reading the write-only location or to reserved space are terminated with an error.
At any instant in time, the MMDVSQ can perform either a divide or square root calculation. The basic integer operations supported by the MMDVSQ are:
For divide:
MMDVSQ_RES = quotient (MMDVSQ_DEND / MMDVSQ_DSOR)
MMDVSQ_RES = remainder (MMDVSQ_DEND % MMDVSQ_DSOR)
For square root:
MMDVSQ_RES = integer (√MMDVSQ_RCND)
The register usage, based on the operation (divide, square root), is detailed in Table 6-1.
Table 6-1. Register Usage = f(Divide, Square Root)
Register Divide Square
Root
Dividend (MMDVSQ_DEND) Yes No Input dividend (numerator) for the divide Divisor (MMDVSQ_DSOR) Yes No Input divisor (denominator) for the divide Control/Status (MMDVSQ_CSR) Yes Yes Control for divide, status for divide and square
Result (MMDVSQ_RES) Yes Yes Output result Radicand (MMDVSQ_RCND) No Yes Input "square" data
Description
root
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MMDVSQ memory map
Absolute
address
(hex)
F000_4000 Dividend Register (MMDVSQ_DEND) 32 R/W Undefined 6.4.1/84 F000_4004 Divisor Register (MMDVSQ_DSOR) 32 R/W Undefined 6.4.2/84 F000_4008 Control/Status Register (MMDVSQ_CSR) 32 R/W See section 6.4.3/86
F000_400C Result Register (MMDVSQ_RES) 32 R/W Undefined 6.4.4/89
F000_4010 Radicand Register (MMDVSQ_RCND) 32 W Undefined 6.4.5/89
Register name
Width
(in bits)
Access Reset value
Section/
page
6.4.1 Dividend Register (MMDVSQ_DEND)
This register is loaded with the input dividend operand before a divide operation is initiated. The register is updated by the MMDVSQ hardware during the execution of a divide or square root calculation. Any memory access (read or write) of the DEND register while the module is busy during a calculation causes the access to be stalled (using wait states) until the calculation completes.
Address:
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
Reset
F000_4000h base + 0h offset = F000_4000h
DIVIDEND
x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x*
* Notes:
x = Undefined at reset.•
MMDVSQ_DEND field descriptions
Field Description
DIVIDEND Dividend
This is the input dividend operand for divide calculations.
6.4.2 Divisor Register (MMDVSQ_DSOR)
This register is loaded with the input divisor operand before a divide operation is initiated. If CSR[DFS] = 0, a write to this register inititates a divide operation. Any memory access (read or write) of the DSOR register while the module is busy during a calculation causes the access to be stalled (using wait states) until the calculation completes.
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If a divide operation is inititated with DSOR = 0, the hardware signals a divide-by-zero condition and sets RES = 0 and CSR[DZ] = 1. If CSR[DZE] = 1, an attempted read of the RES result is error terminated.
Address: F000_4000h base + 4h offset = F000_4004h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
Reset
x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x*
* Notes:
x = Undefined at reset.•
MMDVSQ_DSOR field descriptions
Field Description
DIVISOR Divisor
This is the input divisor operand for divide calculations.
DIVISOR
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Memory map and register definition
6.4.3 Control/Status Register (MMDVSQ_CSR)
This register defines the operating configuration of divide operations and provides status information. The upper 3 bits provide busy status indicators, while the low-order byte defines the configuration for divide operations. The read-only status bits in CSR[31:29] are valid for both divide and square root operations; the configuration and status bit in CSR[5:0] are only valid for divides. A memory write access of the CSR register while the module is busy during a calculation causes the access to be stalled (using wait states) until the calculation completes.
Address:
Reset
F000_4000h base + 8h offset = F000_4008h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
W
Bit
R
W
DIV
BUSY
0 x* x* 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SQRT
0
0
DZ
DFS
DZE REM
0
USGN
SRT
Reset
* Notes:
x = Undefined at reset.•
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
MMDVSQ_CSR field descriptions
Field Description
31
BUSY
86 NXP Semiconductors
BUSY
This read-only bit is asserted when the MMDVSQ is performing a divide or square root. When an operation is initiated, the hardware sets this flag. It remains asserted until the operation completes and the
Table continues on the next page...
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MMDVSQ_CSR field descriptions (continued)
Field Description
hardware automatically clears the indicator. This bit can be used to poll the DVSQ’s execution status. The combined CSR[BUSY, DIV, SQRT] indicators provide an encoded module status:
• If 0b001, then MMDVSQ is idle and the last calculation was a square root
• If 0b010, then MMDVSQ is idle and the last calculation was a divide
• If 0b101, then MMDVSQ is busy processing a square root calculation
• If 0b110, then MMDVSQ is busy processing a divide calculation
The remaining encodings of CSR[BUSY, DIV, SQRT] are reserved.
0 MMDVSQ is idle 1 MMDVSQ is busy performing a divide or square root calculation
30
DIV
29
SQRT
DIVIDE
Current or last operation was a divide. This read-only indicator bit signals if the current or last operation performed by the MMDVSQ was a divide.
0 Current or last MMDVSQ operation was not a divide 1 Current or last MMDVSQ operation was a divide
SQUARE ROOT
Current or last operation was a square root. This read-only indicator bit signals if the current or last operation performed by the MMDVSQ was a square root.
28–6
Reserved
5
DFS
4
DZ
3
DZE
0 Current or last MMDVSQ operation was not a square root 1 Current or last MMDVSQ operation was a square root
This field is reserved. This read-only field is reserved and always has the value 0.
Disable Fast Start
The MMDVSQ supports 2 mechanisms for initiating a divide operation. The default mechanism is a “fast start” where a write to the DSOR register begins the divide. Alternatively, the start mechanism can begin after a write to the CSR register with CSR[SRT] set. The CSR[DFS] indicator selects the divide start mechanism.
0 A divide operation is initiated by a write to the DSOR register 1 A divide operation is initiated by a write to the CSR register with CSR[SRT] = 1
Divide-by-Zero
This read-only status indicator signals the last divide operation had a zero divisor, that is, DSOR = 0x0000_0000. For this case, RES is set to 0x0000_0000 and this indicator bit set. After a divide-by-zero operation, a read of the RES register returns either the zero result, or, if CSR[DZE] = 1, terminates the read with an error. The CSR[DZ] indicator is cleared by the hardware at the beginning of each operation.
0 The last divide operation had a non-zero divisor, that is, DSOR != 0 1 The last divide operation had a zero divisor, that is, DSOR = 0
Divide-by-Zero-Enable
This indicator configures the MMDVSQ’s response to divide-by-zero calculations. If both CSR[DZ] and CSR[DZE] are set, then a subsequent read of the RES register is error terminated to signal the processor of the attempted divide-by-zero.
Table continues on the next page...
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MMDVSQ_CSR field descriptions (continued)
Field Description
0 Reads of the RES register return the register contents 1 If CSR[DZ] = 1, an attempted read of RES register is error terminated to signal a divide-by-zero, else
the register contents are returned
2
REM
1
USGN
0
SRT
REMainder calculation
This indicator selects whether the quotient or the remainder is returned in the RES register. The combined CSR[REM] and CSR[USGN] bits define four possible divide operations:
• If CSR[REM, USGN] = 0b00, perform a signed divide, returning the quotient
• If CSR[REM, USGN] = 0b01, perform an unsigned divide, returning the quotient
• If CSR[REM, USGN] = 0b10, perform a signed divide, returning the remainder
• If CSR[REM, USGN] = 0b11, perform an unsigned divide, returning the remainder
0 Return the quotient in the RES for the divide calculation 1 Return the remainder in the RES for the divide calculation
Unsigned calculation
This indicator selects whether a signed (default) or unsigned divide is performed. See the CSR[REM] description for the encoding of the four possible divide operations.
0 Perform a signed divide 1 Perform an unsigned divide
Start
When written with a logical one and CSR[DFS] = 1, this flag initiates a divide operation. If written as a logical one with CSR[DFS] = 0, it is ignored. This bit always reads as a zero. The state of the register write data defines this bit’s function.
0 No operation initiated 1 If CSR[DFS] = 1, then initiate a divide calculation, else ignore
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6.4.4 Result Register (MMDVSQ_RES)
This register is loaded with the result of the divide or square root calculation. It is updated by the MMDVSQ hardware at the completion of the calculation. When a square root operation is performed (on an unsigned 32-bit number), the result is limited to a 16­bit value with RES[31:16] = 0x0000. Any memory access (read or write) of the RES register while the module is busy during a calculation causes the access to be stalled (using wait states) until the calculation completes and the new result written into the register.
Address:
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
Reset
* Notes:
F000_4000h base + Ch offset = F000_400Ch
RESULT
x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x*
x = Undefined at reset.•
MMDVSQ_RES field descriptions
Field Description
RESULT Result
This is the output result for a divide or square root calculation.
6.4.5 Radicand Register (MMDVSQ_RCND)
The write-only radicand register is loaded with the input “square” number. A memory write to the radicand register initiates a square root calculation. While the MMDVSQ module is busy performing a square root calculation, any memory write access to the RCND register causes the write access to be stalled (using wait states) until the square root calculation finishes. Any attempted read of the radicand register terminates with an error.
Address:
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
Reset
* Notes:
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F000_4000h base + 10h offset = F000_4010h
RADICAND
x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x*
x = Undefined at reset.•
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Functional description

MMDVSQ_RCND field descriptions
Field Description
RADICAND Radicand
This is the input radicand for a square root calculation, that is, the input "square" number.
6.5 Functional description
This section details the algorithms, execution times of the MMDVSQ, and the software interface to the module.
6.5.1
Algorithms
This section provides more details on the integer divide and square root algorithms.
6.5.1.1
6.5.1.1.1
Integer divide including special cases
Overview
The MMDVSQ module implements a "shift, test, and restore" radix-2 algorithm for unsigned integer divide operations. When performing a signed divide calculation, negative input operands are converted into 2’s complement positive numbers first, an unsigned divide performed, and the sign of the results based on the input operand signs, namely:
• The sign of the remainder is the same as the sign of the dividend
• The quotient is negated if the signs of the dividend and divisor are different
The hardware implementation processes two bits per machine cycle and includes "early termination" logic where the execution time is data dependent, based on the magnitude of the positive dividend. See Table 6-4 for more execution time details.
6.5.1.1.2
Special case: Overflow
There is a single "special overflow case" affecting signed integer divides. If the dividend = 0x8000_0000 and the divisor = 0xFFFF_FFFF, the result of this (-231/-1) operation cannot be expressed as a 32-bit 2’s complement number. For this case, the MMDVSQ exactly follows the ARM Cortex-Mx definition and returns 0x8000_0000 (the lower 32 bits of the +231 result) as the quotient with no indication of the overflow condition. If the remainder is selected as the output of this calculation, it returns 0x0000_0000.
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6.5.1.1.3 Special case: Divide-by-Zero
For both signed and unsigned divides, if the divisor is zero, the MMDVSQ hardware detects this condition and the CSR[DZ] indicator set. The quotient result is forced to 0x0000_0000. If the remainder is selected as the output of this calculation, it also returns 0x0000_0000. Additionally, if CSR[DZE] = 1, then an attempted read of the Result register (RES) is error terminated to provide a simple mechanism to signal software of the divide-by-zero condition.
6.5.1.2
Integer square root
6.5.1.2.1 Overview
The unsigned square root algorithm begins by creating a 32-bit “one-hot” bit vector signaling the highest power of four of the contents of the Radicand register (RCND). It then iterates through an algorithm involving magnitude comparisons of the RCND register versus the working result plus bit vector summation, conditional decrementing of the radicand, a 1-bit right shift of the result, and a 2-bit right shift of the one-hot bit vector.
Processing two bits of the radicand per cycle, the result register finishes with the integer portion of the square root calculation. The module includes early termination logic so that the execution time is data dependent, based on the magnitude of the input radicand. See
Table 6-5 for more execution time details. Since both algorithms share common hardware
structures, the incremental cost of the square root logic is an extremely small delta to the basic divide hardware.
The square root algorithm was exhaustively compared (that is, all 232 possible input values) against the standard GNU C library implementation, which converts the unsigned integer input into a double-precision floating-point number, calculates the double­precision square root and then converts it back into an unsigned integer. Each input value calculated identical square root results.
6.5.1.2.2
Square root using Q notation
Consider the use of Q notation for square root calculations returning fractional values. The following description is taken from http://en.wikipedia.org/wiki/Q_(number_format).
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Q is a fixed point number format where the number of fractional bits (and optionally the number of integer bits) is specified. For example, a Q15 number has 15 fractional bits; a Q1.14 number has 1 integer bit and 14 fractional bits. Q format is often used in hardware that does not have a floating-point unit and in applications that require constant resolution.
Q format numbers are (notionally) fixed point numbers (but not actually a number itself); that is, they are stored and operated upon as regular binary numbers (i.e. signed integers), thus allowing standard integer hardware/ALU to perform rational number calculations. The number of integer bits, fractional bits and the underlying word size are to be chosen by the programmer on an application-specific basis - the programmer's choices of the foregoing will depend on the range and resolution needed for the numbers. The machine itself remains oblivious to the notional fixed point representation being employed - it merely performs integer arithmetic the way it knows how. Ensuring that the computational results are valid in the Q format representation is the responsibility of the programmer.
The Q notation is written as Qm.n, where:
•
Q designates that the number is in the Q format notation - the Texas Instruments representation for signed fixed-point numbers (the “Q” being reminiscent of the standard symbol for the set of rational numbers).
•
m is the number of bits set aside to designate the two's complement integer portion of the number, exclusive of the sign bit (therefore if m is not specified it is taken as zero).
•
n is the number of bits used to designate the fractional portion of the number, i.e. the number of bits to the right of the binary point. (If n = 0, the Q numbers are integers ­the degenerate case).
Note that the most significant bit is always designated as the sign bit (the number is stored as a two's complement number) in order to allow standard arithmetic-logic hardware to manipulate Q numbers. Representing a signed fixed-point data type in Q format therefore always requires m+n+1 bits to account for the sign bit. Hence the smallest machine word size required to accommodate a Qm.n number is m+n+1, with the Q number left justified in the machine word.
For a given Qm.n format, using an m+n+1 bit signed integer container with n fractional bits:
•
its range is [-2m, 2m - 2-n]
•
its resolution is 2
-n
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For the unsigned integer format used in the MMDVSQ's square root calculation, an u(nsigned)Qm.n notation requires m+n bits (m+n = 32) for the input radicand. An uQm.n format produces an uQ(m/2).(n/2) square root. As examples, consider the following tables involving the square root of 2 and square root of “pi” calculations. As expected, as the number of fractional bits (n) increases, the error between the calculated square root and the “actual” result decreases.
Table 6-2. Square Root of 2 Calculations (√2 = 1.4142135623)
RCND [Hex] RCND Q format Results [Hex] RES Q Format Decimal % Error
0x0000_0002 uQ32.00 0x0000_0001 uQ16.00 1.0 -29.289% 0x0002_0000 uQ16.16 0x0000_016A uQ08.08 1.4140625 -0.011% 0x0200_0000 uQ08.24 0x0000_16A0 uQ04.12 1.4140625 -0.011% 0x2000_0000 uQ04.28 0x0000_5A82 uQ02.14 1.4141845703 -0.002% 0x8000_0000 uQ02.30 0x0000_B504 uQ01.15 1.4141845703 -0.002%
Table 6-3. Square Root of Pi Calculations (√Pi = 1.7724538509)
RCND [Hex] RCND Q format Results [Hex] RES Q Format Decimal % Error
0x0000_0003 uQ32.0 0x0000_0001 uQ16.00 1.0 -43.581% 0x0003_243F uQ16.16 0x0000_01C5 uQ08.08 1.76953125 -0.165% 0x0324_3F6A uQ08.24 0x0000_1C5B uQ04.12 1.772216769 -0.013% 0x3243_F6A8 uQ04.28 0x0000_716F uQ02.14 1.7723999023 -0.003%
0xC90F_DAA0 uQ02.30 0x0000_E2DF uQ01.15 1.7724304199 -0.001%
The application of the Q notation for square root calculations provides a powerful extension for these types of fractional numeric computations using fixed-point integer processing hardware.
6.5.2
Execution times
The MMDVSQ module includes early termination logic to finish both divide and square root calculations as quickly as possible, based on the magnitude of the input operand. Accordingly, the execution time for the calculations is data dependent as defined in Table
6-4 and Table 6-5. In this context, the execution time is defined from the register write to
initiate the calculation until the result register has been updated and available to read. Stated differently, it represents the time CSR[BUSY] is asserted for a given calculation. In the following two tables, “x” signals a bit with a don’t care value.
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Table 6-4. Divide Execution Times
? DEND[31:0] // unsigned divide
CSR[USGN]
: abs(DEND[31:0]) // signed divide
(01,1x)xx_xxxx_xxxx_xxxx__xxxx_xxxx_xxxx_xxxx 17 00(01,1x)_xxxx_xxxx_xxxx__xxxx_xxxx_xxxx_xxxx 16 0000_(01,1x)xx_xxxx_xxxx__xxxx_xxxx_xxxx_xxxx 15 0000_00(01,1x)_xxxx_xxxx__xxxx_xxxx_xxxx_xxxx 14 0000_0000_(01,1x)xx_xxxx__xxxx_xxxx_xxxx_xxxx 13 0000_0000_00(01,1x)_xxxx__xxxx_xxxx_xxxx_xxxx 12 0000_0000_0000_(01,1x)xx__xxxx_xxxx_xxxx_xxxx 11 0000_0000_0000_00(01,1x)__xxxx_xxxx_xxxx_xxxx 10 0000_0000_0000_0000__(01,1x)xx_xxxx_xxxx_xxxx 9 0000_0000_0000_0000__00(01,1x)_xxxx_xxxx_xxxx 8 0000_0000_0000_0000__0000_(01,1x)xx_xxxx_xxxx 7 0000_0000_0000_0000__0000_00(01,1x)_xxxx_xxxx 6 0000_0000_0000_0000__0000_0000_(01,1x)xx_xxxx 5 0000_0000_0000_0000__0000_0000_00(01,1x)_xxxx 4 0000_0000_0000_0000__0000_0000_0000_(01,1x)xx 3 0000_0000_0000_0000__0000_0000_0000_00(01,1x) 2 0000_0000_0000_0000__0000_0000_0000_0000 1
Execution Time with CSR[BUSY] = 1 [cycles]
Table 6-5. Square Root Execution Times
RCND[31:0] Execution Time with CSR[BUSY] = 1 [cycles]
(01,1x)xx_xxxx_xxxx_xxxx__xxxx_xxxx_xxxx_xxxx 17 00(01,1x)_xxxx_xxxx_xxxx_x_xxx_xxxx_xxxx_xxxx 16 0000_(01,1x)xx_xxxx_xxxx__xxxx_xxxx_xxxx_xxxx 15 0000_00(01,1x)_xxxx_xxxx__xxxx_xxxx_xxxx_xxxx 14 0000_0000_(01,1x)xx_xxxx__xxxx_xxxx_xxxx_xxxx 13 0000_0000_00(01,1x)_xxxx__xxxx_xxxx_xxxx_xxxx 12 0000_0000_0000_(01,1x)xx__xxxx_xxxx_xxxx_xxxx 11 0000_0000_0000_00(01,1x)__xxxx_xxxx_xxxx_xxxx 10 0000_0000_0000_0000__(01,1x)xx_xxxx_xxxx_xxxx 9 0000_0000_0000_0000__00(01,1x)_xxxx_xxxx_xxxx 8 0000_0000_0000_0000__0000_(01,1x)xx_xxxx_xxxx 7 0000_0000_0000_0000__0000_00(01,1x)_xxxx_xxxx 6 0000_0000_0000_0000__0000_0000_(01,1x)xx_xxxx 5 0000_0000_0000_0000__0000_0000_00(01,1x)_xxxx 4 0000_0000_0000_0000__0000_0000_0000_(01,1x)xx 3 0000_0000_0000_0000__0000_0000_0000_00(01,1x) 2 0000_0000_0000_0000__0000_0000_0000_0000 2
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6.5.3 Software interface
The programming model of the MMDVSQ is organized to be similar to the input arguments passed to software libraries for integer divide and square root functions.
6.5.3.1 Operation activation and result retrieval
The MMDVSQ supports 2 mechanisms for initiating a divide operation:
• The default mechanism is a "fast start" where a write to the DSOR register begins the divide.
• Alternatively, the start mechanism can begin after a write to the CSR register with the CSR[SRT] set.
The CSR[DFS] indicator selects the divide start mechanism.
if CSR[DFS] = 0 then a divide is initiated by a write to the DSOR register else a divide is initiated by a write to the CSR register with CSR[SRT] = 1
A square root calculation is initiated by a write to the RCND register. For both divide and square root calculations, the result of the operation is retrieved by
reading the RES register. A memory read of this register while the calculation is still being performed causes the access to be stalled via the insertion of bus wait states until the new result is loaded into the register. Note a stalled bus cycle cannot be interrupted, so if system interrupt latency is a concern, the processor should execute a simple wait loop, for example, polling CSR[BUSY], before reading the RES register. This code construct is fully interruptible, so interrupt latency is minimized.
6.5.3.2
Context save and restore
Given that multiple memory-mapped register accesses are needed for each divide and square root calculation, interrupts may occur during the required sequence of operations. As a result, the MMDVSQ’s programming model can be saved at entry to an interrupt service routine (ISR) and then restored when redispatching to the interrupted task.
The module’s context can be saved by reading the DEND, DSOR, CSR, and RES registers and storing them as part of the task state. There is one special consideration for the task state save. If the last calculation was a zero divide and the divide-by-zero enable is set (CSR[DZE] = 1), then a read of the RES register is error terminated. To avoid a zero-divide error termination during a context save, the following sequence can be used:
1. Read DEND, DSOR, and CSR registers and save the values as part of the task state.
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2. Clear CSR[DZE].
3. Read the RES register and save its value as part of the task state.
When restoring the context, special care must be taken to not initiate another divide calculation. Specifically, CSR[DFS] must be set first before reloading the DEND and DSOR registers. For example, the following sequence can be used for the context reload:
1. Write 0x0000_0020 to the CSR to disable the fast start mechanism.
2. Reload DEND, DSOR, CSR, and RES registers from the saved state.
Since the original context save of the control/status register is guaranteed to have CSR[SRT] = 0, there is no divide operation initiated when this register is reloaded in step
2.
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Chapter 7
AXBS
CM0+ Core Platform
FAU
(FMC)
LD/ST
Dbg
Cortex-M0+ Core
AHB Bus
AGU
RAM
Array
32
Dec
SHFT
ALU
DMA_4ch
NVM Array
PRAM
32
GPIO
PBRIDGE
BME
32
IO Port
Slave Peripherals
Alt-Master
-Lite
m0
s1
s2
s0
m3
m2
NVIC
Fetch
Rn
MUL
MTB Port
MTB
MCM
MMDVSQ
Miscellaneous Control Module (MCM)

7.1 Chip-specific Information for this Module

A generic block diagram of the processor core and platform for this class of microcontrollers is shown in the following figure. The MCM module's location is highlighted.
Figure 7-1. Cortex-M0+ core platform block diagram
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Introduction

7.2 Introduction
The Miscellaneous Control Module (MCM) provides a myriad of miscellaneous control functions.
7.2.1 Features
The MCM includes the following features:
• Program-visible information on the platform configuration
• Crossbar master arbitration policy selection
• Flash controller speculation buffer and cache configurations
7.3

Memory map/register descriptions

The memory map and register descriptions found here describe the registers using byte addresses. The registers can be written only when in supervisor mode.
MCM memory map
Absolute
address
(hex)
F000_3008
F000_300A
F000_300C Platform Control Register (MCM_PLACR) 32 R/W 0000_0250h 7.3.3/100
F000_3040 Compute Operation Control Register (MCM_CPO) 32 R/W 0000_0000h 7.3.4/103
Crossbar Switch (AXBS) Slave Configuration (MCM_PLASC)
Crossbar Switch (AXBS) Master Configuration (MCM_PLAMC)
Register name
Width
(in bits)
Access Reset value
16 R 0007h 7.3.1/99
16 R 0005h 7.3.2/99
Section/
page
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Chapter 7 Miscellaneous Control Module (MCM)
7.3.1 Crossbar Switch (AXBS) Slave Configuration (MCM_PLASC)
PLASC is a 16-bit read-only register identifying the presence/absence of bus slave connections to the device’s crossbar switch.
Address: F000_3000h base + 8h offset = F000_3008h
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Read 0 ASC
Write
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1
MCM_PLASC field descriptions
Field Description
15–8
Reserved
ASC Each bit in the ASC field indicates whether there is a corresponding connection to the crossbar switch's
This field is reserved. This read-only field is reserved and always has the value 0.
slave input port.
0 A bus slave connection to AXBS input port n is absent. 1 A bus slave connection to AXBS input port n is present.
7.3.2 Crossbar Switch (AXBS) Master Configuration (MCM_PLAMC)
PLAMC is a 16-bit read-only register identifying the presence/absence of bus master connections to the device's crossbar switch.
Address:
Read 0 AMC
Write
Reset
F000_3000h base + Ah offset = F000_300Ah
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1
MCM_PLAMC field descriptions
Field Description
15–8
Reserved
AMC Each bit in the AMC field indicates whether there is a corresponding connection to the AXBS master input
This field is reserved. This read-only field is reserved and always has the value 0.
port.
Table continues on the next page...
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Memory map/register descriptions
MCM_PLAMC field descriptions (continued)
Field Description
0 A bus master connection to AXBS input port n is absent 1 A bus master connection to AXBS input port n is present
7.3.3 Platform Control Register (MCM_PLACR)
The PLACR register selects the arbitration policy for the crossbar masters and configures the flash memory controller.
The speculation buffer and cache in the flash memory controller is configurable via PLACR[15:10 ].
The speculation buffer is enabled only for instructions after reset. It is possible to have these states for the speculation buffer:
DFCS EFDS Description
0 0 Speculation buffer is on for instruction
and off for data.
0 1 Speculation buffer is on for instruction
and on for data.
1 X Speculation buffer is off.
The cache in flash controller is enabled and caching both instruction and data type fetches after reset. It is possible to have these states for the cache:
DFCC DFCIC DFCDA Description
0 0 0 Cache is on for both
instruction and data.
0 0 1 Cache is on for instruction
and off for data.
0 1 0 Cache is off for instruction
and on for data.
0 1 1 Cache is off for both
instruction and data.
1 X X Cache is off.
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