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NXP Semiconductors
Document Number: IMX8MM
EVKHUG
User's Guide
0
,
Contents
1. Introduction ........................................................................ 1
i.MX 8M Mini LPDDR4 EVK Board Hardware
User's Guide
1. Introduction
This document is the hardware User’s Guide for the
i.MX 8M Mini LPDDR4 Evaluation Kit (EVK) based
on the NXP Semiconductor’s i.MX 8M Mini
Applications Processor. This board is fully supported by
NXP Semiconductor. This manual includes system
setup and configurations, and provides detailed
information on the overall design and usage of the EVK
board from a hardware system perspective.
1.1.
Board overview
The LPDDR4 EVK board is a platform designed to
show the most commonly used features of the i.MX 8M
Mini Applications Processor in a small and low cost
package. The i.MX 8M Mini LPDDR4 EVK board is an
entry level development board, which helps developers
get familiar with the processor before investing a large
amount of resources in more specific designs.
Table 1 lists the features of the i.MX 8M Mini
LPDDR4 EVK board.
Rev.
1.1. Board overview ....................................................... 1
1.2. Board contents ........................................................ 2
2. Specifications ..................................................................... 2
Processor ............................................................................... 5
2.1. Boot Mode and Boot Device configurations ........... 5
2.2. Power Tree .............................................................. 9
2.3. LPDDR4 DRAM memory .................................... 10
2.4. eMMC memory (U4) ............................................ 11
2.5. QSPI Nor Flash (U5) ............................................ 11
2.6. SD card slot (J701) ............................................... 11
2.7. MIPI-CSI&MIPI-DSI connectors (J802, J801) ..... 11
2.8. Ethernet connector (J501) ..................................... 11
2.9. USB connector (J301, J302) ................................. 11
2.10. Wi-Fi/Bluetooth (U6)............................................ 12
2.11. Audio Line output (J401) ...................................... 12
2.12. Audio Card connector (J1001) .............................. 12
2.13. JTAG connector (J902) ......................................... 12
2.14. USB-UART connector (J901) ............................... 12
2.15. M.2 connector (J601) ............................................ 13
2.16. Expansion connector (J1003) ................................ 13
2.17. I2C connector (J1004)........................................... 13
2.18. User interface buttons ........................................... 14
2.19. User interface LED indicators ............................... 14
3. PCB information .............................................................. 15
3.1. EVK design files ................................................... 16
4. Errata................................................................................ 17
5. Revision History .............................................................. 17
2/2019
© 2019 NXP B.V.
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Specifications
Table 1. Board features
Processor
NXP Applications Processor
MIMX8MM6DVTLZAA
DRAM memory
Micron 2 GB LPDDR4
MT53D512M32D2DS-053 WT:D
Mass storage
SanDisk 16 GB eMMC5.1
SDINBDG4-16G-I
Micron 32 MB QSPI NOR
MT25QU256ABA1EW7-0SIT
MicroSD card connector
SD3.0 supported
Power
ROHM PMIC BD71847 + Discrete DCDC/LDO
Camera
CSI interface (Mini-SAS connector)
Display interface
DSI interface (Mini-SAS connector)
Ethernet
1 GB Ethernet with RJ45 connector
USB
X2 USB (2.0) Type-C connector, only Port2 could be used as the Power Input
Wi-Fi/Bluetooth
x1 on board Wi-Fi/Bluetooth module, 802.11b/g/n/ac, BT4.1
3.5 mm Stereo Line output, 2Vrms
FPC connector (SAI ports) for Audio Card
JTAG (10pin header)
MicroUSB for UART debug, two COM Ports for A53 and A4
M.2 connector
x1 M.2 slot (KEY-E type), support PCIE2.0, I2C interfaces
Expansion connector
40-pin dual-row Pin Header for I2S, UART, I2C and GPIO expansion
I2C connector
8-pin dual-row Pin Header for I2C expansion
Buttons
ON/OFF, RESET
LED indicators
Power status, UART
8MMINILPD4-CPU: 2inch x 2inch, 8-layer
8MMINI-BB: 4inch x 4.2inch, 8-layer
Audio connectors
Debug connectors
PCB
1.2.
Board contents
The i.MX 8M Mini LPDDR4 EVK contains the following items:
• i.MX 8M Mini LPDDR4 EVK board, assembled by two separate boards, 8MMINILPD4-CPU
(SOM Board) and 8MMINI-BB (Base Board)
• IMX-MIPI-HDMI Accessory Card, MIPI-DSI to HDMI adapter board
• USB Type-C 45W Power Delivery Supply, 5V/3A, 9V/3A, 15V/3A, 20V/2.25A supported
• Mini-SAS cable, 8" mini-SAS cable
• USB Type-C Cable, Cable – Assembly, USB 3.0, Type-C Male to Type-A Male
• USB micro-B Cable, Cable – Assembly, USB 2.0, Type-A Male to Micro-B Male
• USB Type-C to A Adapter, Adapter – USB 3.0, Type-C Male to Type-A Female
• Quick Start Guide
2. Specifications
This section provides the detailed information about the electrical design and practical considerations on
the LPDDR4 EVK board. Figure 1 describes each block in the high-level block diagram of the
LPDDR4 EVK board.
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Specifications
Figure 1. MCIMX8M Mini LPDDR4 EVK Block Diagram
Figure 2 shows the overview of the i.MX 8M Mini LPDDR4 EVK board.
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Specifications
8MMINILPD4-CPU
8MMINI-BB
Figure 2. i.MX 8M Mini LPDDR4 EVK board overview
CAUTION
Type-C Port2 is the only power supply port, and it must be always supplied for system
running.
i.MX 8M Mini EVK is not a typical use case of the PD device. It is supplied by the
PD charger only, but with a power switch. When the switch keeps OFF for more than
5.5 seconds after adapting the PD charger, the charger (Source) will repower EVK
(Sink) after the system initiates the PD software. See Section 6.5.7 in the Universal
Serial Bus Power Delivery Specification Revision 2.0. There are two ways to avoid
repower:
• The power switch must always be at the ON side before adapting the PD
charger.
• Change the software to disable the PD function, and make it Type-C supply
only.
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Specifications
BOOT_MODE0
BOOT_MODE1
Processor
The i.MX 8M Mini processors represent NXP Semiconductor’s latest achievement in the integrated
multimedia-focused products offering high performance processing with a high degree of functional
integration, targeted towards the growing market of connected devices. The i.MX 8M Mini processor
features NXP’s advanced implementation of the Quad Arm Cortex®-A53+ Arm Cortex®-M4 core,
which operates at speeds up to 1.8 GHz. Each processor provides a 32-bit DDR3L/DDR4/LPDDR4
memory interface and other interfaces for connecting peripherals, such as MIPI LCD, MIPI Camera,
WLAN, Bluetooth™, Ethernet, Digital Mic, GPS, and multi-sensors.
For more detailed information about the processor, see the datasheet and reference manual on
www.nxp.com/i.MX8MMINI.
2.1.
Boot Mode and Boot Device configurations
The i.MX 8M Mini Applications Processor can boot from the boot configuration selected on SW1101 or
from the boot configuration stored on the internal eFUSE. In addition, the i.MX 8M Mini can download
a program image from a USB connection when configured in serial downloader mode. The method used
to determine where the processor finds its boot information is from two dedicated BOOT MODE pins.
Table 2 shows the values used in the two methods.
NXP Semiconductors 5
Figure 3. Boot Mode Selection
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Specifications
Table 2. Boot Mode settings
0
0
Boot from fuses
1
0
Serial downloader
0
1
Internal boot (Default)
1
1
Reserved
Table 3. Boot Device settings
eMMC/uSDHC3
0110110001
0001010100
MicroSD/uSDHC2
0110110010
0001101000
NAND Flash
0110000000
1000111100
QSPI NOR Flash
0110xxxxxx
00000x0010
Serial Download Mode
1010xxxxxx
xxxxxxxxx0
BOOT_MODE0 BOOT_MODE1 Boot Mode
It is important for the developer to remember that these two pins are tied to the BOOT modules. If the
developer wants to boot the program Image from the Internal Boot mode, which means the processor
will execute the boot code from the internal boot ROM, the position of the switch 1 and 2 must be set to
OFF (0), ON (1), it is the same principle to choose the Serial Downloader mode or Boot from Fuse
mode to load boot code into the processor.
If Internal Boot mode is selected, the developer can set the switches SW1101 and SW1102 to choose the
boot device and related boot configurations as shown in Table 3 and Figure 4. Figure 5 shows the
detailed connection of SW1101 and SW1102.
BOOT Device SW1101 SW1102
NOTE
SW1101 bit 3 and bit 4 are used for compatible design with i.MX 8M
Nano, which must be set to 1 and 0 for i.MX 8M Mini.
SW1102 bit 10 is used for Infinit-Loop (Debug use only), which must be
set to 0.
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Specifications
Figure 4. Boot Device settings
NOTE
SW1101 bit[9:10] for eMMC/SDHC3 boot should be 01 instead of 10, see
chapter 4 errata for detailed information.
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Figure 5. Boot Configuration Schematic
On the i.MX 8M Mini LPDDR4 EVK board, the default boot mode is from the eMMC device. There are
another two boot devices, one QSPI Nor Flash on CPU board, and one MicroSD connector on the Base
Board. If you set the boot device to QSPI or MicroSD, the board will boot from the device accordingly.
NAND boot is not supported on the i.MX 8M Mini LPDDR4 EVK board,
but it is supported on the i.MX 8M Mini DDR4 EVK board.
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For more information about the boot module, such as the meaning of
every bit of the Boot Switch, see the i.MX 8M Mini Reference Manual on
www.nxp.com/i.MX8MMINI.
Specifications
2.2.
Power Tree
There is a Type-C power supply that needs to be connected to the i.MX 8M Mini LPDDR4 EVK board
at connector J302. The other powers on the EVK board are generated from PMIC and discrete devices to
supply the whole system. Figure 6 shows the Power Tree.
Figure 6. Power Tree Diagram
In Figure 6, the developer can get all the voltage supply rails used on the EVK board. When some
modules are not enabled, the power supplies might be shut down by software. Table 4 lists the power
rails on the board.
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Specifications
Table 4. Power rails
0
DCDC_5V
Discrete
5
2
VDD_SNVS_0V8
BD71847 LDO2
0.8 3 RTC_RESET_B
BD71847
- 4 CLK_32K_OUT
BD71847
-
6
VDD_PHY_0V9
BD71847 LDO4
0.9
7
BD71847 BUCK2
7
VDDA_1V8
BD71847 LDO3
1.8 8 VDD_1V8/NVCC_1V8
BD71847 BUCK7
1.8 9 NVCC_DRAM_1V1
BD71847 BUCK8
1.1
10
VDD_3V3/NVCC_3V3
BD71847 BUCK6
3.3
10
NVCC_SD2
BD71847 MUXSW
3.3/1.8
10
VDD_5V
Load Switch
5
10
VDDEXT_3V3
Discrete
3.3
11
VDD_PHY_1V2
BD71847 LDO6
1.2
12
POR_B
BD71847
-
13
VSD_3V3
Load Switch
3.3
SEQ Power Rail Regulator Value/V
1 NVCC_SNVS_1V8 BD71847 LDO1 1.8
5
6
VDD_SOC_0V8
VDD_DRAM&PU_0V9
VDD_ARM_0V9
BD71847 BUCK1
BD71847 BUCK5
0.851
0.9752
0.85/0.95/1.03
1. BD71847 BUCK1 default output voltage is 0.8V. Software will change it to 0.85V in SPL before DDR initialization.
2. BD71847 BUCK5 default output voltage is 0.9V. Software will change it to 0.975V(BD71847 BUCK5 doesn't support 0.95V
output) in SPL before DDR initialization.
3. BD71847 BUCK2 default output voltage is 0.9V. Software will change it to 0.85V for 1.2GHz operation, 0.95V for 1.6GHz,
1.0V for 1.8GHz.
2.3.
LPDDR4 DRAM memory
The i.MX 8M Mini LPDDR4 EVK board has one 512 Meg x 32 (2 channels x 16 I/O) LPDDR4
SDRAM chip (MT53D512M32D2DS-053 WT:D) for a total of 2 GB RAM memory.
In the physical layout, the LPDDR4 chip is placed on the TOP side, the data traces are not necessarily
connected to the LPDDR4 chips in sequential order, but for ease of routing, are connected as best
determined by the layout and other critical traces.
The DRAM_VREF can be generated by i.MX 8M Mini internally, so it does not need to use external
power supply and decoupling capacitors. The calibration resistors used by the LPDDR4 chips and
processor are 240 Ohm 1% resistors. The differential termination resistor for DRAM Clock is 150 ohm
1% on EVK. Developers can change this value depending on simulation and test result.
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2.4.
The eMMC memory is connected to the uSDHC3 interface of i.MX 8M Mini, and it can support up to
eMMC 5.1 device. The eMMC memory is on the 8MMINILPD4-CPU board, and the part number is
SDINBDG4-16G-I. It is the default boot device of the EVK. The boot settings are as shown in Table 3.
2.5.
The QSPI memory is connected to the FlexSPI interface of i.MX 8M Mini, and it can support up to
166 Mhz DDR mode device. The QSPI memory is on the 8MMINILPD4-CPU board, and the part
number is MT25QU256ABA1EW7-0SIT. To select it as the boot device of the EVK, developers can
refer to the boot settings as shown in Table 3.
2.6.
There is one MicroSD card slot (J701) on the 8MMINI-BB board, connecting to the uSDHC2 interface
of i.MX 8M Mini. This connector supports one 4-bit SD3.0 MicroSD card. To select it as the boot
device of the EVK, developers can refer to the boot settings as shown in Table 3.
2.7.
eMMC memory (U4)
QSPI Nor Flash (U5)
SD card slot (J701)
MIPI-CSI&MIPI-DSI connectors (J802, J801)
The i.MX 8M Mini processor supports one 4-lane MIPI-CSI and one 4-lane MIPI-DSI. The MiniSAS
connectors are designed to support camera and LCD with dedicated pin definition. The connectors are as
shown in Figure 2.
2.8.
The Ethernet subsystem of the EVK board is provided by the Qualcomm AR8031 Ethernet Transceiver
(U501). The Ethernet Transceiver (or PHY) receives standard RGMII Ethernet signals from the MACNET core of the i.MX 8M Mini. The processor handles all Ethernet protocols at the MAC layer and
above. The PHY is only responsible for the Link Layer formatting. The Ethernet connector (J501)
integrates Magnetic transformer inside, so it cannot be directly connected to AR8031 (U501).
Each EVK board has a unique MAC address, which is burned into i.MX 8M Mini by Fuse, and the label
is stuck on the connector very clearly.
2.9.
The i.MX 8M Mini Applications Processors contain two USB 2.0 OTG controllers, with two integrated
USB PHY. There are two USB Type-C connectors on the EVK board, both can support Host and Device
Mode.
J301 is connected to USB1 interface of i.MX 8M Mini, which can act as the download port of the EVK.
Ethernet connector (J501)
USB connector (J301, J302)
J302 is connected to USB2 interface of i.MX 8M Mini, which can act the power supply port of the EVK.
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2.10.
The EVK board has a Wi-Fi/Bluetooth module LBEE5KL1PJ on the 8MMINILPD4-CPU board. The
module is Qualcomm QCA9377-3 based, contains SDIO3.0, UART, PCM interface, and can support
802.11b/g/n/ac, BT4.1. The 2.4G/5G antenna is stuck to the edge of the Base Board with a coaxial cable
connected to the CPU Board.
2.11.
The EVK board uses a high-quality Stereo DAC WM8524 (U401), which can support 24 bit I2S data
and 192 KHz sampling rate. The Line output of WM8524 is 2Vrms, not like common headphone output
1 Vrms. Developers must be very careful about this interface. The Line output connector (J401) is a
3.5 mm 4-pole (or TRRS) phone jack.
The Audio Line output connector is designed for active speaker with a power amplifier. To connect it with a
headphone, make sure that the headphone has volume control functionality and set the headphone’s volume
properly before wearing it. Do not plug in the non-volume-control headphone directly. The audio output
volume may be too high for non-volume-control headphone and may damage it.
Wi-Fi/Bluetooth (U6)
Audio Line output (J401)
CAUTION
2.12.
One 60-pin FPC connector (J1001) is provided on the EVK board to support audio card connection, and
the developers can use the audio card to perform audio features development.
2.13.
The i.MX 8M Mini Applications Processor has five JATG signals on dedicated pins, and one HW reset
input signal POR_B
The five JTAG signals used by the processor are:
2.14.
The i.MX 8M Mini Applications Processor has four independent UART Ports (UART1 – UART4). On
the EVK board, UART2 is used for Cortex-A53 core, and UART4 is used for Cortex-M4 core. We use a
Single chip USB to dual channel UART IC for system debugging, and the part number is FT2232D. The
developers can download the driver from FTDI website http://www.ftdichip.com/Drivers/VCP.htm.
After the driver for FT2232D is installed, the PC will enumerate two COM ports when the USB cable is
Audio Card connector (J1001)
JTAG connector (J902)
. Those signals are directly connected to the 10-pin 1.27 mm JTAG connector J902.
• JTAG_TCK TAP Clock
• JTAG_TMS TAP Machine State
• JTAG_TDI TAP Data In
• JTAG_TDO TAP Data Out
• JTAG_nTRST TAP Reset Request (Active Low)
USB-UART connector (J901)
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Table 5. Terminal setting parameters
Data Rate
115,200 Baud
Data bits
8
Parity
None
Stop bits
1
Table 6. J1003 Pin Definition
1
VEXT_3V3
Power Output, 3.3V
2
VDD_5V
Power Output, 5V
3
I2C3_SCL_3V3
I2C3 clock signal
4
VDD_5V
Power Output, 5V
5
I2C3_SDA_3V3
I2C3 data signal
6
GND
Ground
7
UART3_CTS
UART3 clear to send signal
8
UART3_TXD
UART3 transmit signal
9
GND
Ground
10
UART3_RXD
UART3 transmit signal
11
UART3_RTS
UART3 request to send signal
12
EXP_IO8
Expansion IO signal
13
EXP_IO9
Expansion IO signal
14
GND
Ground
15
EXP_IO10
Expansion IO signal
16
EXP_IO11
Expansion IO signal
17
VEXT_3V3
Power Output, 3.3V
18
-
NC
19
ECSPI2_MOSI
SPI2 data signal, master
output slave input
20
GND
Ground
21
ECSPI2_MISO
SPI2 data signal, master input
slave output
22
-
NC
23
ECSPI2_SCLK
SPI2 clock signal
24
ECSPI2_SS0
SPI2 chip select signal
25
GND
Ground
26
-
NC
27
-
NC
28
-
NC
29
-
NC
30
GND
Ground
31
EXP_IO14
Expansion IO signal
32
EXP_IO12
Expansion IO signal
33
EXP_IO13
Expansion IO signal
34
GND
Ground
35
SAI5_RXD3
SAI5 receive data signal
36
SAI5_RXD2
SAI5 receive data signal
37
SAI5_RXD1
SAI5 receive data signal
38
SAI5_RXD0
SAI5 receive data signal
39
GND
Ground
40
SAI5_RXC
SAI5 receive clock signal
plugged into J901. Developers can use Putty, Tera Term, Xshell, or other terminal tools. The required
settings are as listed in Table 5.
2.15.
M.2 connector (J601)
One M.2/NGFF connector (J601) is provided on the EVK board to support PCIE2.0, I2C, and GPIO
connection. This port can be used for the Wi-Fi/Bluetooth card, or some 3G/4G cards.
2.16.
Expansion connector (J1003)
One 40-pin dual-row Pin Header connector (J1003) is provided on the EVK board to support I2S,
UART, I2C, and GPIO connection. The developers can use the port for some specific application
development.
Num Net Name Description Num Net Name Description
2.17.
I2C connector (J1004)
One 8-pin dual-row Pin Header connector (J1004) is provided on the EVK board to support I2C
connection. The developers can use the port for some specific application development.
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Table 7. J1004 Pin Definition
1/2
VDD_3V3
Power Output, 3.3V
3/4
I2C3_SCL_3V3
I2C clock signal
5/6
I2C3_SDA_3V3
I2C data signal
7/8
GND
Ground
Num Net Name Description
2.18.
User interface buttons
There are two user interface buttons on the EVK board.
2.18.1.
Power button (SW901)
The i.MX 8M Mini Applications Processor supports the use of a button input signal to request main SoC
power state changes (i.e. ON or OFF) from the PMU.
The ON/OFF button can be used for debounce, OFF-to-ON time, and max timeout. Debounce is used to
generate the power-off interrupt. In the ON state, if ON/OFF button is held longer than the debounce
time, the power-off interrupt is generated. In the OFF state, if the ON/OFF button is held longer than the
OFF-to-ON time, the state will transit from OFF to ON. Max timeout can also be the time for requesting
physical power down after the ON/OFF button has been held for the defined time.
2.18.2.
Reset button (SW902)
THE RESET button (SW902) is directly connected to the PMIC BD71847. Holding the RESET button
will force to reset the PMIC power outputs except NVCC_SNVS_1V8 and VDD_SNVS_0V8 on the
EVK board. The i.MX 8M Mini applications processor will be immediately turned off and reinitiate a
boot cycle from the OFF state.
2.19.
User interface LED indicators
There are four LED indicators on the board. These LEDs have the following functions:
• Main Power Supply (D708)
— Green – The board is powered on.
— OFF – The board is powered off.
• System Status (D1) on 8MMINILPD4-CPU
— Green Blinking – CPU is running well.
— OFF – CPU is not running.
• M4 UART (D902/D903)
— D902 Green light flashing – The UART data transmitted to PC.
— D903 Orange light flashing – The UART data received from PC.
• A53 UART (D906/D905)
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— D906 Green light flashing – The UART data transmitted to PC.
D708
D903
D1
— D905 Orange light flashing – The UART data received from PC.
Specifications
D905
D906
D902
Figure 7. LED indicator
3. PCB information
The i.MX 8M Mini LPDDR4 EVK is composed by 8MMINILPD4-CPU and 8MMINI-BB. Table 1
lists the dimensions of the two boards. Both the two boards are made with standard 8-layer technology.
The material is FR-4, and the PCB stack-up information is shown in Table 8 and Table 9.
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Table 8. 8MMINILPD4-CPU Board stack up information
1
Signal
0.333+Plating
Dielectric 2.611 mil
2
GND
1
Dielectric 3.94 mil
3
Signal
0.5
Dielectric 3.7 mil
4
GND
1
Dielectric 16.14 mil
5
Power 1
Dielectric 3.805 mil
6
Power
0.5
Dielectric 3.94 mil
7
GND
1
Dielectric 2.611 mil
8
Signal
0.333+Plating
Finished:
47.244(4.724/-4.724) mil
1.2(+0.12/-0.12) MM
Designed:
43.858 mil
1.114 MM
Material:
TU768
TU768
Table 9. 8MMINI-BB Board stack up information
1
Signal
0.5+Plating
Dielectric 2.717 mil
2
GND
1
Dielectric 4.33 mil
3
Signal
1
Dielectric 11.085 mil
4
Power 1
Dielectric 14.170 mil
5
Power 1
Dielectric 11.415 mil
6
Signal
1
Dielectric 4.33 mil
7
GND
1
Dielectric 2.717 mil
8
Signal
0.5+Plating
Finished:
62.992(6.299/-6.299) mil
1.6(+0.16/-0.16) MM
Designed:
59.173 mil
1.503 MM
Material:
TU768
TU768
Layer Description Coppoer (Oz.) Dielectric thickness (mil)
Layer Description Coppoer (Oz.) Dielectric thickness (mil)
3.1.
You can download the schematics, layout files, gerber files, and BOM from
www.nxp.com/imx8mminievk.
16 NXP Semiconductors
EVK design files
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Table 10. Revision history
0
02/2019
Initial release.
4. Errata
Silkscreen: There is a wrong silkscreen on the board. SW1101 bit[9:10] for eMMC/SDHC3 boot should
be 01 instead of 10.
Description: 01 means 8-bit bus width while 10 means 4-bit bus width. It only impacts the eMMC bus
width during ROM booting. U-Boot, kernel, and system functionality are not impacted.
Affected boards: X-8MMINILPD4-EVK (with Base Board 700-31407 REV X5), 8MMINILPD4-EVK
(with Base Board 700-31407 REV A).
Workaround: Users can follow the Quick Start Guide or Hardware User Guide to correct SW1101
switch settings for eMMC/SDHC3 boot.
Figure 8. Boot Configuration Silkscreen
5. Revision History
Revision number Date Substantive changes
NXP Semiconductors 17
i.MX 8M Mini LPDDR4 EVK Board Hardware User's Guide, User's Guide, Rev. 0, 02/2019
Page 18
Document Number: IMX8MMEVKHUG
02/2019
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