NXP Semiconductors i.MX 6Dual, i.MX 6Quad, i.MX 6DualPlus, i.MX 6QuadPlus Reference Manual
© 2012-2016 NXP B.V.
NXP Semiconductors
Chip Errata
Rev. 6.1, 06/2016
IMX6DQCE
Chip Errata for the i.MX 6Dual/6Quad and i.MX 6DualPlus/6QuadPlus
This document details the silicon errata known at the time of publication for the i.MX 6Dual/6Quad and
i.MX 6DualPlus/6QuadPlus multimedia applications processors.
Table 2 provides a revision history for this document.
Table 3 contains a summary of the silicon errata. Bolded rows are specific to either i.MX 6Dual/6Quad or
i.MX 6DualPlus/6QuadPlus (see the errata description column).
Table 4 lists the ARM errata excluded from detailed description in this document.
To identify the silicon revision, refer to the last letter of the part number. See Table 1 for examples.
Table 1. Part number/silicon revision examples
Example Part Numbers Silicon Revision
MCIMX6Q6AVT10AC i.MX 6Quad, Revision 1.2
MCIMX6D6AVT10AD i.MX 6Dual, Revision 1.3
MCIMX6QP6AVT1AA i.MX 6QuadPlus, Revision 1.0
MCIMX6DP6AVT1AA i.MX 6DualPlus, Revision 1.0
For additional information, see either the i.MX 6Dual/6Quad Applications Processor Reference Manual
(IMX6DQRM) or the i.MX 6DualPlus/6QuadPlus Applications Processor Reference Manual
(IMX6DQPRM).
NOTE
BSP functionality in some configurations and use cases, or your own/added
software functionality, may be affected by an erratum. We have made our
best attempt at providing software workaround requirements and BSP status
for each erratum in this document. Whether a software workaround has been
implemented in the BSP or not, the user should evaluate his specific use
cases and take any (additional) necessary actions to prevent the occurrence
or impact of each erratum. Go through your support channel if you have any
questions or concerns.
Chip Errata for the i.MX 6Dual/6Quad and i.MX 6DualPlus/6QuadPlus, Rev. 6.1, 06/2016
2 NXP Semiconductors
The following table provides a revision history for this document.
Table 2. Document Revision History
Rev.
Number
Rev. 6.1 06/2016 • Updated ERR004536 in Table 3 and ERR004536 changing from: Silicon revision 1.3 to; No fix
Rev. 6 02/2016 • Updated the following i.MX 6Dual/6Quad-specific errata:
Rev. 5 06/2015 • Update to ERR006282
Rev. 4 06/2014 • Added ERR007805
Date Substantive Changes
scheduled and removing i.MX 6Dual/6Quad Only.
– ERR004300, ERR004484, ERR004536, ERR005216, ERR005723, ERR005768, ERR005908,
ERR006282, ERR006687, ERR007966, ERR008506,
• Added the following i.MX 6Dual/6Quad-specific errata:
– ERR007926, ERR008587, ERR009219
• Added the following i.MX 6DualPlus/6QuadPlus-specific errata:
– ERR009619, ERR009623, ERR009624
• Added the following i.MX 6Dual/6Quad and i.MX 6DualPlus/6QuadPlus-specific errata:
– ERR007555, ERR007556, ERR007557, ERR007573, ERR007575, ERR007577 , ERR007881,
ERR008990, ERR009165, ERR009218, ERR009535, ERR009596, ERR009598, ERR009604,
ERR009605, ERR009606, ERR009678, ERR009704, ERR009742, ERR009743, ERR009858
• Updated the following i.MX 6Dual/6Quad and i.MX 6DualPlus/6QuadPlus-specific errata:
– ERR004366
• Added Table 4 describing ARM errata not documented in this deliverable.
• Updated the following ARM errata:
• ERR003717, ERR003718, ERR003719, ERR003720, ERR003721, ERR003723, ERR003724,
ERR003725, ERR003726, ERR003727, ERR003728, ERR003729, ERR00 3730, ERR003731,
ERR003732, ERR003735, ERR003736, ERR003737, ERR003738, ERR00 3740, ERR003741,
ERR004324, ERR004326, ERR004327, ERR005175, ERR005183, ERR00 5185, ERR005187,
ERR005199, ERR005200, ERR005382, ERR005383, ERR005385, ERR00 5386, ERR005387,
ERR007006, ERR007007, ERR007008
• Removed errata:
– ERR005779
• Added ERR008001
• Added ERR008000
• Added ERR007554
• Added ERR007926
• Added ERR007966
• Removed ERR003742. This item was ARM erratum 732672. Access to this information must come
directly from ARM.
• Removed ERR007005. This item was ARM erratum 791420. Access to this information must come
directly from ARM.
Rev. 3 11/2013 • Added the following: ERR007005, ERR007006, ERR007007, ERR007008, ER007117, ER007220,
ERR007265, ERR007266
• Updated the following: ERR003740, ERR003742, ERR003778, ERR004512
Chip Errata for the i.MX 6Dual/6Quad and i.MX 6DualPlus/6QuadPlus, Rev. 6.1, 06/2016
NXP Semiconductors 3
Table 2. Document Revision History (continued)
Rev.
Number
Rev. 2 5/2013 • Deleted ERR003775—Addressed in rev. 1 of the i.MX 6Dual/6Quad Applications Processor Reference
Rev. 1.1 2/2013 Restored pages omitted in Rev. 1.
Rev. 1 1/2013 • Added the following:
Rev. 0 10/2012 Initial public release.
Date Substantive Changes
Manual (IMX6DQRM).
• Added the following errata:
– ERR006282
– ERR006308
– ERR006358
– ERR006687
• Updated the following:
– ERR004353
– ERR004446
– ERR005829
– ERR006223
– ERR006259
– ERR006281
• Updated ERR004367
– Deleted ERR005384 (not relevant to this Freescale implementation of the ARM® core)
Chip Errata for the i.MX 6Dual/6Quad and i.MX 6DualPlus/6QuadPlus, Rev. 6.1, 06/2016
4 NXP Semiconductors
Table 3. Summary of Silicon Errata
Errata Name Solution Page
Analog
ERR005852 Analog: Transition from Deep Sleep Mode to LDO Bypass Mode may cause the slow
No fix scheduled
response of the VDDARM_CAP output
®
ARM
ERR003717 ARM: 740657—Global Timer can send two interrupts for the same event No fix scheduled
ERR003718 ARM: 743622—Faulty logic in the Store Buffer may lead to data corruption No fix scheduled
ERR003719 ARM/MP: 751469 — Overflow in PMU counters may not be detected No fix scheduled
ERR003720 ARM/MP: 751472—An interrupted ICIALLUIS operation may prevent the completion
No fix scheduled
of a following broadcast operation
ERR003721 ARM: 751473—Under very rare circumstances, Automatic Data prefetcher can lead
No fix scheduled
to deadlock or data corruption
ERR003723 ARM: 751476—May miss a watchpoint on the second part of an unaligned access
No fix scheduled
that crosses a page boundary
ERR003724 ARM: 754322—Possible faulty MMU translations following an ASID switch No fix scheduled
ERR003725 ARM: 725631—ISB is counted in Performance Monitor events 0x0C and 0x0D No fix scheduled
ERR003726 ARM: 729817—MainID register alias addresses are not mapped on Debug APB
No fix scheduled
interface
ERR003727 ARM: 729818—In debug state, next instruction is stalled when sdabort flag is set,
No fix scheduled
instead of being discarded
ERR003728 ARM: 740661—Event 0x74 / PMUEVENT[38:37] may be inaccurate No fix scheduled
15
16
18
20
22
24
25
26
28
29
30
31
ERR003729 ARM: 740663—Event 0x68 / PMUEVENT[9:8] may be inaccurate No fix scheduled
ERR003730 ARM: 743623—Bad interaction between a minimum of seven PLDs and one
No fix scheduled
Non-Cacheable LDM can lead to a deadlock
ERR003731 ARM: 743626—An imprecise external abort, received while the processor enters
No fix scheduled
WFI, may cause a processor deadlock
ERR003732 ARM: 751471—DBGPCSR format is incorrect No fix scheduled
ERR003733 ARM: 751480—Conditional failed LDREXcc can set the exclusive monitor No fix scheduled
ERR003734 ARM: 752519—An imprecise abort may be reported twice on non-cacheable reads No fix scheduled
ERR003735 ARM: 754323—Repeated Store in the same cache line may delay the visibility of the
No fix scheduled
Store
ERR003736 ARM: 756421—Sticky Pipeline Advance bit cannot be cleared from debug APB
No fix scheduled
accesses
ERR003737 ARM: 757119—Some “Unallocated memory hint” instructions generate an
No fix scheduled
UNDEFINED exception instead of being treated as NOP
ERR003738 ARM/MP: 751475—Parity error may not be reported on full cache line access
No fix scheduled
(eviction / coherent data transfer / cp15 clean operations)
Chip Errata for the i.MX 6Dual/6Quad and i.MX 6DualPlus/6QuadPlus, Rev. 6.1, 06/2016
32
34
36
37
39
40
41
43
44
45
NXP Semiconductors 5
Table 3. Summary of Silicon Errata (continued)
Errata Name Solution Page
ERR003739 ARM: 751470—Imprecise abort on the last data of a cache linefill may not be
No fix scheduled
detected
ERR003740 ARM/PL310: 752271—Double linefill feature can cause data corruption [i.MX
No fix scheduled
6Dual/6Quad only]
ERR003741 ARM/PL310: 729815—The “High Priority for SO and Dev reads” feature can cause
No fix scheduled
Quality of Service issues to cacheable read transactions
ERR003743 ARM/PL310: 754670—A continuous write flow can stall a read targeting the same
No fix scheduled
memory area
ERR004324 ARM/MP: 761319—Ordering of read accesses to the same memory location may not
No fix scheduled
be ensured
ERR004325 ARM/MP: 764369—Data or unified cache line ma intenance operation by MVA may
No fix scheduled
not succeed on an Inner Shareable memory region
ERR004326 ARM/MP: 761321—MRC and MCR are not coun ted in event 0x68 No fix scheduled
ERR004327 ARM/MP: 764319—Read accesses to DBGPRSR and DBGOSLSR may generate
No fix scheduled
an unexpected UNDEF
ERR005175 ARM/MP: 771221—PLD instructions may allocate data in the Data Cache regardless
No fix scheduled
of the Cache Enable bit value
ERR005183 ARM/MP: 771224—Visibility of Debug Enable access rights to enable/disable tracing
No fix scheduled
is not ensured by an ISB
ERR005185 ARM/MP: 771225—Speculative cacheable reads to aborting memory region clear
No fix scheduled
the internal exclusive monitor, may lead to livelock
46
47
48
49
50
51
53
54
55
56
57
ERR005187 ARM/MP: 771223—Parity errors on BTAC and GHB are reported on
PARITYFAIL[7:6], regardless of the Parity Enable bit value
ERR005198 ARM/PL310: 780370—DATAERR, TAGERR, and Tag parity errors are incorrectly
sampled by the eviction buffer, leading to data corruption
ERR005199 ARM/MP: 769419—No automatic Store Buf fer drain, visibility of written data requires
an explicit Cache Sync operation [i.MX 6Dual/6Quad Only]
ERR005200 ARM/MP: 765569—Prefetcher can cross 4 KB boundary if offset is programmed with
value 23
ERR005382 ARM/MP: 775419—PMU event 0x0A (exception return) might count twice the LDM
PC ^ instructions with base address register write-back
ERR005383 ARM/MP: 775420—A data cache maintenance operation that aborts, followed by an
ISB and without any DSB in-between, might lead to deadlock
ERR005385 ARM/MP: 782772—A speculative execution of a Load-Exclusive or Store-Exclusive
instruction after a write to Strongly Ordered memory might deadlock the processor
ERR005386 ARM/MP: 782773—Upd ating a translation entry to move a page mapping might
erroneously cause an unexpected translation fault
ERR005387 ARM/MP: 782774—A spurious event 0x63, “STREX passed,” can be reported on an
LDREX that is preceded by a write to Strongly Ordered memory region
No fix scheduled
No fix scheduled
No fix scheduled
No fix scheduled
No fix scheduled
No fix scheduled
No fix scheduled
No fix scheduled
No fix scheduled
59
60
63
64
65
66
67
69
71
Chip Errata for the i.MX 6Dual/6Quad and i.MX 6DualPlus/6QuadPlus, Rev. 6.1, 06/2016
6 NXP Semiconductors
Table 3. Summary of Silicon Errata (continued)
Errata Name Solution Page
ERR006259 ARM: Debug/trace functions (PMU, PTM and ETB) are disabled with absence of
No fix scheduled
JT AG_TCK clock after POR
ERR007006 ARM/MP:794072-- Short loop including a DMB instruction might cause a denial of
No fix scheduled
service
ERR007007 ARM/MP: 794073 -- Speculative instruction fetches with MMU disabled might not
No fix scheduled
comply with architectural requirements
ERR007008 ARM/MP: 794074 --A write request to Uncacheable Shareable memory region might
No fix scheduled
be executed twice
ERR009604 ARM (CA9): 845369 — Unde r very rare timing circumstances, transition into
No fix scheduled
streaming mode might create a data corruption
ERR009605 ARM (CA9): 761320—Full cache line writes to the same memory region from at least
No fix scheduled
two processors might deadlock the processor
ERR009742 ARM: 795769 - “Write Context ID" event is updated on read access No fix scheduled
ERR009743 ARM: 799770 - DBGPRSR Sticky Reset st atus bit is set to 1 by the CPU debug reset
No fix scheduled
instead of by the CPU non-debug reset
ERR009858 ARM/PL310: 796171 When data banking is implemented, data parity errors can be
No fix scheduled
incorrectly generated
CAAM
ERR004320 CAAM: Three encryption functions may show up as available, even though they are
No fix scheduled
not
72
73
75
76
78
80
82
83
84
85
ERR004347 CAAM: False read access error No fix scheduled
ERR004348 CAAM: Internal 16 Kb RAM (CAAM) does not support wrapped accesses No fix scheduled
ERR005766 CAAM: CAAM cannot handle interleaved READ data “beats” returned by two different
No fix scheduled
slaves in the system, in reply to two different AXI-ID accesses
CCM
ERR006223 CCM: Failure to resume from Wait/Stop mode with power gating No fix scheduled
ERR007265 CCM: When improper low-power sequence is used, the SoC enters low power mode
No fix scheduled
before the ARM core executes WFI
ERR009219 CCM: Asynchronous clock switching can ca use unpredictable behavior [i.MX
No fix scheduled
6Dual/6Quad Only]
eCSPI
ERR009165
ERR009535
ERR009606
eCSPI: TXFIFO empty flag glitch can cause the current FIFO transfer to be sent twice No fix scheduled 93
eCSPI: Burst completion by SS signal in slave mode is not functional No fix scheduled 94
eCSPI: In master mode, burst lengths of 32n+1 will transmit incorrect data No fix scheduled 95
EIM
ERR004446 EIM: AUS mode is nonfunctional for devices larger than 32 MB No fix scheduled
86
87
88
89
90
91
96
Chip Errata for the i.MX 6Dual/6Quad and i.MX 6DualPlus/6QuadPlus, Rev. 6.1, 06/2016
NXP Semiconductors 7
Table 3. Summary of Silicon Errata (continued)
Errata Name Solution Page
ERR009218 EIM: Signals fail to drive as outp uts during boundary scan test No fix scheduled
ENET
ERR004512 ENET: 1 Gb Ethernet MAC (ENET) system limitation No fix scheduled
ERR005783 ENET: ENET Status FIFO may overflow due to consecutive short frames No fix scheduled
ERR005895 ENET: ENET 1588 channel 2 event capture mode not functional No fix sch eduled
ERR006358 ENET: Write to Transmit Descriptor Active Register (ENET_TDAR) is ignored No fix scheduled
ERR006687 ENET: Only the ENET wake-up interrupt request can wake the system from Wait
No fix scheduled
mode [i.MX 6Dual/6Quad Only]
ESAI
ERR008000
ESAI: ESAI may encounter channel swap when overrun/underrun occurs No fix scheduled 103
EXSC
ERR004365 EXSC: Exclusive accesses to certain memories are not supported to full AXI
No fix scheduled
specification
ERR005828 EXSC: Protecting the EIM memory map region causes unpredictable behavior No fix scheduled
FlexCAN
ERR005829 FlexCAN: FlexCAN does not transmit a message that is enabled to be transmitted in
No fix scheduled
a specific moment during the arbitration process
97
98
99
100
101
102
104
105
106
GPMI
ERR008001
GPMI: GPMI does not support the Set Feature command in Toggle mode No fix scheduled 108
GPU
ERR004341 GPU2D: Accessing GPU2D when it is power-gated will cause a deadlock in the
No fix scheduled
system
ERR005908 GPU2D: Image quality degradation observed for stretch blits when the stretch factor
No fix scheduled
is exactly an integer [i.MX 6Dual/6Quad Only]
ERR004300 GPU3D: L1 cach e performance drop [i.MX 6Dual/6Quad Only] No fix scheduled
ERR004484 GPU3D: L1 cach e “Write Address Data” pairing error [i.MX 6Dual/6Quad Only] No fix scheduled
ERR005216 GPU3D: Black texels in Android App Singularity 3D [i.MX 6Dual/6Quad Only] No fix scheduled
HDMI
ERR003744 HDMI: 9000446457—Audio DMA does not generate an interrupt after software stops
No fix scheduled
DMA transaction
ERR003745 HDMI: 9000440660—Audio DMA fails to stop after ERROR detection No fix scheduled
ERR004308 HDMI: 8000504668—The arithmetic unit may get wrong video timing values although
No fix scheduled
the FC_* registers hold correct values
109
110
111
112
113
114
115
116
Chip Errata for the i.MX 6Dual/6Quad and i.MX 6DualPlus/6QuadPlus, Rev. 6.1, 06/2016
8 NXP Semiconductors
Table 3. Summary of Silicon Errata (continued)
Errata Name Solution Page
ERR004323 HDMI: The DMA burst read transaction address region is limited to 8 KB No fix scheduled
ERR004366 HDMI: 9000482480—ARM core read operation returns incorrect data for certain
No fix scheduled
HDCP registers
ERR005171 HDMI: HDMI Tx audio may have noise due to audio DMA FIFO overflow No fix scheduled
ERR005172 HDMI: Under certain circumstances, the HDCP may transmit incorrect Ainfo value,
No fix scheduled
causing a failure on the receiver side
ERR005173 HDMI: Clarification on HDMI programming procedure to avoid FIFO overflow No fix scheduled
ERR005174 HDMI: HDMI AHB Audio DMA stream misalign m ent on system initialization No fix scheduled
I2C
ERR007805
I2C: When the I2C clock speed is configured for 400 kHz, the SCL low period violates
the I2C specification
No fix scheduled 126
I/O
ERR004307 I/O: MIPI_HSI, USB_HSIC, and ENET I/O interfaces should not be configured to
No fix scheduled
Differential input mode
IPU
ERR009623 IPU: IDMAC burst errors when crossing a 4k boundary using NI/PI 420/422 formats
No fix scheduled
[i.MX 6DualPlus/6QuadPlus Only]
MIPI
117
124
118
119
120
122
126
127
ERR004310 MIPI: Glitch or unknown clock frequency on MIPI input clock may occur in case the
No fix scheduled
CCM source clock is modified
ERR005190 MIPI: CSI2 Data lanes are activated before th e HS clock from the CSI Tx side
No fix scheduled
(camera) starts
ERR005191 MIPI: Corruption of short command packets with Word Count (WC) greater than
No fix scheduled
16’hFFEE, during video mode transmission by the MIPI Generic Interface
ERR005192 MIPI: Reverse direction long packets with no payload incorrectly issue a CRC error
No fix scheduled
for MIPI DSI
ERR005193 MIPI: The bits for setting the MIPI DSI video mode cannot be changed on the fly No fix scheduled
ERR005194 MIPI: On MIPI DSI, there is a possible corruption of the video packets caused by
No fix scheduled
overlapping of the current line over the next line, if the configuration is programmed
incorrectly when using the DPI interface
ERR005195 MIPI: Incorrect blanking packet may be sent by the MIPI DSI interface No fix scheduled
ERR005196 MIPI: Error Interrupt generated by the MIPI CSI interface for certain legal packet
No fix scheduled
types
ERR005197 MIPI: Null and Blanking data packets activate ‘dvalid’ signal No fix scheduled
ERR009704 MIPI: CSI-2: CRC error produced in 4-lane configuration No fix scheduled
128
129
130
131
132
133
134
135
136
137
Chip Errata for the i.MX 6Dual/6Quad and i.MX 6DualPlus/6QuadPlus, Rev. 6.1, 06/2016
NXP Semiconductors 9
Table 3. Summary of Silicon Errata (continued)
Errata Name Solution Page
MLB
ERR004312 MLB: Multi fram e per sub-buffer mode is not supported No fix scheduled
MMDC
ERR005778 MMDC: DDR Controller’s measure unit may return an incorrect value when operating
No fix scheduled
below 100 MHz
ERR009596 MMDC: ARCR_GUARD bits of MMDC Core AXI Re-ordering Control register
No fix scheduled
(MMDC_MAARCR) doesn't behave as expected
PCIe
ERR003747 PCIe: 9000436491—Reading the Segmented Buffer Depth Port Logic registers
No fix scheduled
returns all zeros
ERR003748 PCIe: 9000427578—Root ports with address translation drop inbound requests,
No fix scheduled
without reporting an error
ERR003749 PCIe: 9000426180—MSI Interrupt Controller Status Register bit not cleared after
No fix scheduled
being written by software
ERR003751 PCIe: 9000413207—PME Requester ID overwritten when two PMEs are received
No fix scheduled
consecutively
ERR003753 PCIe: 9000405932—AXI/AHB Bridge Slave does not return a response to an
No fix scheduled
outbound non-posted request
ERR003754 PCIe: 9000403702—AHB/AXI Bridge Master responds with UR status instead of CA
No fix scheduled
status for inbound MRd requesting greater than CX_REMOTE_RD_REQ_SIZE
138
139
140
141
142
143
144
145
146
ERR003755 PCIe: 9000402443—Uncorrectable Internal Error Severity register bit has incorrect
No fix scheduled
default value
ERR003756 PCIe: 9000387484—LTSSM: Software-initiated transitions to Disabled, Hot Reset,
No fix scheduled
Configuration, or Loopback states sometimes take longer than expected
ERR003757 PCIe: 9000448152—Internal Address Translation Unit (iATU): Inbound Vendor
No fix scheduled
Defined Message (VDM) ‘ID Match Mode’ is not functional
ERR003758 PCIe: 9000441819—Upstream Port does not transition to Recovery after receiving
No fix scheduled
TS OSs during “ENTER_L2 negotiation”
ERR003759 PCIe: 9000439510—Internal Address Translation Unit (iATU) can sometimes
No fix scheduled
overwrite Outbound (Tx) Vendor Messages and MSIs
ERR003760 PCIe: 9000439175—Poisoned Atomic Op requests targeting RTRGT0 receive UR
No fix scheduled
response instead of CA response
ERR004297 PCIe: 9000336356—Link configuration sometimes proceeds when incorrect TS
No fix scheduled
Ordered Sets are received
ERR004298 PCIe: 9000471173—Bad DLLP error status checking is too strict No fix scheduled
ERR004299 PCIe: 9000493959—L1 ASPM incorrectly entered after link down event during L1
No fix scheduled
ASPM entry negotiation
ERR004321 PCIe: 9000470913—Power Management Control: Core might enter L0s/L1 before
No fix scheduled
Retry buffer is empty
147
148
149
150
151
152
153
154
155
156
Chip Errata for the i.MX 6Dual/6Quad and i.MX 6DualPlus/6QuadPlus, Rev. 6.1, 06/2016
10 NXP Semiconductors
Table 3. Summary of Silicon Errata (continued)
Errata Name Solution Page
ERR004374 PCIe: 9000487440—TLP sometimes unnecessarily replayed No fix scheduled
ERR004489 PCIe: 9000505660—PCIe2 receiver equalizer settings No fix scheduled
ERR004490 PCIe: 9000514662—LTSSM delay when moving from L0 to recovery upon receipt of
No fix scheduled
insufficient TS1 Ordered Sets
ERR004491 PCIe: 9000507633—TLP might be replayed an extra time before core enters
No fix scheduled
recovery
ERR005184 PCIe: Clock pointers can lose sync during clock rate changes No fix scheduled
ERR005186 PCIe: The PCIe Controll er Core Does Not Send Enough TS2 Ordered Sets During
No fix scheduled
Link Retrain And Speed Change
ERR005188 PCIe: The PCIe Controller cannot exit successfully L1 state of L TSSM when the Core
No fix scheduled
Clock is removed
ERR005189 PCIe: PCIe Gen2/Gen3 Hardware Autonomous Speed Disable Bit In Configuration
No fix scheduled
Register is not sticky
ERR005723 PCIe: PCIe does not support L2 power down [i.MX 6Dual/6Quad Only] No fix scheduled
ERR007554 PCIe: MSI Mask Register Reserved Bits not read-only No fix scheduled.
ERR007555 PCIe: iATU - Optional programmable CFG Shift feature for ECAM is not correctly
No fix scheduled
updating address (9000642041)
ERR007556 PCIe: Core Delays Transition From L0 To Recovery After Receiving Two TS OS And
No fix scheduled
Erroneous Data (9000597455)
158
159
160
162
163
165
166
167
168
169
170
171
ERR007557 PCIe: Extra FTS sent when Extended Sync h bit is set (9000588281) No fix scheduled
ERR007559 PCIe: Core sends TS1 with non-PAD lane number too early in
No fix scheduled
Configuration.Linkwidth.Accept State (9000574708)
ERR007573 PCIe: Link and lane number-match not checked in recovery (9000569433) No fix scheduled
ERR007575 PCIe: LTSSM delay when moving from L0 to recovery upon receipt of insufficient TS1
No fix scheduled
Ordered Sets (9000514662)
ERR007577 PCIe: DLLP/T LP can be missed on RX path when immediately followed by EIOS
No fix scheduled
(9000487440)
ERR008587 PCIe: Random link down after warm reset [i.MX 6Dual/6Quad Only] No fix scheduled
PRE
ERR009619 PRE: GPU3D, GPU2D and VPU cannot be power-gated if the PRE is in use [i.MX
No fix scheduled
6DualPlus/6QuadPlus Only]
ERR009624 PRE: ENABLE bit cannot be set in a special case, when the EN_REPEAT bit is set
No fix scheduled
[i.MX 6DualPlus/6QuadPlus Only]
ROM
ERR007117 ROM: When booting from NAND flash, enfc_clk_root clock is not gated off when
doing the clock source switch [i.MX 6Dual/6Quad Only]
ERR007220 ROM: NAND boot may fail due to incorrect Hamming Checking implementation in the
ROM code [i.MX 6Dual/6Quad Only]
Fixed in silicon
revision 1.3.
Fixed in silicon
revision 1.3
172
173
174
175
176
177
178
179
180
181
Chip Errata for the i.MX 6Dual/6Quad and i.MX 6DualPlus/6QuadPlus, Rev. 6.1, 06/2016
NXP Semiconductors 11
Table 3. Summary of Silicon Errata (continued)
Errata Name Solution Page
ERR007926 ROM: 32 kHz internal oscillator timing inaccuracy may affect SD/MMC, NAND, and
No fix scheduled
OneNAND boot [i.MX 6Dual/6Quad Only]
ERR005645 ROM: Normal SD clock speed (SDR12) not selectable in SD/SDXC boot mode No fix scheduled
ERR005768 ROM: In rare cases, secondary image boot flow may not work due to mis-sampling
No fix scheduled
of the WDOG reset [i.MX 6Dual/6Quad Only]
ERR006282 ROM: ROM code uses nonreset PFDs to generate clocks, which may lead to random
boot failures [i.MX 6Dual/6Quad Only]
Fixed in silicon
revision 1.3
ERR007266 ROM: EIM NOR boot may fail if plug-in is used No fix scheduled
ERR008506 ROM: Incorrect NAND BAD Block Management [i.MX 6Dual/6Quad Only] No fix scheduled
ERR009678 ROM: SD/EMMC/NAND prematurely times out during boot [i.MX 6Dual/6Quad Only] No fix scheduled
SATA
ERR003761 SAT A: 9000433864—COMRESET and COMWAKE do not always contain six bursts No fix scheduled
ERR003762 SATA: 9000450053—In SDB FIS with N-bit set, non-matching PMP field is not
No fix scheduled
discarded
ERR003763 SATA: 9000448817—Soft Reset command does not SYNC-escape incoming data
No fix scheduled
FIS
ERR003764 SATA: 9000447882—ERR_I bit set when PhyRdy goes low during non-data FIS
No fix scheduled
reception
ERR003765 SATA: 9000447627—Global reset does not clear IS.IPS register bits when P#IS is
No fix scheduled
non-zero
182
184
185
186
190
191
192
193
194
195
196
197
ERR003766 SATA: 9000446485—phy_partial, phy_slumber incorrectly asserted for a power
No fix scheduled
mode
ERR003767 SATA: 9000446482—hCccComplete cleared, incorrectly incremented No fix scheduled
ERR003769 SATA: 9000445811—Erroneous PRD interrupt assertion No fix scheduled
ERR003770 SATA: 9000451535—Hang due to FIFO count change, when FIFO is cleared No fix scheduled
ERR003771 SATA: 9000451305—Hang after incoming FIS and soft reset No fix scheduled
ERR003772 SAT A: 9000451274—Power mode request collision causes assertion of phy_partial,
No fix scheduled
phy_slumber
ERR003773 SATA: 9000451526—Hang after Soft Reset and PM Request from the Device No fix scheduled
ERR007966 SAT A:SAT A speed negotiation fails after suspend and resume —[i.MX 6Dual/6Quad
No fix scheduled
Only]
ERR009598 SATA: PRD not flushed from PRD FIFO at command list underflow No fix scheduled
SNVS
ERR004367 SNVS: SNVS_LP resets to the power OFF state No fix scheduled
SSI
ERR003778 SSI: In AC97, 16-bit mode, received da ta is shifted by 4-bit locations No fix scheduled
198
199
200
201
202
203
204
205
207
208
209
Chip Errata for the i.MX 6Dual/6Quad and i.MX 6DualPlus/6QuadPlus, Rev. 6.1, 06/2016
12 NXP Semiconductors
Table 3. Summary of Silicon Errata (continued)
Errata Name Solution Page
ERR005764 SSI: AC97 receive data may be wrong when clock ratio between external clock to ipg
No fix scheduled
is higher than 1:8
ERR008990 SSI: Channel swap in single FIFO mode when an underrun or overrun occurs No fix scheduled
USB
ERR004534 USB: Wrong HS disconnection may be generated after resume No fix scheduled
ERR006281 USB: Incorrect DP/DN state when only VBUS is applied No fix scheduled
ERR006308 USB: Host non-doubleword –aligned buffer address can cause host to hang on OUT
No fix scheduled
Retry
ERR004535 USB: USB suspend and resume flow clarifications No fix scheduled
ERR007881 USB: Timeout error in Device mode No fix scheduled
uSDHC
ERR004364 uSDHC: Limitations on uSDHC3 and uSDHC4 clock-gating No fix scheduled
ERR004536 uSDHC: ADMA Length Mismatch Error may occur for longer read latencies No fix scheduled
VPU
ERR004345 VPU: Wrong interrupt is generated sometimes whe n context switchi ng to H.2 64
No fix scheduled
encoder, during multi-instance
ERR004349 VPU: Cannot decode Sorenson Spark Version 0 bitstream No fix scheduled
210
211
212
213
214
215
216
217
218
219
220
ERR004361 VPU: VPU does not work in case of smaller chunk size in SSP (streaming pump
No fix scheduled
processing)
ERR004363 VPU: Causes a macro-block of P-picture decoding error No fix scheduled
WDOG
ERR004346 WDOG: WDOG SRS bit requires to be written twice No fix scheduled
XTAL
ERR005777 XTAL: In some cases, the 24 MHz oscillator start-up is slow or may fail to start No fix scheduled
221
222
223
224
Chip Errata for the i.MX 6Dual/6Quad and i.MX 6DualPlus/6QuadPlus, Rev. 6.1, 06/2016
NXP Semiconductors 13
Table 4. Excluded ARM Errata
ARM Errata Reference Title
743625 A coherent ACP request might interfere with a
non-cacheable SWP/SWPB from the processor,
Potentially causing deadlock
754319 A sequence of cancelled Advanced-SIMD or
VFP stores might deadlock
754320 A cancelled Advanced-SIMD or VFP load
multiple of more than 8 beats might deadlock
745320 A Floating Point write following a failed
conditional read might write corrupted da ta
751469 Overflow in PMU counters may not be detected i.MX6 does not support PMU (Performance
751475 Parity error may not be reported on full cache
line access (eviction / coherent data transfer /
cp15 clean operations)
761321 MRC and MCR are not counted in event 0x68 i.MX6 does not support PMU (Performance
Reason why excluded from this errata
document
i.MX6 does not support the ACP (Accelerator
Coherency Port) hence errata not applicable.
Errata was fixed in the Floating Point Unit (FPU)
Revision 0x4 which is used across i.MX6, hence
not applicable.
Errata was fixed in the Floating Point Unit (FPU)
Revision 0x4 which is used across i.MX6, hence
not applicable.
Errata was fixed in the Floating Point Unit (FPU)
Revision 0x4 which is used across i.MX6, hence
not applicable.
Monitoring Unit) hence this ARM errata is not
applicable.
i.MX6 does not implement parity hence errata not
applicable. The parity feature is disabled by default
and should not be enabled.
Monitoring Unit) hence this ARM errata is not
applicable.
764269 Under very rare circumstances, a sequence of
at least three writes merging in the same 64-bit
address range might cause data corruption
791420 Possible denial of service for coherent requests
on a cache line which is continuously written by
a processor
756420 Instruction Cache parity error reporting on
PARITYF AIL[5:4] output is one cycle earlier than
the other PARITY FAIL bits
732672 An abort on the second part of a double linefill
can cause data corruption on the first part
ARM has not managed to reproduce the failure in
actual Silicon and no software workaround
available for this erratum.
Freescale cannot disclose this errata per ARM
requirements, however software workaround has
been implemented in the Freescale Linux BSP for
this erratum. OS vendors/users must approach
ARM if further information is required.
i.MX6 does not implement parity hence errata not
applicable. The parity feature is disabled by default
and should not be enabled.
Freescale cannot disclose this errata per ARM
requirements, however software workaround has
been implemented in the Freescale Linux BSP for
impacted devices. OS vendors/users must
approach ARM if further information is required.
Chip Errata for the i.MX 6Dual/6Quad and i.MX 6DualPlus/6QuadPlus, Rev. 6.1, 06/2016
14 NXP Semiconductors
ERR005852
ERR005852 Analog: Transition from Deep Sleep Mode to LDO Byp a ss Mode may
cause the slow response of the VDDARM_CAP output
Description:
Normally, the VDDARM_CAP supply takes only approximately 40 μs to raise to the correct
voltage when exiting from Deep Sleep (DSM) mode, if the LDO is enabled. If the LDO bypass
mode is selected, the VDDARM_CAP supply voltage will drop to approximately 0 V when
entering and when exiting from DSM, even though the VDDARM_IN supply is already stable, the
VDDARM_CAP supply will take about 2 ms to rise to the correct voltage.
Projected Impact:
ARM core might fail to resume.
Workarounds:
The software workaround to prevent this issue it to switch to analog bypass mode (0x1E), prior to
entering DSM, and then, revert to the normal bypass mode, when exiting from DSM.
Proposed Solution:
No fix scheduled
Linux BSP Status:
Software workaround integrated in Linux BSP codebase starting in release imx_3.0.35_4.1.0.
Chip Errata for the i.MX 6Dual/6Quad and i.MX 6DualPlus/6QuadPlus, Rev. 6.1, 06/2016
NXP Semiconductors 15
ERR003717
ERR003717 ARM: 740657—Global Timer can send two interrupts for the same
event
Description:
The Global Timer can be programmed to generate an interrupt request to the processor when it
reaches a given programmed value. Due to the erratum, when the Global Timer is programmed not
to use the auto-increment feature, it might generate two interrupt requests instead of one.
Conditions:
The Global Timer Control register is programmed with the following settings:
• Bit[3] = 1’b0 – Global Timer is programmed in “single-shot” mode
• Bit[2] = 1’b1 – Global Timer IRQ generation is enabled
• Bit[1] = 1’b1 – Global Timer value comparison with Comparator registers is enabled
• Bit[0] = 1’b1 – Global Timer count is enabled
With these settings, an IRQ is generated to the processor when the Global T imer value reaches the
value programmed in the Comparator registers.
The Interrupt Handler then performs the following sequence:
1. Read the ICCIAR (Interrupt Acknowledge) register
2. Clear the Global Timer flag
3. Modify the comparator value to set it to a higher value
4. Write the ICCEOIR (End of Interrupt) register
Under these conditions, due to the erratum, the Global Timer might generate a second (spurious)
interrupt request to the processor at the end of this Interrupt Handler sequence.
Projected Impact:
The erratum creates spurious interrupt requests in the system.
Workarounds:
Because the erratum only happens when the Global Timer is programmed in “single-shot” mode,
that is, when it does not use the auto-increment feature, a first possible workaround could be to
program the Global Timer to use the auto-increment feature.
If this solution does not work, a second workaround could be to modify the Interrupt Handler to
avoid the offending sequence. This is achieved by clearing the Global Timer flag after having
incremented the Comparator register value.
Then, the correct code sequence for the Interrupt Handler should look as below:
1. Read the ICCIAR (Interrupt Acknowledge) register
2. Modify the comparator value to set it to a higher value
3. Clear the Global Timer flag
4. Clear the Pending Status information for Interrupt 27 (Global Timer interrupt) in the
Distributor of the Interrupt Controller.
Chip Errata for the i.MX 6Dual/6Quad and i.MX 6DualPlus/6QuadPlus, Rev. 6.1, 06/2016
16 NXP Semiconductors
5. Write the ICCEOIR (End of Interrupt) register
Proposed Solution:
No fix scheduled
Linux BSP Status:
Software workaround not needed in the BSP. Functionality or mode of operation in which the
erratum may manifest itself is not used. The BSP does not use ARM global timer. The
configuration and logic of the kernel does not make use of the Global Timer. If the Global timer is
used, the workaround documented by ARM should be followed. Due to limitations of this timer
specifically in low power mode operation we do not recommend the use of this ARM Global timer.
ERR003717
Chip Errata for the i.MX 6Dual/6Quad and i.MX 6DualPlus/6QuadPlus, Rev. 6.1, 06/2016
NXP Semiconductors 17
ERR003718
ERR003718 ARM: 743622—Faulty logic in the Store Buffer may lead to data
corruption
Description:
Under very rare conditions, a faulty optimization in the Cortex®-A9 store buffer might lead to data
corruption.
Conditions:
The code sequence which exhibits the failure requires at least five cacheable writes in 64-bit data
chunk:
• Three of the writes must be in the same cache line
• Another write must be in a different cache line
• All of the above four writes hit in the L1 data cache
• A fifth write is required in any of the above two cache lines that fully writes a 64-bit data chunk
With the above code sequence, under very rare circumstances, this fifth write might get corrupted,
with the written data either being lost, or being written in another cache line.
The conditions under which the erratum can occur are extremely rare, and require the coincidence
of multiple events and states in the Cortex-A9 micro-architecture.
As an example: let’s assume A, A’, A”, and A’’’ are all in the same cache line—B and B’ are in
another cache line. The following code sequence might trigger the erratum:
STR A
STR A’
STR A’’
STR B
STR A’’’ (or STR B’)
At the time where the first four STR are in the Cortex-A9 store buffer , and the fifth STR arrives at
a very precise cycle in the Store Buffer input stage, then the fifth STR might not see its cache line
dependency on the previous STR instructions. Because of this, in cases when the cache line A or
B gets invalidated due to a coherent request from another CPU, the fifth STR might write in a faulty
cache line, causing data corruption.
An alternative version of the erratum might happen even without a coherent request — In the case
when the fifth STR is a 64-bit write in the same location as one of A, A’, A ’ ’, then the erratum might
also be exhibited. Note that this is a quite uncommon scenario because it requires a first write to a
memory location that is immediately and fully overwritten.
Projected Impact:
When it occurs, this erratum creates a data corruption.
Workarounds:
A software workaround is available for this erratum that requires setting bit[6] in the
undocumented Diagnostic Control register, placed in CP15 c15 0 c0 1.
The bit can be written in Secure state only, with the following Read/Modify/W rite code sequence:
Chip Errata for the i.MX 6Dual/6Quad and i.MX 6DualPlus/6QuadPlus, Rev. 6.1, 06/2016
18 NXP Semiconductors
MRC p15,0,rt,c15,c0,1
ORR rt,rt,#0x40
MCR p15,0,rt,c15,c0,1
When this bit is set, the “fast lookup” optimization in the Store Buffer is disabled, which will
prevent the failure to happen.
Setting this bit has no visible impact on the overall performance or power consumption of the
processor.
Proposed Solution:
No fix scheduled
Linux BSP Status:
Software workaround implemented in Linux BSP codebase (UBOOT) starting in release
imx_3.0.35_4.1.0.
ERR003718
Chip Errata for the i.MX 6Dual/6Quad and i.MX 6DualPlus/6QuadPlus, Rev. 6.1, 06/2016
NXP Semiconductors 19
ERR003719
ERR003719 ARM/MP: 751469 — Overflow in PMU counters may not be detected
Description:
Overflow detection logic in the Performance Monitor Counters is faulty, and under certain timing
conditions, the overflow may remain undetected. In this case, the Overflow Flag Status register
(PMOVSR) is not updated as it should, and no interrupt is reported on the corresponding PMUIRQ
line.
It is important to notice that the Cycle counter is not affected by this erratum.
Projected Impact:
PMU overflow detection is not reliable.
Workarounds:
The main workaround for this erratum is to poll the performance counter . The maximum increment
in a single cycle for a given event is 2. Therefore, polling can be infrequent as no counter can
increment by more than 2^32 in fewer than 2 billion cycles.
If the main usage model for performance counters is collecting values over a long period, then
polling can be used to collect values (and reset the counter) rather than waiting for an overflow to
occur. Polling can be done infrequently and overflow avoided.
If the main usage model for performance counters relies on presetting the counter to some value
and waiting for an overflow to occur, then polling can be used to detect when an overflow event
has been missed. An overflow can be determined to have been missed if the unsigned value in the
counter is less than the value preset into the counter. Again, polling can be done infrequently
because of the number of cycles it would need for this check to fail. In the case that the erratum
was triggered and an overflow event was missed, that counter sample can be thrown away or the
true value can be reconstructed.
An alternative workaround is to configure two counters to be triggered by the same event,
staggering their initial count values by 1. This will result in the rollover being triggered by at least
counter.
This alternative workaround works for all Cortex-A9 events but the three following ones, due to
the fact these three events can increment by 2 in a single cycle:
- 0x68 – Instructions coming out of the core renaming stage
- 0x73 – Floating-point instructions
- 0x74 – NEON instructions
For these 3 events, only the first workaround is applicable to fix the defect.
Proposed Solution:
No fix scheduled
Linux BSP Status:
Software workaround is not needed because this erratum will not be encountered in normal device
operation. The Freescale Linux BSP does not support this optional profiling feature. Users may add
Chip Errata for the i.MX 6Dual/6Quad and i.MX 6DualPlus/6QuadPlus, Rev. 6.1, 06/2016
20 NXP Semiconductors
ERR003719
support for this profiling feature as required, but should ensure the multiple errata impacting the
ARM PMU are considered especially for multi-core usage.
Chip Errata for the i.MX 6Dual/6Quad and i.MX 6DualPlus/6QuadPlus, Rev. 6.1, 06/2016
NXP Semiconductors 21
ERR003720
ERR003720 ARM/MP: 751472—An interrupted ICIALLUIS operation may prevent
the completion of a following broadcast operation
Description:
In an MPCore configuration with two or more processors working in SMP mode with maintenance
operation broadcast enabled, if a processor is interrupted while executing an ICIALLUIS
operation, and performs another broadcast maintenance operation during its Interrupt Service
Routine, then this second operation might not be executed on other processors in the cluster.
Conditions:
The erratum requires an MPCore configuration with two or more CPUs working in SMP mode.
One processor has interrupts enabled, and Cache and TLB maintenance broadcast enabled too
(ACTLR.FW=1’b1). This processor executes an ICIALLUIS (invalidates all instruction caches
Inner Shareable to Point of Unification). This instruction is executed on the processor, and also
broadcast to other processors in the MPCore cluster . The processor then receives an interrupt (IRQ
or FIQ), which interrupts the ICIALLUIS operation.
During the Interrupt Service Routine, the processor executes any other Cache or TLB maintenance
operation which is also broadcast to other processors in the MPCore cluster . If the other processors
in the cluster receive this second maintenance operation before having completed the first
ICIALLUIS operation, then the erratum occurs, as the other processors will not execute the second
maintenance operation. This is because there is no “stacking” mechanism for acknowledge
answers between the processors, so that the acknowledge request sent to signify the completion of
the ICIALLUIS will be interpreted by the originating processor as an acknowledge for the second
maintenance operation.
Projected Impact:
Due to the erratum, the processor might end up with corrupted entries in the Cache or in the TLB,
leading to possible failures in the system.
Workarounds:
A software workaround is available for this erratum that involves setting bit[11] in the
undocumented Diagnostic Control register, placed in CP15 c15 0 c0 1.
This bit can be written in Secure state only, with the following Read/Modify/W rite code sequence:
MRC p15,0,rt,c15,c0,1
ORR rt,rt,#0x800
MCR p15,0,rt,c15,c0,1
When it is set, this bit prevents CP15 maintenance operations to be interrupted.
Using this software workaround is not expected to cause any visible impact on the system.
Proposed Solution:
No fix scheduled
Chip Errata for the i.MX 6Dual/6Quad and i.MX 6DualPlus/6QuadPlus, Rev. 6.1, 06/2016
22 NXP Semiconductors
Linux BSP Status:
Software workaround implemented in Linux BSP codebase (UBOOT) starting in release
imx_3.0.35_4.1.0.
ERR003720
Chip Errata for the i.MX 6Dual/6Quad and i.MX 6DualPlus/6QuadPlus, Rev. 6.1, 06/2016
NXP Semiconductors 23
ERR003721
ERR003721 ARM: 751473—Under very rare circumstances, Automatic Data
prefetcher can lead to deadlock or data corruption
Description:
Under very rare timing circumstances, the automatic Data prefetcher might cause address hazard
issues, possibly leading to a data corruption or a deadlock of the processor.
Conditions:
The erratum can only happen when the Data Cache and MMU are enabled in the following cases:
• On all memory regions marked as Write-Back Non-Shared, when the Data Prefetcher in L1 is
enabled (ACTLR[2]=1’b1), regardless of the ACTLR.SMP bit.
• On all memory regions marked as Write-Back Shared, when the Data Prefetch Hint in L2 is
enabled (ACTLR[1]=1’b1), and when the processor is in SMP mode (ACTLR.SMP=1’b1).
Projected Impact:
When the bug happens, a data corruption or a processor deadlock can happen.
Workarounds:
The workaround for this erratum requires not enabling the automatic Data Prefetcher by keeping
ACTRL[2:1]=2’b00, which is the default value on exit from reset.
Although this feature might show significant performance gain on a few synthetic benchmarks, it
usually has no impact on real systems. It means, this workaround is not expected to cause any
visible impact on final products.
Proposed Solution:
No fix scheduled
Linux BSP Status:
Software workaround not needed in the BSP. Functionality or mode of operation in which the
erratum may manifest itself is not used. Linux BSP keeps ACTRL[2:1]=2’b00.
Chip Errata for the i.MX 6Dual/6Quad and i.MX 6DualPlus/6QuadPlus, Rev. 6.1, 06/2016
24 NXP Semiconductors
ERR003723
ERR003723 ARM: 751476—May miss a watchpoint on the second part of an
unaligned access that crosses a page boundary
Description:
Under rare conditions, a watchpoint on the second part of an unaligned access that crosses a 4 KB
page boundary and that is missed in the micro-TLB for the second part of its request might be
undetected.
The erratum requires a previous conditional instruction that accesses the second 4 KB memory
region (= where the watchpoint is set), is missed in the micro-TLB, and is condition failed. The
erratum also requires that no other micro-TLB miss occurs between this conditional failed
instruction and the unaligned access. This implies that the unaligned access must hit in the
micro-TLB for the first part of its request.
Projected Impact:
A valid watchpoint trigger is missed.
Workarounds:
In case, a watchpoint is set on any of the first 3 bytes of a 4 KB memory region, and unaligned
accesses are not being faulted, then the erratum might happen.
The workaround then requires setting a guard watchpoint on the last byte of the previous page, and
dealing with any “false positive” matches as and when they occur.
Proposed Solution:
No fix scheduled
Linux BSP Status:
The Linux BSP does not use this debug feature—the ARM workaround should be followed.
Software workaround is not needed because this erratum will not be encountered in normal device
operation.
Chip Errata for the i.MX 6Dual/6Quad and i.MX 6DualPlus/6QuadPlus, Rev. 6.1, 06/2016
NXP Semiconductors 25
ERR003724
ERR003724 ARM: 754322—Possible faulty MMU translations following an ASID
switch
Description:
A microTLB entry might be corrupted following an ASID switch, possibly corrupting subsequent
MMU translations.
The erratum requires execution of an explicit memory access, which might be speculative. This
memory access misses in the TLB and cause a translation table walk. The erratum occurs when the
translation table walk starts before the ASID switch code sequence, but completes after the ASID
switch code sequence. In this case, a new entry is allocated in the microTLB for the TLB entry for
this translation table walk, but corresponding to the old ASID. Because the microTLB does not
record the ASID value, the new MMU translation, which should happen with the new ASID
following the ASID switch, might hit this stale microTLB entry and become corrupted.
Note that there is no Trustzone Security risk because the Security state of the access is held in the
microTLB, and cannot be corrupted.
Projected Impact:
The errata might cause MMU translation corruptions.
Workarounds:
The workaround for this erratum involves adding a DSB in the ASID switch code sequence. The
ARM architecture only mandates ISB before and after the ASID switch. Adding a DSB prior to the
ASID switch ensures that the Page T able W alk completes prior to the ASID change, so that no stale
entry can be allocated in the micro-TLB.
The examples in the ARM Architecture Reference Manual for synchronizing the change in the
ASID and TTBR need to be changed as follows:
The sequence:
becomes
the sequence:
Change ASID to 0
ISB
Change Translation Table Base Register
ISB
Change ASID to new value
DSB
Change ASID to 0
ISB
Change Translation Table Base Register
ISB
DSB
Change ASID to new value
Change Translation Table Base Register to the global-only mappings
ISB
Change ASID to new value
Chip Errata for the i.MX 6Dual/6Quad and i.MX 6DualPlus/6QuadPlus, Rev. 6.1, 06/2016
26 NXP Semiconductors
ISB
Change Translation Table Base Register to new value
becomes
Change Translation Table Base Register to the global-only mappings
ISB
DSB
Change ASID to new value
ISB
Change Translation Table Base Register to new value
and the sequence:
Set TTBCR.PD0 = 1
ISB
Change ASID to new value
Change Translation Table Base Register to new value
ISB
Set TTBCR.PD0 = 0
becomes
Set TTBCR.PD0 = 1
ISB
DSB
Change ASID to new value
Change Translation Table Base Register to new value
ISB
Set TTBCR.PD0 = 0
ERR003724
Proposed Solution:
No fix scheduled
Linux BSP Status:
Software workaround integrated in Linux BSP codebase starting in release imx_3.0.35_4.1.0.
Chip Errata for the i.MX 6Dual/6Quad and i.MX 6DualPlus/6QuadPlus, Rev. 6.1, 06/2016
NXP Semiconductors 27
ERR003725
ERR003725 ARM: 725631—ISB is counted in Performance Monitor events 0x0C
and 0x0D
Description:
The ISB is implemented as a branch in the Cortex-A9 micro-architecture. This implies that events
0x0C (software change of PC) and 0x0D (immediate branch) are asserted when an ISB occurs. This
is not compliant with the ARM architecture.
Projected Impact:
The count of events 0x0C and 0x0D are not 100% precise when using the Performance Monitor
counters, due to the ISB being counted in addition to the real software changes to PC (for 0x0C)
and immediate branches (0x0D).
The erratum also causes the corresponding PMUEVENT bits to toggle in case an ISB is executed.
• PMUEVENT[13] relates to event 0x0C
• PMUEVENT[14] relates to event 0x0D
Workarounds:
Count ISB instructions along with event 0x90. The user should subtract this ISB count from the
results obtained in events 0x0C and 0x0D, to obtain the precise count of software change of PC
(0x0C) and immediate branches (0x0D).
Proposed Solution:
No fix scheduled
Linux BSP Status:
Software workaround is not needed because this erratum will not be encountered in normal device
operation.The Freescale Linux BSP does not support this optional profiling feature. Users may add
support for this profiling feature as required, but should ensure the multiple errata impacting the
ARM PMU are considered especially for multi-core usage.
Chip Errata for the i.MX 6Dual/6Quad and i.MX 6DualPlus/6QuadPlus, Rev. 6.1, 06/2016
28 NXP Semiconductors
ERR003726
ERR003726 ARM: 729817—MainID register alias addresses are not mapped on
Debug APB interface
Description:
The ARM Debug Architecture specifies registers 838 and 839 as “Alias of the MainID register”.
They should be accessible through the APB Debug interface at addresses 0xD18 and 0xD1C.
In Cortex-A9, the two alias addresses are not implemented. A read access at any of these two
addresses returns 0, instead of the MIDR value.
Note that read accesses to these two registers through the internal CP14 interface are trapped to
UNDEF , which is compliant with the ARM Debug architecture. So, the erratum only applies to the
alias addresses through the external Debug APB interface.
Projected Impact:
If the debugger or any other external agent tries to read the MIDR register using the alias addresses,
it will get a faulty answer (0x0), which can cause all sorts of malfunction in the debugger
afterwards.
Workarounds:
The workaround for this erratum requires always accessing the MIDR at its original address,
0xD00, and not at any of its alias addresses.
Proposed Solution:
No fix scheduled
Linux BSP Status:
Software workaround is not needed because this erratum will not be encountered in normal device
operation.
Chip Errata for the i.MX 6Dual/6Quad and i.MX 6DualPlus/6QuadPlus, Rev. 6.1, 06/2016
NXP Semiconductors 29
ERR003727
ERR003727 ARM: 729818—In debug state, next instruction is st alled when sdabort
flag is set, instead of being discarded
Description:
When the processor is in debug state, an instruction written to the ITR after a Load/Store
instruction that aborts gets executed on clearing the SDABORT_l, instead of being discarded.
Projected Impact:
Different failures can happen due to the instruction being executed when it should not. In most
cases, it is expected that the failure will not cause any significant problem.
Workarounds:
There are a selection of workarounds with increasing complexity and decreasing impact. In each
case, the impact is a loss of performance when debugging:
• Do not use stall mode
• Do not use stall mode when doing load/store operations
• Always check for a sticky abort after issuing a load/store operation in stall mode (the cost of this
probably means the above second workaround is a preferred alternative)
• Always check for a sticky abort after issuing a load/store operation in stall mode, before issuing
any further instructions that might corrupt important target state (such as, further load/store
instructions, instructions that write to “live” registers [VFP, CP15, etc.])
Proposed Solution:
No fix scheduled
Linux BSP Status:
Software workaround is not needed because this erratum will not be encountered in normal device
operation.
Chip Errata for the i.MX 6Dual/6Quad and i.MX 6DualPlus/6QuadPlus, Rev. 6.1, 06/2016
30 NXP Semiconductors
Loading...