NXP Semiconductors CBT3126 User Manual

CBT3126

Quad FET bus switch

Rev. 02 — 23 October 2008 Product data sheet

1. General description

The CBT3126 is a quadruple FET bus switch features independent line switches. Each
switch is disabled when the associated Output Enable (OE) input is LOW.

The CBT3126 is characterized for operation from −40 °Cto+85°C.

2. Features

n Standard ’126-type pinout
n Multiple package options
n 5 Ω switch connection between two ports
n TTL-compatible input levels
n Minimal propagation delay through the switch
n Latch-up protection exceeds 500 mA per JEDEC standard JESD78 class II level A
n ESD protection:

u HBM JESD22-A114E exceeds 2000 V
u MM JESD22-A115-A exceeds 200 V
u CDM JESD22-C101C exceeds 1000 V

n Specified from −40 °Cto+85°C

3. Ordering information

Table 1. Ordering information

Type number Temperature range Package

Name Description Version

CBT3126D −40 °Cto+85°C SO14 plastic small outline package; 14 leads;

body width 3.9 mm

CBT3126DB −40 °Cto+85°C SSOP14 plastic shrink small outline package; 14 leads;

body width 5.3 mm

SOT108-1

SOT337-1

NXP Semiconductors

CBT3126

Quad FET bus switch

Table 1. Ordering information

…continued

Type number Temperature range Package

Name Description Version

CBT3126DS −40 °Cto+85°C SSOP16

[1]

plastic shrink small outline package; 16 leads;
body width 3.9 mm; leadpitch 0.635 mm

CBT3126PW −40 °Cto+85°C TSSOP14 plastic thin shrink small outline package; 14 leads;

body width 4.4 mm

[1] Also known as QSOP16.

4. Functional diagram

23

1OE

1A 1B

2OE

2A 2B

3OE

3A 3B

4OE

4A 4B

001aaj023

1A

1

1OE

56

2A

4

2OE

98

3A

10

3OE

12 11

4A

13

4OE

001aaj024

SOT519-1

SOT402-1

1B

2B

3B

4B

Pin numbers are for the 14 pin packages.

Fig 1. Logic symbol Fig 2. Logic diagram

CBT3126_2 © NXP B.V. 2008. All rights reserved.

Product data sheet Rev. 02 — 23 October 2008 2 of 15

NXP Semiconductors

5. Pinning information

5.1 Pinning

CBT3126

1

1OE V

2

1A 4OE

3

1B 4A

4

2OE 4B

5

2A 3OE

6

2B 3A

7

GND 3B

001aaj025

CBT3126

Quad FET bus switch

CBT3126

1

n.c. V

14

CC

13
12
11
10

9
8

2

1OE 4OE

3

1A 4A

4

1B 4B

5

2OE 3OE

6

2A 3A

7

2B 3B

8

GND n.c.

001aaj026

16

CC

15
14
13
12
11
10

9

Fig 3. Pin configuration SOT108-1 (SO14), SOT337-4

Fig 4. Pin configuration SOT519-1 (SSOP16)

(SSOP14) and SOT402-1 (TSSOP14)

5.2 Pin description

Table 2. Pin description

Symbol Pin SOT108-1 SOT337-4

Pin SOT519-1 Description

and SOT402-1

1OE to 4OE 1, 4, 10, 13 2, 5, 12, 15 output enable input
1A to 4A, 2, 5, 9, 12 3, 6, 11, 14 A input/output
1B to 4B 3, 6, 8, 11 4, 7, 10, 13 B output/input
GND 7 8 ground (0 V)
V

CC

14 16 positive supply voltage

n.c. - 1, 9 not connected

6. Functional description

Table 3. Function selection

H = HIGH voltage level; L = LOW voltage level.

Inputs Switch
nOE

L nA to nB disconnected
H nA to nB connected

CBT3126_2 © NXP B.V. 2008. All rights reserved.

Product data sheet Rev. 02 — 23 October 2008 3 of 15

NXP Semiconductors

CBT3126

Quad FET bus switch

7. Limiting values

Table 4. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol Parameter Conditions Min Max Unit

V

CC

V

I

I

CC

I

IK

T

stg

P

tot

[1] The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed.
[2] The package thermal impedance is calculated from JESD51-7.
[3] For SO14 package; P
[4] For SSOP14, SSOP16 and TSSOP14 packages; P

supply voltage −0.5 +7.0 V
input voltage

[1]

−0.5 +7.0 V
supply current continuous current through each VCC or GND pin - 128 mA
input clamping current VI<0V −50 - mA
storage temperature −65 +150 °C
total power dissipation T

derates linearly with 8 mW/K above 70 °C.

tot

= −40 °C to +125 °C

amb

SO14 package
SSOP14 and SSOP16 package
TSSOP14 package

derates linearly with 5.5 mW/K above 70 °C.

tot

[2]
[3]

- 500 mW

[4]

- 500 mW

[4]

- 500 mW

8. Recommended operating conditions

Table 5. Operating conditions

All unused control inputs of the device must be held at VCC or GND to ensure proper device operation.

Symbol Parameter Conditions Min Max Unit

V

CC

V

IH

V

IL

T

amb

supply voltage 4.5 5.5 V
HIGH-level input voltage 2.0 - V
LOW-level input voltage - 0.8 V
ambient temperature operating in free-air −40 +85 °C

9. Static characteristics

Table 6. Static characteristics

T

=−40°C to +85°C.

amb

Symbol Parameter Conditions Min Typ

V
V
I
I

∆I

C
C

I
CC

IK
pass

CC

I
io(off)

input clamping voltage VCC= 4.5 V; II= −18 mA - - −1.2 V
pass voltage VI=VCC= 5.0 V; IO= −100 µA - 3.8 - V
input leakage current VCC= 5.5 V; VI= GND or 5.5 V - - ±1 µA
supply current VCC= 5.5 V; IO= 0 mA;

V

I=VCC

or GND

additional supply current control pins; per input;

V

= 5.5 V; one input at 3.4 V,

CC

other inputs at V

or GND

CC

--3µA

[2]

- - 2.5 mA

input capacitance control pins; VI= 3 V or 0 V - 1.7 - pF
off-state input/output capacitance VO=3V or 0V;OE = V

CC

- 3.4 - pF

[1]

Max Unit

CBT3126_2 © NXP B.V. 2008. All rights reserved.

Product data sheet Rev. 02 — 23 October 2008 4 of 15

NXP Semiconductors

CBT3126

Quad FET bus switch

Table 6. Static characteristics

T

=−40°C to +85°C.

amb

Symbol Parameter Conditions Min Typ

R

ON

ON resistance VCC= 4.0 V

…continued

[1]

Max Unit

[3]

VI= 2.4 V; II= 15 mA - 16 22 Ω

= 4.5 V

V

CC

=0V; II=64mA - 5 7 Ω

V

I

=0V; II=30mA - 5 7 Ω

V

I

= 2.4 V; II= 15 mA - 10 15 Ω

V

I

[1] All typical values are measured at VCC=5V; T

amb

=25°C.
[2] This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND.
[3] Measured by the voltage drop between the A and the B terminals at the indicated current through the switch. ON resistance is

determined by the lowest voltage of the two (A or B) terminals.

10. Dynamic characteristics

Table 7. Dynamic characteristics

T

=−40°C to +85°C; VCC= 4.5 V to 5.5 V; for test circuit see Figure 7.

amb

Symbol Parameter Conditions Min Max Unit

t

pd

t

en

t

dis

propagation delay nA to nB or nB to nA; see Figure 5
enable time OE to nA or nB; see Figure 6
disable time OE to nA or nB; see Figure 6

[1][2]

- 0.25 ns

[2]

1.6 4.5 ns

[2]

1.0 5.4 ns

[1] This parameter is warranted but not production tested. The propagation delay is based on the RC time constant of the typical ON

resistance of the switch and a load capacitance, when driven by an ideal voltage source (zero output impedance).

[2] t

t
t

PLH
PZL
PLZ

and t
and t
and t

are the same as tpd;

PHL

are the same as ten;

PZH

are the same as t

PHZ

.

dis

11. AC waveforms

V

I

input

0 V

V

OH

output

V

OL

V

M

t

PHL

V

M

Measurement points are given in Table 8.
VOL and VOH are typical voltage output levels that occur with the output load.

Fig 5. The input (nA, nB) to output (nB, nA) propagation delay times

V

M

t

PLH

V

M

001aai367

CBT3126_2 © NXP B.V. 2008. All rights reserved.

Product data sheet Rev. 02 — 23 October 2008 5 of 15