NXP TDA18218HN DATA SHEET

现货库存、技术资料、百科信息、热点资讯，精彩尽在鼎好!

TDA18218HN

DVB-T Silicon Tuner IC

Rev. 01 — 8 July 2009 Product data sheet

1. General description

The TDA18218HN is a Silicon Tuner IC designed for digital terrestrial (DVB-T) TV
reception. The TDA18218HN integrates the overall tuning function, including selectivity
and provides a low-IF output signal.

The TDA18218HN uses integrated IF filters to support 6 MHz, 7 MHz or 8 MHz channel
bandwidths. The TDA18218HN requires only one single 16 MHz crystal for clock
generation. A clock signal is available on crystal oscillator output pins (XTO_P / XTO_N)
to synchronize the channel decoder.

The TDA18218HN is a low cost Silicon Tuner targeting digital terrestrial applications. The
TDA18218HN matches the performance of the conventional can tuners. Additionally, the
following benefits can be stated:

2. Features

• Easy on-board integration

• Drastically reduces:

– the size of the tuner function
– the power consumption

n Fully integrated IF selectivity; eliminating the need for external SAW filters
n Fully integrated oscillators with no external components
n Integrated wideband gain control
n Alignment free
n RF loop-through for easy implementation in the Set-Top Box (STB)
n Integrated die thermal sensor
n Single 3.3 V power supply
n Low power consumption (750 mW)
n Crystal oscillator output buffer (16 MHz) for single crystal applications
n I2C-bus interface compatible with 3.3 V and 5 V microcontrollers
n Three Standby modes
n RoHS packaging

3. Applications

n DVB-T Set-Top Box (STB) and TV receiver
n System application optimization is described in the application note
n Driver application is described in the application note

AN0814

AN0822

NXP Semiconductors

TDA18218HN

DVB-T Silicon Tuner IC

4. Quick reference data

Table 1. Quick reference data

T

=25°C; VCC= 3.3 V; IF output level option = 2 V (p - p); IF output load=1kΩ on each terminal

amb

Symbol Parameter Conditions Min Typ Max Unit

f

RF

NF

ϕ

n

P power dissipation - 775 - mW
V

i(max)

α

image

S

dig

[1] Measured with TDA10048 channel decoder.

RF frequency center of channel 174 - 864 MHz
tuner noise figure normal mode; maximum gain - 5 7 dB

tun

phase noise worst case in the RF frequency range

10 kHz - −85 - dBc/Hz
100 kHz - −105 - dBc/Hz

maximum input voltage 1 dB gain compression, one analog TV signal - 108 - dBµV
image rejection normal mode - 65 - dB
digital sensitivity DVB-T (64QAM 2/3); BER = 2 × 10

−4 [1]

- −82 - dBm

5. Ordering information

Table 2. Ordering information

Type number Package

TDA18218HN HVQFN48 plastic thermal enhanced very thin quad flat package;

6. Block diagram

AGC1

1

RF_IN

LEVEL

CONTROL

46

LT

ATTENUATOR

Name Description Version

SOT619-1

no leads; 48 terminals; body 7 × 7 × 0.85 mm

AGC2

LEVEL

CONTROL

INTERFACE

22

SCL

AS

BP

FILTER

mixer

IF

SELECTIVITY

LPFc

TDA18218HN

I2C

35

SDA

36

SYNTHESIZER

14

VTLO

CPLO

15

XTAL_P

IF

AGC

CRYSTAL

OSCILATOR

16

XTAL_N

31

IFO_P

30

IFO_N

32

VIFAGC

19

XTO_P

20

XTO_N

17

001aaj012

Fig 1. Block diagram

TDA18218HN_1 © NXP B.V. 2009. All rights reserved.

Product data sheet Rev. 01 — 8 July 2009 2 of 25

NXP Semiconductors

7. Pinning information

7.1 Pinning

TDA18218HN

DVB-T Silicon Tuner IC

index area

CAPREG_VCO REG28

Fig 2. Pin configuration

7.2 Pin description

terminal 1

1 36

RF_IN SDA

2 35

i.c. SCL

3 34

i.c. GND(DIG)

GND(RF) i.c.

GND(IF) IFO_N

V

GND(VCO)

V

CC(PLL)

4 33
5 32

i.c. VIFAGC

6 31

i.c. IFO_P

7 30
8 29

CC(IF)

9 28

i.c. GND(IF)

10 27
11 26
12 25

CC(RF)

i.c.
4847464544434241403938

CC(RF)

V

LT

V

GND(RF)

i.c.

GND(RF)

GND(RF)

GND(RF)

i.c.

TDA18218HN

1314151617181920212223

VTLO

CPLO

GND(PLL)

i.c.

XTAL_N

XTO_P

XTAL_P

Transparent top view

AS

XTO_N

XTAL_MS

GND(RF)

CAPRFAGC
37

24

CP_K

GND(IF)

V

CC(IF)

REG18
VT_K

001aaj013

Table 3. Pin description

Symbol Pin Description

RF_IN 1 unbalanced RF input
i.c. 2 internally connected; leave open
i.c. 3 internally connected; leave open
GND(RF) 4 RF ground
i.c. 5 internally connected; leave open
i.c 6 internally connected; leave open
GND(IF) 7 IF ground
V

CC(IF)

8 IF supply voltage (3.3 V)
i.c. 9 internally connected; leave open
CAPREG_VCO 10 VCO supply decoupling
GND(VCO) 11 VCO ground
V

CC(PLL)

12 PLL supply voltage
GND(PLL) 13 PLL ground
VTLO 14 local oscillator (LO) tuning voltage input

TDA18218HN_1 © NXP B.V. 2009. All rights reserved.

Product data sheet Rev. 01 — 8 July 2009 3 of 25

NXP Semiconductors

TDA18218HN

DVB-T Silicon Tuner IC

Table 3. Pin description

Symbol Pin Description

CPLO 15 charge pump of the LO synthesizer
XTAL_P 16 crystal oscillator input positive
XTAL_N 17 crystal oscillator input negative
i.c. 18 internally connected; leave open
XTO_P 19 crystal oscillator output buffer positive
XTO_N 20 crystal oscillator output buffer negative
XTAL_MS 21 XTAL out mode
AS 22 I
GND(IF) 23 IF ground
CP_K 24 charge pump of the calibration synthesizer
VT_K 25 tuning voltage of the calibration synthesizer
REG18 26 internal regulator decoupling
REG28 27 internal regulator decoupling
GND(IF) 28 IF ground
V

CC(IF)

IFO_N 30 IF output negative
IFO_P 31 IF output positive
VIFAGC 32 IF gain control input
i.c. 33 internally connected; leave open
GND(DIG) 34 digital ground
SCL 35 I
SDA 36 I
CAPRFAGC 37 RF AGC filtering
GND(RF) 38 RF ground
i.c. 39 internally connected; leave open
GND(RF) 40 RF ground
GND(RF) 41 RF ground
GND(RF) 42 RF ground
i.c. 43 internally connected; leave open
GND(RF) 44 RF ground
V

CC(RF)

LT 46 loop-through
V

CC(RF)

i.c. 48 internally connected; leave open

29 IF supply voltage (3.3 V)

45 RF supply voltage

47 RF supply voltage

…continued

2

C-bus address selection input

2

C-bus clock input

2

C-bus data input and output

8. Functional description

The RF input signal is driven to a low-noise amplifier. It is then amplified and fed to the
image rejection mixer.The mixer down-converts the RF signal to a low IF frequency,which
depends on channel bandwidth (standard IF filters are implemented for 6 MHz, 7 MHz

TDA18218HN_1 © NXP B.V. 2009. All rights reserved.

Product data sheet Rev. 01 — 8 July 2009 4 of 25

NXP Semiconductors

and 8 MHz channel bandwidths). The TDA18218HN requires a single 16 MHz crystal for
clock generation, a 16 MHz differential sine wave clock reference is available to drive a
channel decoder.

8.1 AGC1 stage

The TDA18218HN embeds 2 different RF amplifiers with internal gain control.
The first stage, AGC1, behaves like a LNA (Low noise amplifier); its gain can take 4

different values (15 dB, 12 dB, 9 dB and 6 dB). Purpose of this amplifier is to ensure a low
noise figure for the tuner.

In order to optimize noise and linearity performances an internal level detector selects the
appropriate gain:

• If the signal level at the tuner is low, the gain is set to the maximum value (15 dB).

• If the signal level at the tuner input is high, the gain is set to the minimum value (6 dB).

• In between the gain is set to an intermediate value 12 dB or 9 dB.

The strategy of the level detection is a proprietary algorithm from NXP, managed by the
driver.

TDA18218HN

DVB-T Silicon Tuner IC

It should be noted that:

1. The level detector measures the signal level within the complete RF frequency range,
i.e. from 50 MHz to 870 MHz. Consequently, AGC1 gain is adapted to the complete
RF power. If a strong signal is present at the tuner input, it will determine AGC1 gain
(even if it is not the wanted signal). This concept prevents the tuner from overloading.

2. The level control is always operating.

8.2 AGC2 stage

The second stage, AGC2, is also an amplifier with a gain controlled thanks to a level
detector.

The gain is controlled between −12 dB and +16.4 dB, it is adapted by steps of 0.2 dB.
It should be noted that:

1. The level control is always operating. Consequently, this amplifier is responsible for
adapting the daily level changes.

2. The level detector measures the signal level within the complete RF frequency range
(same as AGC1)

The strategy of the level detection is a proprietary algorithm from NXP, managed by the
driver.

8.3 IF AGC

Finally, in order to adapt the tuner output level, a last amplifier is used (IF AGC). This
amplifier delivers the appropriate level to the DVB-T channel decoder. The output level is
therefore controlled thanks to the DC voltage applied on VIFAGC pin. This voltage is
commonly delivered by the channel decoder.

TDA18218HN_1 © NXP B.V. 2009. All rights reserved.

Product data sheet Rev. 01 — 8 July 2009 5 of 25

NXP Semiconductors

It should be noted that the level control is always operating.
The strategy of the level detection has to be adapted for each type of channel decoder. It

must be defined to satisfy ADC sampling (minimum level, ADC headroom).
All AGC amplifiers are controlled independently.

8.4 Power-down mode

The TDA18218HN can be programmed in Standby mode. The following blocks are turned
off when programming a power-down:

• AGC2 and its level detector

• BP filter

• Mixer and VCO

• IF selectivity LPFc

• IF AGC

Remaining functions are:

TDA18218HN

DVB-T Silicon Tuner IC

• Loop-Through

• 16 MHz clock output (to drive a channel decoder)

2

• I

C-bus Core (to wake-up the IC later on)

9. Control interface

9.1 I2C-bus format, write and read mode

I2C-bus uses two pins (SDA and SCL) to transfer information between devices connected
to the bus. The SDA pin provides bidirectional data transfer. While the SCL pin provides
the timing sequences. Data can be read and written as follows:

Write mode:

• Any register can be written to using its subaddress

• Any following (contiguous) registers can be written using the subaddress of the first

register

Read mode:

• The read after Restart mode is not allowed.In addition, registers cannot be read using

the subaddress of the register. However, registers can be read as follows:

– from 00h to 16h
– from 00h to 27h
– from 00h to 3Ah
– from 00h to any register subaddress, if MSB = 1 for the next register

TDA18218HN_1 © NXP B.V. 2009. All rights reserved.

Product data sheet Rev. 01 — 8 July 2009 6 of 25

NXP Semiconductors

TDA18218HN

DVB-T Silicon Tuner IC

POR

(Hex)

value

(Hex)

[1]

C0

-0908

-FF01

-D0F0

-4040

-8484

-0000

-1313

-0000

LO_Frac_1[23:16] 00 00

LO_Frac_0[31:24] 00 00

LO_Frac_2[15:12] - 07 00

7 (MSB) 6 5 4 3 2 1 0 (LSB)

C-bus register map

xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx

xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x

2

xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx

xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx

Register Bit Initial

Address byte 1 1 1 0 0 0 MA[1:0] R/W - -

Address byte 2 0 0 AD[5:0] - -

byte 1

byte 2

byte 3

byte 4

byte 5

byte 6

- Freq_prog_

byte 7

Start

byte 8

byte 1

byte 2

byte 3

0Dh Main divider

0Eh Main divider

0Fh Main divider

10h Call divider

11h Call divider

0Ch Main divider

01h Read byte 1 - LO_Lock CAL_Lock - TM_D[3:0] 88 80

02h Read byte 2 - 00 00

03h Read byte 3 AGC2[7:0] 8E 3C

04h Read byte 4 AGC1[2] - LT[1:0] AGC1[1:0] 03 00

05h Read byte 5 - 00 00

06h Read byte 6 - 00 00

07h Main divider

08h PSM byte 1 - 00 00

Sub

address

Table 4. I

TDA18218HN_1 © NXP B.V. 2009. All rights reserved.

Product data sheet Rev. 01 — 8 July 2009 7 of 25

00h ID byte 1 ID[6:0] C0

09h Main divider

0Bh Main divider

0Ah Main divider

12h Call divider

NXP Semiconductors

POR

(Hex)

(Hex)

value

[2]

B5

SM F0

[3]

TDA18218HN

DVB-T Silicon Tuner IC

59

[2]59[3]

B0

Synthe

PD_LO_

_Ifout

-0000

-0101

-8484

-0909

- pdDETECT1 pdAGC2b - 19
AGC_On - 98 98

width[1:0]

pulse_up_

AGC1_au_ptr[1:0] 58 58

aud_sel

Manual_LT AGC1_aud[2:0] 10 00

AGC1_

Gup_sel

Gup_sel

- IFAGC_Top[3:0] 48 48

_LT_RFin

- pdLT - pdAGC1b PD_RFAGC

17h Power-down

byte 1

- RFSW_MTO

18h Power-down

byte 2

19h XTOUT byte - XtOut[3:0] 0A 0A

1Ah IF byte 1 - IF_level[2:0] - BP_Filter[2:0] 8E 86

1Bh IF byte 2 - LP_Fc[1:0] 69 6A

…continued

7 (MSB) 6 5 4 3 2 1 0 (LSB)

C-bus register map

xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx

xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x

2

xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx

xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx

Register Bit Initial

Sub

address

Table 4. I

TDA18218HN_1 © NXP B.V. 2009. All rights reserved.

Product data sheet Rev. 01 — 8 July 2009 8 of 25

byte 4

13h Call divider

14h Call divider

byte 5

15h Call divider

byte 6

16h Call divider

byte 7

TM_ON - 01 C3

auto

1Dh PSM byte 2 TM_

1Ch AGC2b byte pulse_up_

Range

1Eh PSM byte 3 - 00 00

1Fh PSM byte 4 AGC1_Speed[1:0] - AGC1_

20h AGC1 byte 1 AGC2_RAM_sel[1:0] AGC2_

21h AGC1 byte 2 AGC2_Speed[1:0] - AGC1_Gud[4:0] 40 40

22h AGC1 byte 3 - 8C 80

23h AGC2 byte 1 - AGC2_Gud[4:0] 00 00

24h AGC2 byte 2 - 0C 0C

byte

25h Analog AGC

26h RC byte - 85 80

27h RSSI byte - C9 8E