PCF8563
Real time clock/calendar
Rev. 04 — 12 March 2004 Product data
1. General description
The PCF8563 is a CMOS real time clock/calendar optimized for low power
consumption. A programmableclockoutput,interruptoutputandvoltage-low detector
are also provided. All address and data are transferred serially via a two-line
bidirectional I2C-bus. Maximum bus speed is 400 kbit/s. The built-in word address
register is incremented automatically after each written or read data byte.
2. Features
■ Provides year, month, day, weekday, hours, minutes and seconds based on
32.768 kHz quartz crystal
■ Century flag
■ Clock operating voltage: 1.8 V to 5.5 V
■ Low backup current; typical 0.25 µA at VDD= 3.0 V and T
■ 400 kHz two-wire I2C-bus interface (at VDD= 1.8 V to 5.5 V)
■ Programmable clock output for peripheral devices (32.768 kHz, 1024 Hz,
32 Hz and 1 Hz)
■ Alarm and timer functions
■ Integrated oscillator capacitor
■ Internal power-on reset
■ I2C-bus slave address: read A3H and write A2H
■ Open-drain interrupt pin.
amb
=25°C
3. Applications
■ Mobile telephones
■ Portable instruments
■ Fax machines
■ Battery powered products.
Philips Semiconductors
PCF8563
Real time clock/calendar
4. Quick reference data
Table 1: Quick reference data
Symbol Parameter Conditions Min Typ Max Unit
V
DD
I
DD
supply voltage operating; I2C-bus inactive; T
2
operating; I
T
amb
C-bus active; f
= −40 °C to +125 °C
supply current timer and clock output disabled;
= 400 kHz
f
SCL
timer and clock output disabled;
f
= 100 kHz
SCL
timer and clock output disabled;
f
= 0 Hz; T
SCL
= 5 V - - 550 nA
V
DD
= 2 V - - 450 nA
V
DD
T
amb
T
stg
ambient temperature operating −40 - +85 °C
storage temperature −65 - +150 °C
amb
=25°C
=25°C 1.0 - 5.5 V
amb
= 400 kHz;
SCL
1.8 - 5.5 V
- - 800 µA
- - 200 µA
5. Ordering information
Table 2: Ordering information
Type number Package
Name Description Version
PCF8563P DIP8 plastic dual in-line package; 8 leads (300 mil) SOT97-1
PCF8563T SO8 plastic dual in-line package; 8 leads; body width 3.9 mm SOT96-1
PCF8563TS TSSOP8 plastic thin shrink small outline package; 8 leads; body width 3 mm SOT505-1
9397 750 12999
Product data Rev. 04 — 12 March 2004 2 of 30
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Philips Semiconductors
6. Block diagram
PCF8563
Real time clock/calendar
CLKOUT
INT
SS
DD
1
2
3
4
8
6
5
OSCILLATOR
OSCILLATOR
OSCI
OSCO
V
V
SCL
SDA
Fig 1. Block diagram.
7. Pinning information
32.768 kHz
VOLTAGE
DETECTOR
MONITOR
I2C-BUS
INTERFACE
POR
PCF8563
DIVIDER
CONTROL
LOGIC
ADDRESS
REGISTER
7
CONTROL/STATUS 1
1 Hz
CONTROL/STATUS 2
SECONDS/VL
MINUTES
HOURS
DAYS
WEEKDAYS
MONTHS/CENTURY
YEARS
MINUTE ALARM
HOUR ALARM
DAY ALARM
WEEKDAY ALARM
CLKOUT CONTROL
TIMER CONTROL
TIMER
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
MGM662
7.1 Pinning
OSCI
INT
V
SS
1
2
PCF8563P
3
4
MCE403
V
8
DD
CLKOUTOSCO
7
SCL
6
SDA
5
OSCI
INT
V
SS
1
2
3
4
PCF8563T
MCE198
Fig 2. Pin configuration DIP8. Fig 3. Pin configuration SO8. Fig 4. Pin configuration TSSOP8.
V
8
DD
CLKOUTOSCO
7
SCL
6
SDA
5
OSCI
INT
V
SS
1
2
PCF8563TS
3
4
MCE199
V
8
DD
CLKOUTOSCO
7
SCL
6
SDA
5
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Product data Rev. 04 — 12 March 2004 3 of 30
Philips Semiconductors
handbook, halfpage
OSCI
PCF8563
Real time clock/calendar
1
8
V
DD
OSCO
Fig 5. Device diode protection diagram.
7.2 Pin description
Table 3: Pin description
Symbol Pin Description
OSCI 1 oscillator input
OSCO 2 oscillator output
INT 3 interrupt output (open-drain; active LOW)
V
SS
SDA 5 serial data input and output
SCL 6 serial clock input
CLKOUT 7 clock output, open-drain
V
DD
7
6
5
MGR886
V
INT
SS
2
3
4
PCF8563
4 ground
8 positive supply voltage
CLKOUT
SCL
SDA
8. Functional description
The PCF8563 contains sixteen 8-bit registers with an auto-incrementing address
register, an on-chip 32.768 kHz oscillator with one integrated capacitor, a frequency
divider which provides the source clock for the Real Time Clock/calender (RTC), a
programmable clock output, a timer, an alarm, a voltage-low detector and a 400 kHz
I2C-bus interface.
All 16 registers are designed as addressable 8-bit parallel registers although not all
bits are implemented. The first two registers (memory address 00H and 01H) are
used as control and/or status registers. The memory addresses 02H through 08H are
used as counters for the clock function (seconds up to years counters). Address
locations 09H through 0CH contain alarm registers which define the conditions for an
alarm. Address 0DH controls the CLKOUT output frequency. 0EH and 0FH are the
timer control and timer registers, respectively.
The seconds, minutes, hours, days, weekdays, months, years as well as the minute
alarm, hour alarm, day alarm and weekday alarm registers are all coded in BCD
format.
When one of the RTC registers is read the contents of all counters are frozen.
Therefore, faulty reading of the clock/calendar during a carry condition is prevented.
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Product data Rev. 04 — 12 March 2004 4 of 30
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Philips Semiconductors
8.1 Alarm function modes
By clearing the MSB of one or more of the alarm registers (bit AE = alarm enable),
the corresponding alarm condition(s) will be active. In this way an alarm can be
generated from once per minute up to once per week. The alarm condition sets the
Alarm Flag (AF). The asserted AF can be used to generateaninterrupt (INT).TheAF
can only be cleared by software.
8.2 Timer
The 8-bit countdown timer at address 0FH is controlled by the timer control register at
address 0EH. The timer control register determines one of 4 source clock
frequencies for the timer (4096 Hz, 64 Hz, 1 Hz, or1⁄60Hz), and enables or disables
the timer. The timer counts down from a software-loaded 8-bit binary value. At the
end of every countdown, the timer sets the Timer Flag (TF). The TF may only be
cleared by software.Theasserted TF can be used to generate an interrupt (INT). The
interrupt may be generated as a pulsed signal every countdown period or as a
permanently active signal which follows the condition of TF. Bit TI/TP is used to
control this mode selection. When reading the timer, the current countdown value is
returned.
PCF8563
Real time clock/calendar
8.3 Clock output
A programmable square wave is available at pin CLKOUT. Operation is controlled by
the CLKOUT control register at address 0DH. Frequencies of 32.768 kHz (default),
1024 Hz, 32 Hz and 1 Hz can be generated for use as a system clock,
microcontroller clock, input to a charge pump, or for calibration of the oscillator.
CLKOUT is an open-drain output and enabled at power-on. If disabled it becomes
high-impedance.
8.4 Reset
The PCF8563 includes an internal reset circuit which is active whenever the oscillator
is stopped. In the reset state the I2C-bus logic is initialized and all registers, including
the address pointer, are cleared with the exception of bits FE, VL, TD1, TD0, TESTC
and AE which are set to logic 1.
8.5 Voltage-low detector
The PCF8563 has an on-chip voltage-low detector. When VDD drops below V
bit VL in the seconds register is set to indicate that the integrity of the clock
information is no longer guaranteed. The VL flag can only be cleared by software.
Bit VL is intended to detect the situation when VDD is decreasing slowly, for example
under battery operation. Should VDD reach V
bit VL will be set. This will indicate that the time may be corrupted.
before power is re-asserted then
low
low
,
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Product data Rev. 04 — 12 March 2004 5 of 30
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Philips Semiconductors
PCF8563
Real time clock/calendar
handbook, halfpage
V
DD
V
low
period of battery
operation
VL set
MGR887
normal power
operation
t
Fig 6. Voltage-low detection.
8.6 Register organization
Table 4: Binary formatted registers overview
Bit positions labelled as x are not implemented. Bit positions labelled with 0 should always be written with logic 0; if read they
could be either logic 0 or logic 1.
Address Register name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
00H control/status 1 TEST1 0 STOP 0 TESTC 0 0 0
01H control/status 2 0 0 0 TI/TP AF TF AIE TIE
0DH CLKOUT control FE xxxxxFD1FD0
0EH timer control TE xxxxxTD1TD0
0FH timer <timer countdown value>
Table 5: BCD formatted registers overview
Bit positions labelled as x are not implemented.
Address Register name BCD format tens nibble BCD format units nibble
Bit 7
3
2
Bit 6
2
2
Bit 5
1
2
Bit 4
0
2
Bit 3
3
2
Bit 2
2
2
Bit 1
1
2
Bit 0
0
2
02H seconds VL <seconds 00 to 59 coded in BCD>
03H minutes x <minutes 00 to 59 coded in BCD>
04H hours x x <hours 00 to 23 coded in BCD>
05H days x x <days 01 to 31 coded in BCD>
06H weekdays xxxxx <weekdays 0 to 6>
07H months/century C x x <months 01 to 12 coded in BCD>
08H years <years 00 to 99 coded in BCD>
09H minute alarm AE <minute alarm 00 to 59 coded in BCD>
0AH hour alarm AE x <hour alarm 00 to 23 coded in BCD>
0BH day alarm AE x <day alarm 01 to 31 coded in BCD>
0CH weekday alarm AE xxxx <weekday alarm 0 to 6>
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Philips Semiconductors
PCF8563
Real time clock/calendar
8.6.1 Control/status 1 register
Table 6: Control/status 1 (address 00H) bits description
Bit Symbol Value Description
7 TEST1 0 normal mode
1 EXT_CLK test mode
6 0 default value is logic 0
5 STOP 0 RTC source clock runs
1 all RTC divider chain flip-flops are asynchronously set to logic 0; the RTC clock is
stopped (CLKOUT at 32.768 kHz is still available)
4 0 default value is logic 0
3 TESTC 0 Power-on reset override facility is disabled; set to logic0 for normal operation
1 Power-on reset override may be enabled
2 to 0 0 default value is logic 0
8.6.2 Control/status 2 register
Bits TF and AF: When an alarm occurs, AF is set to 1. Similarly, at the end of a timer
countdown, TF is set to 1. These bits maintain their value until overwritten by
software. If both timer and alarm interrupts are required in the application, the source
of the interrupt can be determined by reading these bits. To prevent one flag being
overwritten while clearing another a logic AND is performed during a write access.
Bits TIE and AIE: These bits activate or deactivate the generation of an interrupt
when TF or AF is asserted, respectively. The interrupt is the logical OR of these two
conditions when both AIE and TIE are set.
Table 7: Control/status 2 (address 01H) bits description
Bit Symbol Value Description
7 to 5 0 default value is logic 0
4 TI/TP 0
1
3 AF 0 (read) alarm flag inactive
1 (read) alarm flag active
0 (write) alarm flag is cleared
1 (write) alarm flag remains unchanged
2 TF 0 (read) timer flag inactive
1 (read) timer flag active
0 (write) timer flag is cleared
1 (write) timer flag remains unchanged
1 AIE 0 alarm interrupt disabled
1 alarm interrupt enabled
0 TIE 0 timer interrupt disabled
1 timer interrupt enabled
INT is active when TF is active (subject to the status of TIE)
INT pulses active according to Table 8 (subject to the status of TIE); note that if
AF and AIE are active then
INT will be permanently active
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Product data Rev. 04 — 12 March 2004 7 of 30
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Philips Semiconductors
PCF8563
Real time clock/calendar
Table 8: INT operation (bit TI/TP = 1)
Source clock (Hz) INT period (s)
[2]
n=1
1
1
1
1
⁄
8192
⁄
128
⁄
64
⁄
64
4096
64
1
1
⁄
60
[1] TF and INT become active simultaneously.
[2] n = loaded countdown value. Timer stopped when n = 0.
[1]
n>1
1
⁄
4096
1
⁄
64
1
⁄
64
1
⁄
64
8.6.3 Time and date registers
Table 9: Seconds/VL (address 02H) bits description
Bit Symbol Value Description
7 VL 0 clock integrity is guaranteed
1 integrity of the clock information is no longer guaranteed
6 to 0 seconds 00 to 59 this register holds the current seconds coded in BCD format; example: seconds
register contains x101 1001 = 59 seconds
Table 10: Minutes (address 03H) bits description
Bit Symbol Value Description
6 to 0 minutes 00 to 59 this register holds the current minutes coded in BCD format
Table 11: Hours (address 04H) bits description
Bit Symbol Value Description
5 to 0 hours 00 to 23 this register holds the current hours coded in BCD format
Table 12: Days (address 05H) bits description
Bit Symbol Value Description
5 to 0 days
[1] The PCF8563 compensates for leap years by adding a 29th day to February if the year counter contains a value which is exactly
divisible by 4, including the year00.
[1]
01 to 31 this register holds the current day coded in BCD format
Table 13: Weekdays (address 06H) bits description
Bit Symbol Value Description
[1]
2 to 0 weekdays
[1] These bits may be re-assigned by the user.
0 to 6 this register holds the current weekday coded in BCD format, see Table 14
Table 14: Weekday assignments
Day Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Sunday xxxxx000
Monday xxxxx001
Tuesday xxxxx010
Wednesday xxxxx011
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Philips Semiconductors
PCF8563
Real time clock/calendar
Table 14: Weekday assignments
Day Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Thursday xxxxx100
Friday xxxxx101
Saturday xxxxx110
Table 15: Months/century (address 07H) bits description
Bit Symbol Value Description
7 century
4 to 0 month 01 to 12 this register holds the current month coded in BCD format, see Table 16
[1] These bits may be re-assigned by the user.
[1]
0 indicates the century is 20xx
1 indicates the century is 19xx
Table 16: Month assignments
Month Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
January Cxx00001
February Cxx00010
March C x x 00011
April Cxx00100
May Cxx00101
June Cxx00110
July Cxx00111
August C x x 01000
September C x x 01001
October C x x 10000
November C x x 10001
December C x x 10010
this bit is toggled when the years register overflows from 99 to 00
…continued
Table 17: Years (address 08H) bits description
Bit Symbol Value Description
7 to 0 years 00 to 99 this register holds the current year coded in BCD format
8.6.4 Alarm registers
When one or more of these registers are loaded with a valid minute, hour, day or
weekday and its corresponding bit Alarm Enable (AE) is logic 0, then that information
will be compared with the current minute, hour, day and weekday. When all enabled
comparisons first match, the Alarm Flag (AF) is set. AF will remain set until cleared
by software. Once AF has been cleared it will only be set again when the time
increments to match the alarm condition once more. Alarm registers which have their
bit AE at logic 1 will be ignored.
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Philips Semiconductors
PCF8563
Real time clock/calendar
Table 18: Minute alarm (address 09H) bits description
Bit Symbol Value Description
7 AE 0 minute alarm is enabled
1 minute alarm is disabled
6 to 0 alarm minutes 00 to 59 this register holds the minute alarm information coded in BCD format
Table 19: Hour alarm (address 0AH) bits description
Bit Symbol Value Description
7 AE 0 hour alarm is enabled
1 hour alarm is disabled
5 to 0 alarm hours 00 to 23 this register holds the hour alarm information coded in BCD format
Table 20: Day alarm (address 0BH) bits description
Bit Symbol Value Description
7 AE 0 day alarm is enabled
1 day alarm is disabled
5 to 0 alarm days 01 to 31 this register holds the day alarm information coded in BCD format
Table 21: Weekday alarm (address 0CH) bits description
Bit Symbol Value Description
7 AE 0 weekday alarm is enabled
1 weekday alarm is disabled
2 to 0 alarm
weekdays
0 to 6 this register holds the weekday alarm information coded in BCD format
8.6.5 Clock output control register
Table 22: CLKOUT control (address 0DH) bits description
Bit Symbol Value Description
7 FE 0 the CLKOUT output is inhibited and CLKOUT output is set to high-impedance
1 the CLKOUT output is activated
1 to 0 FD1 and
FD0
Table 23: FD1 and FD0: CLKOUT frequency selection
FD1 FD0 CLKOUT frequency
0 0 32.768 kHz
0 1 1024 Hz
1032Hz
111Hz
these bits control the frequency output at pin CLKOUT; see Table 23
8.6.6 Countdown timer
The timer register is an 8-bit binary countdown timer. It is enabled and disabled via
the timer control register bit TE. The source clock for the timer is also selected by the
timer control register. Other timer properties such as interrupt generation are
controlled via control/status 2 register.
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Product data Rev. 04 — 12 March 2004 10 of 30
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