PCA9555
16-bit I2C-bus and SMBus I/O port with interrupt
Rev. 08 — 22 October 2009 Product data sheet
1. General description
The PCA9555 is a 24-pin CMOS device that provides 16 bits of General Purpose parallel
Input/Output (GPIO) expansion for I2C-bus/SMBus applications and was developed to
enhance the NXP Semiconductors family of I2C-bus I/O expanders. The improvements
include higher drive capability, 5 V I/O tolerance, lower supply current, individual I/O
configuration, and smaller packaging. I/O expanders provide a simple solution when
additional I/O is needed for ACPI power switches, sensors, push buttons, LEDs, fans, etc.
The PCA9555consists of two 8-bit Configuration (Input or Output selection); Input, Output
and Polarity Inversion (active HIGH or active LOW operation) registers. The system
master can enable the I/Os as either inputs or outputs by writing to the I/O configuration
bits. The data for each Input or Output is kept in the corresponding Input or Output
register. The polarity of the read register can be inverted with the Polarity Inversion
register. All registers can be read by the system master. Although pin-to-pin and I2C-bus
address compatible with the PCF8575, software changes are required due to the
enhancements, and are discussed in
Application Note AN469
.
2. Features
The PCA9555 open-drain interrupt output is activated when any input state differs from its
corresponding input port register state and is used to indicate to the system master that
an input state has changed. The power-on reset sets the registers to their default values
and initializes the device state machine.
Three hardware pins (A0, A1, A2) vary the fixed I2C-bus address and allow up to eight
devices to share the same I2C-bus/SMBus. The fixed I2C-bus address of the PCA9555 is
the same as the PCA9554, allowing up to eight of these devices in any combination to
share the same I2C-bus/SMBus.
n Operating power supply voltage range of 2.3 V to 5.5 V
n 5 V tolerant I/Os
n Polarity Inversion register
n Active LOW interrupt output
n Low standby current
n Noise filter on SCL/SDA inputs
n No glitch on power-up
n Internal power-on reset
n 16 I/O pins which default to 16 inputs
n 0 Hz to 400 kHz clock frequency
n ESD protection exceeds 2000 V HBM per JESD22-A114, 200 V MM per
JESD22-A115, and 1000 V CDM per JESD22-C101
NXP Semiconductors
n Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA
n Six packages offered: DIP24, SO24, SSOP24, TSSOP24, HVQFN24 and HWQFN24
3. Ordering information
Table 1. Ordering information
Type number Package
PCA9555N DIP24 plastic dual in-line package; 24 leads (600 mil) SOT101-1
PCA9555D SO24 plastic small outline package; 24 leads;
PCA9555DB SSOP24 plastic shrink small outline package; 24 leads;
PCA9555PW TSSOP24 plastic thin shrink small outline package; 24 leads;
PCA9555BS HVQFN24 plastic thermal enhanced very thin quad flat package;
PCA9555HF HWQFN24 plastic thermal enhanced very very thin quad flat
PCA9555
16-bit I2C-bus and SMBus I/O port with interrupt
Name Description Version
SOT137-1
body width 7.5 mm
SOT340-1
body width 5.3 mm
SOT355-1
body width 4.4 mm
SOT616-1
no leads; 24 terminals; body 4 × 4 × 0.85 mm
SOT994-1
package; no leads; 24 terminals; body 4 × 4 × 0.75 mm
3.1 Ordering options
Table 2. Ordering options
Type number Topside mark Temperature range
PCA9555N PCA9555 −40 °C to +85 °C
PCA9555D PCA9555D −40 °C to +85 °C
PCA9555DB PCA9555 −40 °C to +85 °C
PCA9555PW PCA9555 −40 °C to +85 °C
PCA9555BS 9555 −40 °C to +85 °C
PCA9555HF P55H −40 °C to +85 °C
PCA9555_8 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 08 — 22 October 2009 2 of 34
NXP Semiconductors
4. Block diagram
PCA9555
16-bit I2C-bus and SMBus I/O port with interrupt
PCA9555
A0
A1
A2
SCL
SDA
V
DD
V
SS
INPUT
FILTER
POWER-ON
RESET
Remark: All I/Os are set to inputs at reset.
Fig 1. Block diagram of PCA9555
I2C-BUS/SMBus
CONTROL
8-bit
write pulse
read pulse
8-bit
write pulse
read pulse
INPUT/
OUTPUT
PORTS
INPUT/
OUTPUT
PORTS
LP filter
002aac702
IO1_0
IO1_1
IO1_2
IO1_3
IO1_4
IO1_5
IO1_6
IO1_7
IO0_0
IO0_1
IO0_2
IO0_3
IO0_4
IO0_5
IO0_6
IO0_7
V
DD
INT
5. Pinning information
5.1 Pinning
INT
IO0_0
IO0_1
IO0_2
IO0_3
IO0_4
IO0_5
IO0_6
IO0_7
V
A1
A2
SS
1
2
3
4
5
6
7
8
9
10
11
12
PCA9555N
002aac697
24
V
DD
23
SDA
22
SCL
21
A0
20
IO1_7
19
IO1_6
18
IO1_5
17
IO1_4
16
IO1_3
15
IO1_2
14
IO1_1
13
IO1_0
1
INT V
2
A1 SDA
3
A2 SCL
4
IO0_0 A0
5
IO0_1 IO1_7
6
IO0_2 IO1_6
IO0_3 IO1_5
IO0_4 IO1_4
IO0_5 IO1_3
IO0_6 IO1_2
IO0_7 IO1_1
V
SS
7
8
9
10
11
12
PCA9555D
002aac698
Fig 2. Pin configuration for DIP24 Fig 3. Pin configuration for SO24
PCA9555_8 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 08 — 22 October 2009 3 of 34
24
DD
23
22
21
20
19
18
17
16
15
14
13
IO1_0
NXP Semiconductors
PCA9555
16-bit I2C-bus and SMBus I/O port with interrupt
INT
A1
A2
IO0_0
IO0_1
IO0_2
IO0_3
IO0_4
IO0_5
IO0_6
IO0_7
V
SS
1
2
3
4
5
6
7
8
9
10
11
12
PCA9555DB
002aac699
24
V
DD
23
SDA
22
SCL
21
A0
20
IO1_7
19
IO1_6
18
IO1_5
17
IO1_4
16
IO1_3
15
IO1_2
14
IO1_1
13
IO1_0
INT
A1
A2
IO0_0
IO0_1
IO0_2
IO0_3
IO0_4
IO0_5
IO0_6
IO0_7
V
SS
1
2
3
4
5
6
7
8
9
10
11
12
PCA9555PW
002aac700
24
V
DD
23
SDA
22
SCL
21
A0
20
IO1_7
19
IO1_6
18
IO1_5
17
IO1_4
16
IO1_3
15
IO1_2
14
IO1_1
13
IO1_0
Fig 4. Pin configuration for SSOP24 Fig 5. Pin configuration for TSSOP24
8
IO0_7
9
SS
V
DD
SDA
V
101112
IO1_0
IO1_1
SCL
19
18
14
13
IO1_2
IO1_4
IO1_3
002aac881
terminal 1
index area
IO0_0 A0
IO0_1 IO1_7
IO0_2 IO1_6
IO0_3 IO1_5
IO0_4
IO0_5
A2
2423222120
1
2 17
3 16
PCA9555BS
4 15
5
6
789
IO0_6
Transparent top view
A1
IO0_7
INT
SS
V
DD
SDA
V
101112
IO1_0
IO1_1
SCL
19
18
14
13
IO1_2
IO1_4
IO1_3
002aac701
terminal 1
index area
IO0_0 A0
IO0_1 IO1_7
IO0_2 IO1_6
IO0_3 IO1_5
IO0_4
IO0_5
A2A1INT
2423222120
1
2 17
3 16
PCA9555HF
4 15
5
6
7
IO0_6
Transparent top view
Fig 6. Pin configuration for HVQFN24 Fig 7. Pin configuration for HWQFN24
PCA9555_8 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 08 — 22 October 2009 4 of 34
NXP Semiconductors
5.2 Pin description
Table 3. Pin description
Symbol Pin Description
INT 1 22 interrupt output (open-drain)
A1 2 23 address input 1
A2 3 24 address input 2
IO0_0 4 1 port 0 input/output
IO0_1 5 2
IO0_2 6 3
IO0_3 7 4
IO0_4 8 5
IO0_5 9 6
IO0_6 10 7
IO0_7 11 8
V
SS
IO1_0 13 10 port 1 input/output
IO1_1 14 11
IO1_2 15 12
IO1_3 16 13
IO1_4 17 14
IO1_5 18 15
IO1_6 19 16
IO1_7 20 17
A0 21 18 address input 0
SCL 22 19 serial clock line
SDA 23 20 serial data line
V
DD
[1] HVQFN and HWQFN package die supply ground is connected to both the VSSpin and the exposed center
PCA9555
16-bit I2C-bus and SMBus I/O port with interrupt
DIP24, SO24,
SSOP24, TSSOP24
12 9
24 21 supply voltage
pad. The VSS pin must be connected to supply ground for proper device operation. For enhanced thermal,
electrical, and board-level performance, the exposed pad needs to be soldered to the board using a
corresponding thermal pad on the board, and for proper heat conduction through the board thermal vias
need to be incorporated in the PCB in the thermal pad region.
HVQFN24,
HWQFN24
[1]
supply ground
PCA9555_8 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 08 — 22 October 2009 5 of 34
NXP Semiconductors
6. Functional description
Refer to Figure 1 “Block diagram of PCA9555”.
6.1 Device address
PCA9555
16-bit I2C-bus and SMBus I/O port with interrupt
slave address
Fig 8. PCA9555 device address
6.2 Registers
6.2.1 Command byte
The command byte is the first byte to follow the address byte during a write transmission.
It is used as a pointer to determine which of the following registers will be written or read.
Table 4. Command byte
Command Register
0 Input port 0
1 Input port 1
2 Output port 0
3 Output port 1
4 Polarity Inversion port 0
5 Polarity Inversion port 1
6 Configuration port 0
7 Configuration port 1
0 1 0 0 A2 A1 A0
fixed
programmable
002aac219
R/W
PCA9555_8 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 08 — 22 October 2009 6 of 34
NXP Semiconductors
6.2.2 Registers 0 and 1: Input port registers
This register is an input-only port. It reflects the incoming logic levels of the pins,
regardless of whether the pin is defined as an input or an output by Register 3. Writes to
this register have no effect.
The default value ‘X’ is determined by the externally applied logic level.
Table 5. Input port 0 Register
Bit 7 6 5 4 3 2 1 0
Symbol I0.7 I0.6 I0.5 I0.4 I0.3 I0.2 I0.1 I0.0
Default XXXXXXXX
Table 6. Input port 1 register
Bit 7 6 5 4 3 2 1 0
Symbol I1.7 I1.6 I1.5 I1.4 I1.3 I1.2 I1.1 I1.0
Default XXXXXXXX
6.2.3 Registers 2 and 3: Output port registers
PCA9555
16-bit I2C-bus and SMBus I/O port with interrupt
This register is an output-only port. It reflects the outgoing logic levels of the pins defined
as outputs by Registers 6 and 7. Bit values in this register have no effect on pins defined
as inputs. In turn, reads from this register reflect the value that is in the flip-flop controlling
the output selection, not the actual pin value.
Table 7. Output port 0 register
Bit 7 6 5 4 3 2 1 0
Symbol O0.7 O0.6 O0.5 O0.4 O0.3 O0.2 O0.1 O0.0
Default 11111111
Table 8. Output port 1 register
Bit 7 6 5 4 3 2 1 0
Symbol O1.7 O1.6 O1.5 O1.4 O1.3 O1.2 O1.1 O1.0
Default 11111111
6.2.4 Registers 4 and 5: Polarity Inversion registers
This register allows the user to invert the polarity of the Input port register data. If a bit in
this register is set (written with ‘1’), the Input port data polarity is inverted. If a bit in this
register is cleared (written with a ‘0’), the Input port data polarity is retained.
Table 9. Polarity Inversion port 0 register
Bit 7 6 5 4 3 2 1 0
Symbol N0.7 N0.6 N0.5 N0.4 N0.3 N0.2 N0.1 N0.0
Default 00000000
Table 10. Polarity Inversion port 1 register
Bit 7 6 5 4 3 2 1 0
Symbol N1.7 N1.6 N1.5 N1.4 N1.3 N1.2 N1.1 N1.0
Default 00000000
PCA9555_8 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 08 — 22 October 2009 7 of 34
NXP Semiconductors
6.2.5 Registers 6 and 7: Configuration registers
This register configures the directions of the I/O pins. If a bit in this register is set (written
with ‘1’), the corresponding port pin is enabled as an input with high-impedance output
driver. If a bit in this register is cleared (written with ‘0’), the corresponding port pin is
enabled as an output. Note that there is a high value resistor tied to VDD at each pin. At
reset, the device's ports are inputs with a pull-up to VDD.
Table 11. Configuration port 0 register
Bit 7 6 5 4 3 2 1 0
Symbol C0.7 C0.6 C0.5 C0.4 C0.3 C0.2 C0.1 C0.0
Default 11111111
Table 12. Configuration port 1 register
Bit 7 6 5 4 3 2 1 0
Symbol C1.7 C1.6 C1.5 C1.4 C1.3 C1.2 C1.1 C1.0
Default 11111111
PCA9555
16-bit I2C-bus and SMBus I/O port with interrupt
6.3 Power-on reset
When power is applied to VDD, an internal power-on reset holds the PCA9555 in a reset
condition until VDDhas reached V
. At that point, the reset condition is released and the
POR
PCA9555 registers and SMBus state machine will initialize to their default states. The
power-on reset typically completes the reset and enables the part by the time the power
supply is above V
. However, when it is required to reset the part by lowering the power
POR
supply, it is necessary to lower it below 0.2 V.
6.4 I/O port
When an I/O is configured as an input, FETs Q1 and Q2 are off, creating a
high-impedance input with a weak pull-up to VDD. The input voltage may be raised above
VDD to a maximum of 5.5 V.
If the I/O is configured as an output, then either Q1 or Q2 is on, depending on the state of
the Output Port register. Care should be exercised if an external voltage is applied to an
I/O configured as an output because of the low-impedance path that exists between the
pin and either VDD or VSS.
PCA9555_8 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 08 — 22 October 2009 8 of 34
NXP Semiconductors
PCA9555
16-bit I2C-bus and SMBus I/O port with interrupt
data from
shift register
data from
shift register
configuration
write pulse
read pulse
data from
shift register
write polarity
write
pulse
pulse
configuration
register
DQ
FF
CK Q
DQ
FF
CK
output port
register
At power-on reset, all registers return to default values.
Fig 9. Simplified schematic of I/Os
input port
register
DQ
FF
CK
polarity inversion
register
DQ
FF
CK
Q1
100 kΩ
Q2
output port
register data
V
DD
I/O pin
V
SS
input port
register data
to INT
polarity
inversion
register data
002aac703
6.5 Bus transactions
6.5.1 Writing to the port registers
Data is transmitted to the PCA9555 by sending the device address and setting the least
significant bit to a logic 0 (see Figure 8 “PCA9555 device address”). The command byte is
sent after the address and determines which register will receive the data following the
command byte.
The eight registers within the PCA9555 are configured to operate as four register pairs.
The four pairs are Input Ports, Output Ports, Polarity Inversion Ports, and Configuration
Ports. After sending data to one register, the next data byte will be sent to the other
register in the pair (see Figure 10 and Figure 11). For example, if the first byte is sent to
Output Port 1 (register 3), then the next byte will be stored in Output Port 0 (register 2).
There is no limitation on the number of data bytes sent in one write transmission. In this
way, each 8-bit register may be updated independently of the other registers.
PCA9555_8 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 08 — 22 October 2009 9 of 34
PCA9555_8 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 08 — 22 October 2009 10 of 34
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx
xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx
xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
NXP Semiconductors
SCL
slave address
SDA A
write to port
data out
from port 0
data out
from port 1
1 0 0 A2 A1 A0 0 AS0
START condition R/W acknowledge
Fig 10. Write to Output port registers
SCL
slave address
SDA A P
1 0 0 A2 A1 A0 0 AS0
987654321
987654321
from slave
00001100
command byte
00000100
command byte
A
acknowledge
from slave
A
data to port 0
DATA 0
data to register
DATA 0
t
v(Q)
LSBMSB
0.00.7
acknowledge
from slave
data to register
data to port 1
DATA 1 1.01.7
DATA VALID
DATA 1
t
LSBMSB
v(Q)
A
P
A
STOP
condition
002aac220
16-bit I
2
C-bus and SMBus I/O port with interrupt
START condition R/W acknowledge
Fig 11. Write to Configuration registers
from slave
acknowledge
from slave
acknowledge
from slave
STOP
condition
002aac221
PCA9555
NXP Semiconductors
6.5.2 Reading the port registers
In order to read data from the PCA9555, the bus master must first send the PCA9555
address with the least significant bit set to a logic 0 (see Figure 8 “PCA9555 device
address”). The command byte is sent after the address and determines which register will
be accessed. After a restart, the device address is sent again, but this time the least
significant bit is set to a logic 1. Data from the register defined by the command byte will
then be sent by the PCA9555 (see Figure 12, Figure 13 and Figure 14). Data is clocked
into the register on the falling edge of the acknowledge clock pulse. After the first byte is
read, additional bytes may be read but the data will now reflect the information in the other
register in the pair. For example, if you read Input Port 1, then the next byte read would be
Input Port 0. There is no limitation on the number of data bytes received in one read
transmission but the final byte received, the bus master must not acknowledge the data.
slave address
SDA
1 0 0 A2 A1 A00 0
PCA9555
16-bit I2C-bus and SMBus I/O port with interrupt
AS
COMMAND BYTE
(cont.)
A
START condition R/W
slave address
(cont.)
S
1 0 0 A2 A1 A0 1 A0
(repeated)
START condition
Remark: Transfer can be stopped at any time by a STOP condition.
Fig 12. Read from register
acknowledge
from slave
R/W
acknowledge
from slave
acknowledge
from slave
data from lower or
upper byte of register
LSBMSB
DATA (first byte)
at this moment master-transmitter becomes master-receiver
and slave-receiver becomes slave-transmitter
A P
acknowledge
from master
data from upper or
lower byte of register
DATA (last byte)
no acknowledge
LSBMSB
from master
NA
STOP
condition
002aac222
PCA9555_8 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 08 — 22 October 2009 11 of 34
Loading...