NXP PCA 9554 D Datasheet

PCA9554/PCA9554A

8-bit I2C-bus and SMBus I/O port with interrupt

Rev. 07 — 13 November 2006 Product data sheet

1. General description

The PCA9554 and PCA9554A are 16-pin CMOS devices that provide 8 bits of General Purpose parallel Input/Output (GPIO) expansion for I2C-bus/SMBus applications and were developed to enhance the NXP Semiconductors family of I2C-bus I/O expanders. The improvements include higher drive capability, 5 V I/O tolerance, lower supply current, individual I/O conﬁguration, 400 kHz clock frequency, and smaller packaging. I/O expanders provide a simple solution when additional I/O is needed for ACPI power switches, sensors, push buttons, LEDs, fans, etc.

The PCA9554/PCA9554A consist of an 8-bit Conﬁguration register (Input or Output selection); 8-bit Input Port register, 8-bit Output Port register and an 8-bit Polarity Inversion register (active HIGH or active LOW operation). The system master can enable the I/Os as either inputs or outputs by writing to the I/O conﬁguration bits. The data for each input or output is kept in the corresponding Input Port or Output Port register. The polarity of the read register can be inverted with the Polarity Inversion register. All registers can be read by the system master. Although pin-to-pin and I2C-bus address compatible with the PCF8574 series, software changes are required due to the enhancements and are discussed in

Application Note AN469

2. Features

The PCA9554/PCA9554A open-drain interrupt output is activated when any input state differs from its corresponding Input Port register state and is used to indicate to the system master that an input state has changed. The power-on reset sets the registers to their default values and initializes the device state machine.

Three hardware pins (A0, A1, A2) vary the ﬁxed I2C-bus address and allow up to eight devices to share the same I2C-bus/SMBus. The PCA9554A is identical to the PCA9554 except that the ﬁxed I2C-bus address is different allowing up to sixteen of these devices (eight of each) on the same I2C-bus/SMBus.

n Operating power supply voltage range of 2.3 V to 5.5 V n 5 V tolerant I/Os n Polarity Inversion register n Active LOW interrupt output n Low standby current n Noise ﬁlter on SCL/SDA inputs n No glitch on power-up n Internal power-on reset n 8 I/O pins which default to 8 inputs n 0 Hz to 400 kHz clock frequency

NXP Semiconductors

PCA9554/PCA9554A

8-bit I2C-bus and SMBus I/O port with interrupt

n ESD protection exceeds 2000 V HBM per JESD22-A114, 200 V MM per

JESD22-A115 and 1000 V CDM per JESD22-C101

n Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA n Packages offered: DIP16, SO16, SSOP16, SSOP20, TSSOP16,

HVQFN16 (2 versions: 4 × 4 × 0.85 mm and 3 × 3 × 0.85 mm), and bare die

3. Ordering information

Table 1. Ordering information

=−40°C to +85°C.

amb

Type number Topside mark Package

Name Description Version

PCA9554N PCA9554N DIP16 plastic dual in-line package; 16 leads (300 mil); PCA9554AN PCA9554AN PCA9554D PCA9554D SO16 plastic small outline package; 16 leads; PCA9554AD PCA9554AD PCA9554DB 9554DB SSOP16 plastic shrink small outline package; 16 leads; PCA9554ADB 9554A PCA9554TS PCA9554 SSOP20 plastic shrink small outline package; 20 leads; PCA9554ATS PA9554A PCA9554PW 9554DH TSSOP16 plastic thin shrink small outline package; 16 leads; PCA9554APW 9554ADH PCA9554BS 9554 HVQFN16 plastic thermal enhanced very thin quad ﬂat package; PCA9554ABS 554A PCA9554BS3 P54 HVQFN16 plastic thermal enhanced very thin quad ﬂat package; PCA9554ABS3 54A PCA9554U - bare die - -

long body

body width 7.5 mm

body width 5.3 mm

body width 4.4 mm

no leads; 16 terminals; body 4 × 4 × 0.85 mm

no leads; 16 terminals; body 3 × 3 × 0.85 mm

SOT38-1

SOT162-1

SOT338-1

SOT266-1

SOT403-1

SOT629-1

SOT758-1

Product data sheet Rev. 07 — 13 November 2006 2 of 30

NXP Semiconductors

4. Block diagram

PCA9554/PCA9554A

8-bit I2C-bus and SMBus I/O port with interrupt

A0 A1 A2

SCL SDA

INPUT

FILTER

POWER-ON

RESET

I2C-BUS/SMBus

CONTROL

All I/Os are set to inputs at reset.

Fig 1. Block diagram of PCA9554/PCA9554A

PCA9554/PCA9554A

8-bit

write pulse

read pulse

INPUT/

OUTPUT

PORTS

FILTER

002aac492

IO0 IO1 IO2 IO3 IO4 IO5 IO6 IO7

INT

Product data sheet Rev. 07 — 13 November 2006 3 of 30

NXP Semiconductors

5. Pinning information

5.1 Pinning

PCA9554/PCA9554A

8-bit I2C-bus and SMBus I/O port with interrupt

PCA9554N

PCA9554AN

A0 V

A1 SDA

A2 SCL

IO0 INT

IO1 IO7

IO2 IO6

IO3 IO5

002aac485

IO4

A0 A1

A2 IO0 IO1 IO2 IO3

1 2 3 4 5 6 7 8

PCA9554D

PCA9554AD

002aac486

16 15 14 13 12 11 10

Fig 2. Pin conﬁguration for DIP16 Fig 3. Pin conﬁguration for SO16

IO0 IO1 IO2 IO3

A0 A1 A2

1 2 3 4 5 6 7 8

PCA9554DB

PCA9554ADB

002aac487

SDA

SCL

INT

IO7

IO6

IO5 IO4

IO0 IO1 IO2 IO3

A0 A1 A2

1 2 3 4 5 6 7 8

PCA9554PW

PCA9554APW

002aac488

16 15 14 13 12 11 10

SDA SCL INT IO7 IO6 IO5 IO4

Fig 4. Pin conﬁguration for SSOP16 Fig 5. Pin conﬁguration for TSSOP16

Product data sheet Rev. 07 — 13 November 2006 4 of 30

NXP Semiconductors

PCA9554/PCA9554A

8-bit I2C-bus and SMBus I/O port with interrupt

INT IO7

SCL IO6

n.c. n.c.

SDA IO5

A0 V

A1 IO3

n.c. n.c.

A2 IO2

IO0 IO1

Fig 6. Pin conﬁguration for SSOP20

PCA9554BS

PCA9554ABS

terminal 1

index area

A2 SCL IO0 INT IO1 IO7 IO2

A1 16

1 12 2 11 3 10 4 9

A0 15

SDA

V 14

PCA9554TS

PCA9554ATS

IO6

20 19 18 17 16

IO4

14 13 12 11

002aac489

PCA9554BS3

PCA9554ABS3

terminal 1

index area

A2 SCL IO0 IO1 IO7 IO2 IO6

1 12 2 11 3 10 4 9

SDA

V 14

INT

IO3

Transparent top view

IO4

IO5

002aac490

Fig 7. Pin conﬁguration for HVQFN16

(SOT629-1)

IO3

Transparent top view

IO4

IO5

002aac491

Fig 8. Pin conﬁguration for HVQFN16

(SOT758-1)

Product data sheet Rev. 07 — 13 November 2006 5 of 30

NXP Semiconductors

5.2 Pin description

Table 2. Pin description

Symbol Pin Description

A0 1 15 6 address input 0 A1 2 16 7 address input 1 A2 3 1 9 address input 2 IO0 4 2 10 input/output 0 IO1 5 3 11 input/output 1 IO2 6 4 12 input/output 2 IO3 7 5 14 input/output 3 V

IO4 9 7 16 input/output 4 IO5 10 8 17 input/output 5 IO6 11 9 19 input/output 6 IO7 12 10 20 input/output 7 INT 13 11 1 interrupt output (open-drain) SCL 14 12 2 serial clock line SDA 15 13 4 serial data line V

n.c. - - 3, 8, 13, 18 not connected

PCA9554/PCA9554A

8-bit I2C-bus and SMBus I/O port with interrupt

DIP16, SO16, SSOP16, TSSOP16

16 14 5 supply voltage

HVQFN16 SSOP20

[1]

15 supply ground

[1] HVQFN package die supply groundis connected to both VSSpin and exposed center pad. VSSpin must be

connected to supply ground for proper device operation. For enhanced thermal, electrical, and board level performance, the exposed pad needs to be soldered to the board using a corresponding thermal pad on the board and forproper heat conduction through the board, thermal vias need to be incorporated in the PCB in the thermal pad region.

6. Functional description

Refer to Figure 1 “Block diagram of PCA9554/PCA9554A”.

6.1 Registers

6.1.1 Command byte

Table 3. Command byte

Command Protocol Function

0 read byte Input Port register 1 read/write byte Output Port register 2 read/write byte Polarity Inversion register 3 read/write byte Conﬁguration register

The command byte is the ﬁrst byte to follow the address byte during a write transmission. It is used as a pointer to determine which of the following registers will be written or read.

Product data sheet Rev. 07 — 13 November 2006 6 of 30

NXP Semiconductors

6.1.2 Register 0 - Input Port register

This register is a read-only port. It reﬂects the incoming logic levels of the pins, regardless of whether the pin is deﬁned as an input or an output by Register 3. Writes to this register have no effect.

The default ‘X’ is determined by the externally applied logic level, normally ‘1’ when no external signal externally applied because of the internal pull-up resistors.

Table 4. Register 0 - Input Port register bit description

Bit Symbol Access Value Description

7 I7 read only X determined by externally applied logic level 6 I6 read only X 5 I5 read only X 4 I4 read only X 3 I3 read only X 2 I2 read only X 1 I1 read only X 0 I0 read only X

PCA9554/PCA9554A

8-bit I2C-bus and SMBus I/O port with interrupt

6.1.3 Register 1 - Output Port register

This register reﬂects the outgoing logic levels of the pins deﬁned as outputs by Register 3. Bit values in this register have no effect on pins deﬁned as inputs. Reads from this register return the value that is in the ﬂip-ﬂop controlling the output selection, not the actual pin value.

Table 5. Register 1 - Output Port register bit description

Legend: * default value.

Bit Symbol Access Value Description

7 O7 R 1* reﬂects outgoing logic levels of pins deﬁned as 6O6 R 1* 5O5 R 1* 4O4 R 1* 3O3 R 1* 2O2 R 1* 1O1 R 1* 0O0 R 1*

outputs by Register 3

Product data sheet Rev. 07 — 13 November 2006 7 of 30

NXP Semiconductors

6.1.4 Register 2 - Polarity Inversion register

This register allows the user to invert the polarity of the Input Port register data. If a bit in this register is set (written with ‘1’), the corresponding Input Port data is inverted. If a bit in this register is cleared (written with a ‘0’), the Input Port data polarity is retained.

Table 6. Register 2 - Polarity Inversion register bit description

Legend: * default value.

Bit Symbol Access Value Description

7 N7 R/W 0* inverts polarity of Input Port register data 6 N6 R/W 0* 5 N5 R/W 0* 4 N4 R/W 0* 3 N3 R/W 0* 2 N2 R/W 0* 1 N1 R/W 0* 0 N0 R/W 0*

PCA9554/PCA9554A

8-bit I2C-bus and SMBus I/O port with interrupt

0 = Input Port register data retained (default value) 1 = Input Port register data inverted

6.1.5 Register 3 - Conﬁguration register

This register conﬁgures the directions of the I/O pins. If a bit in this register is set, the corresponding port pin is enabled as an input with high-impedance output driver.If a bit in this register is cleared, the corresponding port pin is enabled as an output. At reset, the I/Os are conﬁgured as inputs with a weak pull-up to VDD.

Table 7. Register 3 - Conﬁguration register bit description

Legend: * default value.

Bit Symbol Access Value Description

7 C7 R/W 1* conﬁgures the directions of the I/O pins 6 C6 R/W 1* 5 C5 R/W 1* 4 C4 R/W 1* 3 C3 R/W 1* 2 C2 R/W 1* 1 C1 R/W 1* 0 C0 R/W 1*

6.2 Power-on reset

When power is applied to VDD, an internal Power-On Reset (POR) holds the PCA9554/PCA9554A in a reset condition until VDD has reached V reset condition is released and the PCA9554/PCA9554A registers and state machine will initialize to their default states. Thereafter, VDD must be lowered below 0.2 V to reset the device.

0 = corresponding port pin enabled as an output 1 = corresponding port pin conﬁgured as input

(default value)

. At that point, the

POR

For a power reset cycle, VDD must be lowered below 0.2 V and then restored to the operating voltage.

Product data sheet Rev. 07 — 13 November 2006 8 of 30

NXP Semiconductors

6.3 Interrupt output

The open-drain interrupt output is activated when one of the port pins change state and the pin is conﬁgured as an input. The interrupt is deactivated when the input returns to its previous state or the Input Port register is read.

Note that changing an I/O from and output to an input may cause a false interrupt to occur if the state of the pin does not match the contents of the Input Port register.

6.4 I/O port

When an I/O is conﬁgured as an input, FETs Q1 and Q2 are off, creating a high-impedance input with a weak pull-up (100 kΩ typ.) to VDD. The input voltage may be raised above VDD to a maximum of 5.5 V.

If the I/O is conﬁgured as an output, then either Q1 or Q2 is enabled, depending on the state of the Output Port register. Care should be exercised if an external voltage is applied to an I/O conﬁgured as an output because of the low-impedance paths that exist between the pin and either VDD or VSS.

PCA9554/PCA9554A

8-bit I2C-bus and SMBus I/O port with interrupt

data from

shift register

data from

shift register

write configuration

pulse

write pulse

read pulse

data from

shift register

write polarity

pulse

configuration register

CK Q

output port register

input port register

polarity inversion register

100 kΩ

output port register data

IO0 to IO7

input port register data

to INT

polarity inversion register data

002aac493

Remark: At power-on reset, all registers return to default values.

Fig 9. Simpliﬁed schematic of IO0 to IO7

Product data sheet Rev. 07 — 13 November 2006 9 of 30

NXP Semiconductors

6.5 Device address

PCA9554/PCA9554A

8-bit I2C-bus and SMBus I/O port with interrupt

slave address

0 1 0 0 A2 A1 A0 R/W

fixed

hardware

selectable

002aac494

0 1 1 1 A2 A1 A0 R/W

slave address

fixed

Fig 10. PCA9554 device address Fig 11. PCA9554A device address

6.6 Bus transactions

Data is transmitted to the PCA9554/PCA9554A registers using the Write mode as shown in Figure 12 and Figure 13. Data is read from the PCA9554/PCA9554A registers using the Read mode as shown in Figure 14 and Figure 15. These devices do not implement an auto-increment function, so once a command byte has been sent, the register which was addressed will continue to be accessed by reads until a new command byte has been sent.

SCL

slave address

SDA A

write to port

data out

from port

1 0 0 A2 A1 A0 0 AS0

START condition R/W

acknowledge

from slave

987654321

command byte

00000010

acknowledge

from slave

data to port

DATA 1

programmable

acknowledge

from slave

v(Q)

002aac495

STOP condition

data 1 valid

002aac472

Fig 12. Write to Output Port register

SCL

slave address

SDA A

data to

1 0 0 A2 A1 A0 0 AS0

START condition R/W

acknowledge

from slave

987654321

command byte

0000011/00

acknowledge

from slave

data to register

DATA

acknowledge

from slave

STOP condition

002aac473

Fig 13. Write to Conﬁguration register or Polarity Inversion register

Product data sheet Rev. 07 — 13 November 2006 10 of 30

NXP Semiconductors

slave address

SDA

1 0 0 A2 A1 A0 0 AS0

command byte

PCA9554/PCA9554A

8-bit I2C-bus and SMBus I/O port with interrupt

(cont.)

START condition R/W

slave address

(cont.)

1 0 0 A2 A1 A0 1 A0

(repeated) START condition

Fig 14. Read from register

SCL

slave address

SDA NA

read from

port

data into

port

INT

1 0 0 A2 A1 A0 1 AS0

START condition R/W

v(INT_N)

acknowledge

from slave

R/W

acknowledge

from slave

acknowledge

from slave

h(D)

acknowledge

from slave

data from register

DATA (first byte)

acknowledge

from master

at this moment master-transmitter becomes master-receiver and slave-receiver becomes slave-transmitter

987654321

data from port

DATA 1

DATA 2 DATA 3 DATA 4

rst(INT_N)

A P

acknowledge

from master

su(D)

data from register

DATA (last byte)

data from port

DATA 4

no acknowledge

from master

no acknowledge

from master

002aac474

002aac475

STOP condition

This ﬁgure assumes the command byte has previously been programmed with 00h. Transfer of data can be stopped at any moment by a STOP condition.

Fig 15. Read Input Port register

Product data sheet Rev. 07 — 13 November 2006 11 of 30

NXP Semiconductors

7. Application design-in information

VDD (5 V)

10 kΩ 10 kΩ

10 kΩ10 kΩ

MASTER

CONTROLLER

SCL

SDA

SCL SDA

INTINT

A2 A1 A0

PCA9554/PCA9554A

8-bit I2C-bus and SMBus I/O port with interrupt

2 kΩ

PCA9554

IO0 IO1

IO2 IO3 IO4 IO5 IO6 IO7

enable

SUBSYSTEM 1

(e.g., temp. sensor)

INT

RESET

SUBSYSTEM 2

(e.g., counter)

controlled switch (e.g., CBT device)

ALARM

SUBSYSTEM 3

(e.g., alarm system)

Device address conﬁgured as 0100 100X for this example. IO0, IO1, IO2 conﬁgured as outputs. IO3, IO4, IO5 conﬁgured as inputs. IO6 and IO7 are not used and must be conﬁgured as outputs.

Fig 16. Typical application

8. Limiting values

Table 8. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol Parameter Conditions Min Max Unit

I/O

O(IOn)

tot

stg

amb

002aac496

supply voltage −0.5 +6.0 V input current - ±20 mA voltage on an input/output pin VSS− 0.5 5.5 V output current on pin IOn - ±50 mA supply current - 85 mA ground supply current - 100 mA total power dissipation - 200 mW storage temperature −65 +150 °C ambient temperature operating −40 +85 °C

Product data sheet Rev. 07 — 13 November 2006 12 of 30

NXP Semiconductors

PCA9554/PCA9554A

8-bit I2C-bus and SMBus I/O port with interrupt

9. Static characteristics

Table 9. Static characteristics

VDD= 2.3 V to 5.5 V; VSS=0V; T

Symbol Parameter Conditions Min Typ Max Unit

Supplies

V I

stb

POR

supply voltage 2.3 - 5.5 V supply current operating mode; VDD= 5.5 V;

standby current Standby mode; VDD= 5.5 V; no load;

power-on reset voltage no load; VI=VDD or V

Input SCL; input/output SDA

LOW-level input voltage −0.5 - +0.3V HIGH-level input voltage 0.7V LOW-level output current VOL= 0.4 V 3 6 - mA leakage current VI=VDD=V input capacitance VI=V

I/Os

Interrupt

LOW-level input voltage −0.5 - +0.8 V HIGH-level input voltage 2.0 - 5.5 V LOW-level output current VOL= 0.5 V; VDD= 2.3 V

HIGH-level output voltage IOH= −8 mA; VDD= 2.3 V

input leakage current VDD= 3.6 V; VI=V input leakage current VDD= 5.5 V; VI=V input capacitance - 3.7 5 pF output capacitance - 3.7 5 pF

INT

LOW-level output current VOL= 0.4 V 3 - - mA

=−40°C to +85°C; unless otherwise speciﬁed.

amb

no load; f

I=VSS

Standby mode; V V

I=VDD

= 0.7 V; VDD= 2.3 V

= 0.5 V; VDD= 3.0 V

= 0.7 V; VDD= 3.0 V

= 0.5 V; VDD= 4.5 V

= 0.7 V; VDD= 4.5 V

= −10 mA; VDD= 2.3 V

= −8 mA; VDD= 3.0 V

= −10 mA; VDD= 3.0 V

= −8 mA; VDD= 4.75 V

= −10 mA; VDD= 4.75 V

= 100 kHz

SCL

; f

= 0 kHz; I/O = inputs

SCL

= 5.5 V; no load;

; f

= 0 kHz; I/O = inputs

SCL

DD SS

- 104 175 µA

- 550 700 µA

- 0.25 1 µA

[1]

- 1.5 1.65 V

- 5.5 V

−1- +1 µA

- 6 10 pF

[2]

810- mA

[2]

10 13 - mA

[2]

814- mA

[2]

10 19 - mA

[2]

817- mA

[2]

10 24 - mA

[3]

1.8 - - V

[3]

1.7 - - V

[3]

2.6 - - V

[3]

2.5 - - V

[3]

4.1 - - V

[3]

4.0 - - V

--1 µA

--−100 µA

Product data sheet Rev. 07 — 13 November 2006 13 of 30

NXP Semiconductors

PCA9554/PCA9554A

8-bit I2C-bus and SMBus I/O port with interrupt

Table 9. Static characteristics

VDD= 2.3 V to 5.5 V; VSS=0V; T

…continued

=−40°C to +85°C; unless otherwise speciﬁed.

amb

Symbol Parameter Conditions Min Typ Max Unit

Select inputs A0, A1, A2

[1] VDD must be lowered to 0.2 V in order to reset part. [2] Each I/O must be externally limited to a maximum of 25 mA and the device must be limited to a maximum current of 100 mA. [3] The total current sourced by all I/Os must be limited to 85 mA.

LOW-level input voltage −0.5 - 0.8 V HIGH-level input voltage 2.0 - 5.5 V input leakage current −1- 1 µA

10. Dynamic characteristics

Table 10. Dynamic characteristics

Symbol Parameter Conditions Standard-mode

C-bus

Min Max Min Max

SCL

BUF

SCL clock frequency 0 100 0 400 kHz bus free time between a STOP and

4.7 - 1.3 - µs

START condition

HD;STA

SU;STA

hold time (repeated) START condition 4.0 - 0.6 - µs set-up time for a repeated START

4.7 - 0.6 - µs

condition

SU;STO

HD;DAT

VD:ACK

VD;DAT

SU;DAT

LOW

HIGH

set-up time for STOP condition 4.0 - 0.6 - µs data hold time 0 - 0 - µs data valid acknowledge time data valid time

[1]

0.3 3.45 0.1 0.9 µs

[2]

300 - 50 - ns data set-up time 250 - 100 - ns LOW period of the SCL clock 4.7 - 1.3 - µs HIGH period of the SCL clock 4.0 - 0.6 - µs rise time of both SDA and SCL signals - 1000 20 + 0.1C fall time of both SDA and SCL signals - 300 20 + 0.1C pulse width of spikes that must be

- 50 - 50 ns

suppressed by the input ﬁlter

Port timing

v(Q)

su(D)

h(D)

data output valid time - 200 - 200 ns data input setup time 100 - 100 - ns data input hold time 1 - 1 - µs

Interrupt timing

v(INT_N)

rst(INT_N)

valid time on pin INT - 4 - 4 µs reset time on pin INT - 4 - 4 µs

Fast-mode I2C-bus Unit

[3]

300 ns

[3]

300 µs

[1] t [2] t [3] Cb= total capacitance of one bus line in pF.

Product data sheet Rev. 07 — 13 November 2006 14 of 30

= time for Acknowledgement signal from SCL LOW to SDA (out) LOW.

VD;ACK

= minimum time for SDA data output to be valid following SCL LOW.

VD;DAT

NXP Semiconductors

SDA

PCA9554/PCA9554A

8-bit I2C-bus and SMBus I/O port with interrupt

BUF

SCL

Fig 17. Deﬁnition of timing

LOW

HD;STA

HD;DAT

HIGH

SU;DAT

HD;STA

SU;STA

SU;STO

PP S

002aaa986

Product data sheet Rev. 07 — 13 November 2006 15 of 30

NXP Semiconductors

11. Package outline

PCA9554/PCA9554A

8-bit I2C-bus and SMBus I/O port with interrupt

DIP16: plastic dual in-line package; 16 leads (300 mil); long body

seating plane

pin 1 index

w M

SOT38-1

(e )

0 5 10 mm

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

UNIT

inches

Note

1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.

OUTLINE

VERSION

SOT38-1

max.

4.7 0.51 3.7

1 2

min.

max.

1.40

1.14

0.055

0.15

0.045

IEC JEDEC JEITA

050G09 MO-001 SC-503-16

0.53

0.38

0.021

0.015

cEe M

0.32

0.23

0.013

0.009

REFERENCES

21.8

21.4

0.86

0.84

scale

(1) (1)

6.48

6.20

0.26

0.24

0.3

0.15

0.13

3.9

3.4

EUROPEAN

PROJECTION

8.25

7.80

0.32

0.31

9.5

8.3

0.37

0.33

max.

0.2542.54 7.62

0.087

0.010.10.020.19

ISSUE DATE

99-12-27 03-02-13

2.2

(1)

Fig 18. Package outline SOT38-1 (DIP16)

Product data sheet Rev. 07 — 13 November 2006 16 of 30

NXP Semiconductors

PCA9554/PCA9554A

8-bit I2C-bus and SMBus I/O port with interrupt

SO16: plastic small outline package; 16 leads; body width 7.5 mm

pin 1 index

w M

SOT162-1

detail X

(A )

v M

0 5 10 mm

scale

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

UNIT

max.

2.65

inches

Note

1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.

0.1

OUTLINE VERSION

SOT162-1

0.3

0.1

0.012

0.004

A2A3b

2.45

0.25

2.25

0.096

0.01

0.089

IEC JEDEC JEITA

075E03 MS-013

0.49

0.36

0.019

0.014

0.32

0.23

0.013

0.009

(1)E(1) (1)

10.5

10.1

0.41

0.40

REFERENCES

eHELLpQ

7.6

7.4

0.30

0.29

1.27

0.05

10.65

10.00

0.419

0.394

1.4

0.055

1.1

0.4

0.043

0.016

1.1

1.0

0.043

0.039

0.25

0.25 0.1

0.01

EUROPEAN

PROJECTION

ywv θ

0.9

0.4

0.035

0.004

0.016

ISSUE DATE

99-12-27 03-02-19

Fig 19. Package outline SOT162-1 (SO16)

Product data sheet Rev. 07 — 13 November 2006 17 of 30

NXP Semiconductors

PCA9554/PCA9554A

8-bit I2C-bus and SMBus I/O port with interrupt

SSOP16: plastic shrink small outline package; 16 leads; body width 5.3 mm

pin 1 index

SOT338-1

v M

(A )

DIMENSIONS (mm are the original dimensions)

OUTLINE

VERSION

SOT338-1

max.

0.21

0.05

1.80

1.65

IEC JEDEC JEITA

0.25

0.38

0.25

UNIT A1A2A3b

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

0.20

0.09

REFERENCES

MO-150

w M

0 2.5 5 mm

scale

(1)E(1)

6.4

6.0

eHELLpQZywv θ

5.4

5.2

7.9

0.65 1.25

7.6

1.03

0.63

detail X

0.9

0.7

0.130.2 0.1

EUROPEAN

PROJECTION

(1)

1.00

0.55

ISSUE DATE

99-12-27 03-02-19

Fig 20. Package outline SOT338-1 (SSOP16)

Product data sheet Rev. 07 — 13 November 2006 18 of 30

NXP Semiconductors

PCA9554/PCA9554A

8-bit I2C-bus and SMBus I/O port with interrupt

SSOP20: plastic shrink small outline package; 20 leads; body width 4.4 mm

pin 1 index

110

w M

detail X

SOT266-1

v M

(A )

0 2.5 5 mm

scale

DIMENSIONS (mm are the original dimensions)

UNIT A1A2A3b

Note

1. Plastic or metal protrusions of 0.20 mm maximum per side are not included.

max.

1.5

0.1501.4

1.2

0.25

IEC JEDEC JEITA

OUTLINE

VERSION

SOT266-1 MO-152

0.32

0.20

6.6

0.13

6.4

REFERENCES

(1)E(1)

4.5

4.3

eHELLpQZywv θ

0.65 1 0.2

6.6

6.2

0.75

0.45

0.65

0.45

PROJECTION

0.13 0.1

EUROPEAN

(1)

0.48

0.18

ISSUE DATE

99-12-27 03-02-19

Fig 21. Package outline SOT266-1 (SSOP20)

Product data sheet Rev. 07 — 13 November 2006 19 of 30

NXP Semiconductors

PCA9554/PCA9554A

8-bit I2C-bus and SMBus I/O port with interrupt

TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm

pin 1 index

w M

detail X

SOT403-1

v M

(A )

0 2.5 5 mm

scale

DIMENSIONS (mm are the original dimensions)

UNIT A1A2A3b

Notes

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.

max.

0.15

1.1

OUTLINE

VERSION

SOT403-1 MO-153

0.05

0.95

0.25

0.80

IEC JEDEC JEITA

0.30

0.19

(1)E(2) (1)

0.2

5.1

0.1

4.9

REFERENCES

eHELLpQZywv θ

4.5

4.3

0.65

6.6

6.2

0.75

0.50

0.4

0.3

EUROPEAN

PROJECTION

0.13 0.10.21

0.40

0.06

ISSUE DATE

99-12-27 03-02-18

Fig 22. Package outline SOT403-1 (TSSOP16)

Product data sheet Rev. 07 — 13 November 2006 20 of 30

NXP Semiconductors

PCA9554/PCA9554A

8-bit I2C-bus and SMBus I/O port with interrupt

HVQFN16: plastic thermal enhanced very thin quad flat package; no leads; 16 terminals; body 4 x 4 x 0.85 mm

terminal 1 index area

SOT629-1

detail X

1/2 e

terminal 1 index area

DIMENSIONS (mm are the original dimensions)

Note

1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.

(1)

UNIT

OUTLINE

VERSION

SOT629-1 MO-220 - - -- - -

max.

0.05

0.00

0.38

0.23

0.2

IEC JEDEC JEITA

0 2.5 5 mm

(1)

4.1

2.25

3.9

1.95

4.1

3.9

(1)

2.25

0.651

1.95

REFERENCES

scale

1/2 e

1.95

ISSUE DATE

01-08-08 02-10-22

0.75

0.50

0.1v0.05

0.05 0.1

EUROPEAN

PROJECTION

ACCB

1.95

Fig 23. Package outline SOT629-1 (HVQFN16)

Product data sheet Rev. 07 — 13 November 2006 21 of 30

NXP Semiconductors

PCA9554/PCA9554A

8-bit I2C-bus and SMBus I/O port with interrupt

HVQFN16: plastic thermal enhanced very thin quad flat package; no leads; 16 terminals; body 3 x 3 x 0.85 mm

terminal 1 index area

SOT758-1

1/2 e

terminal 1 index area

DIMENSIONS (mm are the original dimensions)

(1)

UNIT

Note

1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.

OUTLINE VERSION

SOT758-1 MO-220 - - -- - -

max.

0.05

0.00

0.30

0.18

16 13

0.2

IEC JEDEC JEITA

0 2.5 5 mm

(1)

3.1

1.75

2.9

1.45

3.1

2.9

(1)

REFERENCES

1.75

1.45

1/2 e

scale

0.51

1.5

ACCB

detail X

1.5

0.5

0.1v0.05

0.3

0.05 0.1

EUROPEAN

PROJECTION

ISSUE DATE

02-03-25 02-10-21

Fig 24. Package outline SOT758-1 (HVQFN16)

Product data sheet Rev. 07 — 13 November 2006 22 of 30

NXP Semiconductors

12. Handling information

Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be completely safe you must take normal precautions appropriate to handling integrated circuits.

13. Soldering

13.1 Introduction

There is no soldering method that is ideal for all surface mount IC packages. Wave soldering can still be used for certain surface mount ICs, but it is not suitable for ﬁne pitch SMDs. In these situations reﬂow soldering is recommended.

13.2 Through-hole mount packages

13.2.1 Soldering by dipping or by solder wave

Typical dwell time of the leads in the wave ranges from 3 seconds to 4 seconds at 250 °C or 265 °C, depending on solder material applied, SnPb or Pb-free respectively.

PCA9554/PCA9554A

8-bit I2C-bus and SMBus I/O port with interrupt

The total contact time of successive solder waves must not exceed 5 seconds. The device may be mounted up to the seating plane, but the temperature of the plastic

body must not exceed the speciﬁed maximum storage temperature (T printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit.

13.2.2 Manual soldering

Apply the soldering iron (24 V or less) to the lead(s) of the package, either below the seating plane or not more than 2 mm aboveit. If the temperature of the soldering iron bit is less than 300 °C it may remain in contact for up to 10 seconds. If the bit temperature is between 300 °C and 400 °C, contact may be up to 5 seconds.

13.3 Surface mount packages

13.3.1 Reﬂow soldering

Key characteristics in reﬂow soldering are:

• Lead-free versus SnPb soldering; note that a lead-free reﬂow process usually leads to

higher minimum peak temperatures (see Figure 25) than a PbSn process, thus reducing the process window

• Solder paste printing issues including smearing, release, and adjusting the process

window for a mix of large and small components on one board

• Reﬂow temperature proﬁle; this proﬁle includes preheat, reﬂow (in which the board is

heated to the peak temperature) and cooling down. It is imperative that the peak temperature is high enough forthe solder to make reliable solder joints (a solder paste characteristic). In addition, the peak temperature must be low enough that the

stg(max)

). If the

Product data sheet Rev. 07 — 13 November 2006 23 of 30

NXP Semiconductors

Table 11. SnPb eutectic process (from J-STD-020C)

Package thickness (mm) Package reﬂow temperature (°C)

< 2.5 235 220 ≥ 2.5 220 220

Table 12. Lead-free process (from J-STD-020C)

Package thickness (mm) Package reﬂow temperature (°C)

< 1.6 260 260 260

1.6 to 2.5 260 250 245 > 2.5 250 245 245

PCA9554/PCA9554A

8-bit I2C-bus and SMBus I/O port with interrupt

packages and/or boards are not damaged. The peak temperature of the package depends on package thickness and volume and is classiﬁed in accordance with

Table 11 and 12

Volume (mm3) < 350 ≥ 350

Volume (mm3) < 350 350 to 2000 > 2000

Moisture sensitivity precautions, as indicated on the packing, must be respected at all times.

Studies have shown that small packages reach higher temperatures during reﬂow soldering, see Figure 25.

maximum peak temperature

temperature

MSL: Moisture Sensitivity Level

Fig 25. Temperature proﬁles for large and small components

= MSL limit, damage level

minimum peak temperature

= minimum soldering temperature

peak

temperature

time

001aac844

For further information on temperature proﬁles, refer to Application Note

“Surface mount reﬂow soldering description”

Product data sheet Rev. 07 — 13 November 2006 24 of 30

AN10365

NXP Semiconductors

13.3.2 Wave soldering

Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems.

To overcome these problems the double-wave soldering method was speciﬁcally developed.

If wave soldering is used the following conditions must be observed for optimal results:

• Use a double-wave soldering method comprising a turbulent wave with high upward

• For packages with leads on two sides and a pitch (e):

• For packages with leads on four sides, the footprint must be placed at a 45° angle to

PCA9554/PCA9554A

8-bit I2C-bus and SMBus I/O port with interrupt

pressure followed by a smooth laminar wave.

– larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be

parallel to the transport direction of the printed-circuit board;

– smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the

transport direction of the printed-circuit board.

The footprint must incorporate solder thieves at the downstream end.

the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners.

During placement and before soldering, the package must be ﬁxed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured.

Typical dwell time of the leads in the wave ranges from 3 seconds to 4 seconds at 250 °C or 265 °C, depending on solder material applied, SnPb or Pb-free respectively.

A mildly-activated ﬂux will eliminate the need for removal of corrosive residues in most applications.

13.3.3 Manual soldering

Fix the component by ﬁrst soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the ﬂat part of the lead. Contact time must be limited to 10 seconds at up to 300 °C.

When using a dedicated tool, all other leads can be soldered in one operation within 2 seconds to 5 seconds between 270 °C and 320 °C.

13.4 Package related soldering information

Table 13. Suitability of IC packages for wave, reﬂow and dipping soldering methods

Mounting Package

Through-hole mount CPGA, HCPGA suitable −−

DBS, DIP, HDIP, RDBS, SDIP, SIL suitable

Through-hole-surface mount

PMFP

[1]

[4]

Soldering method Wave Reﬂow

[3]

not suitable not suitable −

− suitable

[2]

Dipping

Product data sheet Rev. 07 — 13 November 2006 25 of 30

NXP Semiconductors

PCA9554/PCA9554A

8-bit I2C-bus and SMBus I/O port with interrupt

Table 13. Suitability of IC packages for wave, reﬂow and dipping soldering methods

Mounting Package

[1]

Soldering method Wave Reﬂow

Surface mount BGA, HTSSON..T

LFBGA,SQFP, SSOP..T

[5]

, LBGA,

[5]

,TFBGA,

not suitable suitable −

…continued

[2]

Dipping

VFBGA, XSON DHVQFN, HBCC, HBGA, HLQFP,

not suitable

[6]

suitable − HSO, HSOP, HSQFP, HSSON, HTQFP, HTSSOP, HVQFN, HVSON, SMS

[7]

PLCC LQFP, QFP, TQFP not recommended SSOP, TSSOP, VSO, VSSOP not recommended CWQCCN..L

[1] For more detailed information on the BGA packages refer to the

Semiconductors sales ofﬁce.

[2] All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with

respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of

the moisture in them (the so called popcorn effect). [3] For SDIP packages, the longitudinal axis must be parallel to the transport direction of the printed-circuit board. [4] Hot bar soldering or manual soldering is suitable for PMFP packages. [5] These transparent plastic packages are extremely sensitive to reﬂow soldering conditions and must on no account be processed

through more than one soldering cycle or subjected to infrared reﬂow soldering with peak temperature exceeding 217 °C ± 10 °C

measured in the atmosphere of the reﬂow oven. The package body peak temperature must be kept as low as possible. [6] These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the solder cannot penetrate

between the printed-circuit board and the heatsink. On versions with the heatsink on the top side, the solder might be deposited on the

heatsink surface. [7] If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction. The package footprint

must incorporate solder thieves downstream and at the side corners. [8] Wave soldering is suitable for LQFP, QFP and TQFP packages with a pitch (e) larger than 0.8 mm; it is deﬁnitely not suitable for

packages with a pitch (e) equal to or smaller than 0.65 mm. [9] Wave soldering is suitable for SSOP, TSSOP, VSO and VSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is deﬁnitely

not suitable for packages with a pitch (e) equal to or smaller than 0.5mm. [10] Image sensor packages in principle should not be soldered. They are mounted in sockets or delivered pre-mounted on ﬂex foil.

However, the image sensor package can be mounted by the client on a ﬂex foil by using a hot bar soldering process. The appropriate

soldering proﬁle can be provided on request.

, SO, SOJ suitable suitable −

[10]

, WQCCN..L

[10]

not suitable not suitable −

(LF)BGA Application Note

[7][8] [9]

(AN01026); order a copy from your NXP

suitable − suitable −

Product data sheet Rev. 07 — 13 November 2006 26 of 30

NXP Semiconductors

14. Abbreviations

Table 14. Abbreviations

Acronym Description

ACPI Advanced Conﬁguration and Power Interface CDM Charged Device Model CMOS Complementary Metal Oxide Semiconductor ESD ElectroStatic Discharge FET Field-Effect Transistor GPIO General Purpose Input/Output HBM Human Body Model

C-bus Inter-Integrated Circuit bus

I I/O Input/Output LED Light-Emitting Diode MM Machine Model PCB Printed-Circuit Board POR Power-On Reset SMBus System Management Bus

PCA9554/PCA9554A

8-bit I2C-bus and SMBus I/O port with interrupt

Product data sheet Rev. 07 — 13 November 2006 27 of 30

NXP Semiconductors

PCA9554/PCA9554A

8-bit I2C-bus and SMBus I/O port with interrupt

15. Revision history

Table 15. Revision history

Document ID Release date Data sheet status Change notice Supersedes

PCA9554_9554A_7 20061113 Product data sheet - PCA9554_9554A_6 Modiﬁcations:

PCA9554_9554A_6 (9397 750 13289)

PCA9554_9554A_5 (9397 750 10163)

PCA9554_9554A_4 (9397 750 09817)

PCA9554_9554A_3 (9397 750 08342)

PCA9554_9554A_2 (9397 750 08209)

PCA9554_9554A_1 (9397 750 08159)

• The format of this data sheet has been redesigned to comply with the new identity guidelines

of NXP Semiconductors.

• Legal texts have been adapted to the new company name where appropriate.

• Added HVQFN16 (SOT758-1) and bare die package offerings

• Pin names I/O0 through I/O7 changed to IO0 through IO7

• Table 2 “Pin description”: added Table note 1 and its reference at HVQFN pin 6 (V

• Symbol (t

and tPV) changed to t

and tPH) changed to t

and tPS) changed to t

and tIV) changed to t

and tIR) changed to t

v(Q)

h(D)

su(D)

v(INT_N)

rst(INT_N)

• Figure 16 “Typical application” modiﬁed (deleted “PCA9554A”)

• Table 8 “Limiting values”:

– Changed parameter description for symbol V

an input/output pin”

– Changed symbol “I – Changed parameter description of I

, DC output current on an I/O” to “I

I/O

from “supply current” to “ground supply current”

from “DC voltage on an I/O” to “voltage on

I/O

, output current on pin IOn”

O(IOn)

• Table 9 “Static characteristics”:

– Symbols “I

” and “I

stbl

” replaced with “I

stbh

stb

”

• Added Section 14 “Abbreviations”

20040930 Product data - PCA9554_9554A_5

20020726 Product data 853-2243 28672of

26 July 2002

20020513 Product speciﬁcation - PCA9554_9554A_3

20010507 Product speciﬁcation - PCA9554_9554A_2

20010319 Product speciﬁcation - PCA9554_9554A_1

20010319 Product speciﬁcation - -

PCA9554_9554A_4

)

Product data sheet Rev. 07 — 13 November 2006 28 of 30

NXP Semiconductors

16. Legal information

16.1 Data sheet status

PCA9554/PCA9554A

8-bit I2C-bus and SMBus I/O port with interrupt

Document status

Objective [short] data sheet Development This document contains data from the objective speciﬁcation for product development. Preliminary [short] data sheet Qualiﬁcation This document contains data from the preliminary speciﬁcation. Product [short] data sheet Production This document contains the product speciﬁcation.

[1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Deﬁnitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices.The latest product status

information is available on the Internet at URL

[1][2]

Product status

16.2 Deﬁnitions

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in modiﬁcations or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information.

Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title.A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales ofﬁce. In case of any inconsistency or conﬂict with the short data sheet, the full data sheet shall prevail.

16.3 Disclaimers

General — Information in this document is believed to be accurate and

reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information.

Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation speciﬁcations and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof.

Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of a NXP Semiconductors product can reasonably be expected to

[3]

http://www.nxp.com.

Deﬁnition

result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk.

Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the speciﬁed use without further testing or modiﬁcation.

Limiting values — Stress above one or more limiting values (as deﬁned in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability.

Terms and conditions of sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at

http://www.nxp.com/proﬁle/terms, including those pertaining to warranty,

intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conﬂict between information in this document and such terms and conditions, the latter will prevail.

No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyanceor implication of any license under any copyrights, patents or other industrial or intellectual property rights.

16.4 Trademarks

Notice: All referenced brands,product names,service names and trademarks are the property of their respective owners.

I2C-bus — logo is a trademark of NXP B.V.

17. Contact information

For additional information, please visit: http://www.nxp.com For sales ofﬁce addresses, send an email to: salesaddresses@nxp.com

Product data sheet Rev. 07 — 13 November 2006 29 of 30

NXP Semiconductors

18. Contents

1 General description . . . . . . . . . . . . . . . . . . . . . . 1

2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

3 Ordering information. . . . . . . . . . . . . . . . . . . . . 2

4 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3

5 Pinning information. . . . . . . . . . . . . . . . . . . . . . 4

5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 6

6 Functional description . . . . . . . . . . . . . . . . . . . 6

6.1 Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

6.1.1 Command byte . . . . . . . . . . . . . . . . . . . . . . . . . 6

6.1.2 Register 0 - Input Port register . . . . . . . . . . . . . 7

6.1.3 Register 1 - Output Port register. . . . . . . . . . . . 7

6.1.4 Register 2 - Polarity Inversion register . . . . . . . 8

6.1.5 Register 3 - Conﬁguration register . . . . . . . . . . 8

6.2 Power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . 8

6.3 Interrupt output. . . . . . . . . . . . . . . . . . . . . . . . . 9

6.4 I/O port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

6.5 Device address. . . . . . . . . . . . . . . . . . . . . . . . 10

6.6 Bus transactions. . . . . . . . . . . . . . . . . . . . . . . 10

7 Application design-in information . . . . . . . . . 12

8 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 12

9 Static characteristics. . . . . . . . . . . . . . . . . . . . 13

10 Dynamic characteristics . . . . . . . . . . . . . . . . . 14

11 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 16

12 Handling information. . . . . . . . . . . . . . . . . . . . 23

13 Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

13.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . 23

13.2 Through-hole mount packages. . . . . . . . . . . . 23

13.2.1 Soldering by dipping or by solder wave . . . . . 23

13.2.2 Manual soldering . . . . . . . . . . . . . . . . . . . . . . 23

13.3 Surface mount packages . . . . . . . . . . . . . . . . 23

13.3.1 Reﬂow soldering. . . . . . . . . . . . . . . . . . . . . . . 23

13.3.2 Wave soldering. . . . . . . . . . . . . . . . . . . . . . . . 25

13.3.3 Manual soldering . . . . . . . . . . . . . . . . . . . . . . 25

13.4 Package related soldering information . . . . . . 25

14 Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 27

15 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 28

16 Legal information. . . . . . . . . . . . . . . . . . . . . . . 29

16.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 29

16.2 Deﬁnitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

16.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 29

16.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 29

17 Contact information. . . . . . . . . . . . . . . . . . . . . 29

18 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

PCA9554/PCA9554A

8-bit I2C-bus and SMBus I/O port with interrupt

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Date of release: 13 November 2006

Document identifier: PCA9554_9554A_7

NXP PCA 9554 D Datasheet

Specifications and Main Features

Frequently Asked Questions

User Manual

1. General description

2. Features

3. Ordering information

4. Block diagram

5. Pinning information

5.1 Pinning

5.2 Pin description

6. Functional description

6.1 Registers

6.1.1 Command byte

6.1.2 Register 0 - Input Port register

6.1.3 Register 1 - Output Port register

6.1.4 Register 2 - Polarity Inversion register

6.2 Power-on reset

6.3 Interrupt output

6.4 I/O port

6.5 Device address

6.6 Bus transactions

7. Application design-in information

8. Limiting values

9. Static characteristics

10. Dynamic characteristics

11. Package outline

12. Handling information

13. Soldering

13.1 Introduction

13.2 Through-hole mount packages

13.2.1 Soldering by dipping or by solder wave

13.2.2 Manual soldering

13.3 Surface mount packages

13.3.2 Wave soldering

13.3.3 Manual soldering

13.4 Package related soldering information

14. Abbreviations

15. Revision history

16. Legal information

16.1 Data sheet status

16.3 Disclaimers

16.4 Trademarks

17. Contact information

18. Contents