PCA9554/PCA9554A
8-bit I2C-bus and SMBus I/O port with interrupt
Rev. 07 — 13 November 2006 Product data sheet
1. General description
The PCA9554 and PCA9554A are 16-pin CMOS devices that provide 8 bits of General
Purpose parallel Input/Output (GPIO) expansion for I2C-bus/SMBus applications and
were developed to enhance the NXP Semiconductors family of I2C-bus I/O expanders.
The improvements include higher drive capability, 5 V I/O tolerance, lower supply current,
individual I/O configuration, 400 kHz clock frequency, and smaller packaging. I/O
expanders provide a simple solution when additional I/O is needed for ACPI power
switches, sensors, push buttons, LEDs, fans, etc.
The PCA9554/PCA9554A consist of an 8-bit Configuration register (Input or Output
selection); 8-bit Input Port register, 8-bit Output Port register and an 8-bit Polarity
Inversion register (active HIGH or active LOW operation). The system master can enable
the I/Os as either inputs or outputs by writing to the I/O configuration bits. The data for
each input or output is kept in the corresponding Input Port or Output Port register. The
polarity of the read register can be inverted with the Polarity Inversion register. All
registers can be read by the system master. Although pin-to-pin and I2C-bus address
compatible with the PCF8574 series, software changes are required due to the
enhancements and are discussed in
Application Note AN469
.
2. Features
The PCA9554/PCA9554A open-drain interrupt output is activated when any input state
differs from its corresponding Input Port register state and is used to indicate to the
system master that an input state has changed. The power-on reset sets the registers to
their default values and initializes the device state machine.
Three hardware pins (A0, A1, A2) vary the fixed I2C-bus address and allow up to eight
devices to share the same I2C-bus/SMBus. The PCA9554A is identical to the PCA9554
except that the fixed I2C-bus address is different allowing up to sixteen of these devices
(eight of each) on the same I2C-bus/SMBus.
n Operating power supply voltage range of 2.3 V to 5.5 V
n 5 V tolerant I/Os
n Polarity Inversion register
n Active LOW interrupt output
n Low standby current
n Noise filter on SCL/SDA inputs
n No glitch on power-up
n Internal power-on reset
n 8 I/O pins which default to 8 inputs
n 0 Hz to 400 kHz clock frequency
NXP Semiconductors
PCA9554/PCA9554A
8-bit I2C-bus and SMBus I/O port with interrupt
n ESD protection exceeds 2000 V HBM per JESD22-A114, 200 V MM per
JESD22-A115 and 1000 V CDM per JESD22-C101
n Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA
n Packages offered: DIP16, SO16, SSOP16, SSOP20, TSSOP16,
HVQFN16 (2 versions: 4 × 4 × 0.85 mm and 3 × 3 × 0.85 mm), and bare die
3. Ordering information
Table 1. Ordering information
T
=−40°C to +85°C.
amb
Type number Topside mark Package
Name Description Version
PCA9554N PCA9554N DIP16 plastic dual in-line package; 16 leads (300 mil);
PCA9554AN PCA9554AN
PCA9554D PCA9554D SO16 plastic small outline package; 16 leads;
PCA9554AD PCA9554AD
PCA9554DB 9554DB SSOP16 plastic shrink small outline package; 16 leads;
PCA9554ADB 9554A
PCA9554TS PCA9554 SSOP20 plastic shrink small outline package; 20 leads;
PCA9554ATS PA9554A
PCA9554PW 9554DH TSSOP16 plastic thin shrink small outline package; 16 leads;
PCA9554APW 9554ADH
PCA9554BS 9554 HVQFN16 plastic thermal enhanced very thin quad flat package;
PCA9554ABS 554A
PCA9554BS3 P54 HVQFN16 plastic thermal enhanced very thin quad flat package;
PCA9554ABS3 54A
PCA9554U - bare die - -
long body
body width 7.5 mm
body width 5.3 mm
body width 4.4 mm
body width 4.4 mm
no leads; 16 terminals; body 4 × 4 × 0.85 mm
no leads; 16 terminals; body 3 × 3 × 0.85 mm
SOT38-1
SOT162-1
SOT338-1
SOT266-1
SOT403-1
SOT629-1
SOT758-1
PCA9554_9554A_7 © NXP B.V. 2006. All rights reserved.
Product data sheet Rev. 07 — 13 November 2006 2 of 30
NXP Semiconductors
4. Block diagram
PCA9554/PCA9554A
8-bit I2C-bus and SMBus I/O port with interrupt
A0
A1
A2
SCL
SDA
V
DD
V
SS
INPUT
FILTER
POWER-ON
RESET
I2C-BUS/SMBus
CONTROL
All I/Os are set to inputs at reset.
Fig 1. Block diagram of PCA9554/PCA9554A
PCA9554/PCA9554A
8-bit
write pulse
read pulse
INPUT/
OUTPUT
PORTS
LP
FILTER
002aac492
IO0
IO1
IO2
IO3
IO4
IO5
IO6
IO7
V
DD
INT
PCA9554_9554A_7 © NXP B.V. 2006. All rights reserved.
Product data sheet Rev. 07 — 13 November 2006 3 of 30
NXP Semiconductors
5. Pinning information
5.1 Pinning
PCA9554/PCA9554A
8-bit I2C-bus and SMBus I/O port with interrupt
PCA9554N
PCA9554AN
1
A0 V
2
A1 SDA
3
A2 SCL
4
IO0 INT
5
IO1 IO7
6
IO2 IO6
7
IO3 IO5
8
V
SS
002aac485
16
DD
15
14
13
12
11
10
9
IO4
V
A0
A1
A2
IO0
IO1
IO2
IO3
SS
1
2
3
4
5
6
7
8
PCA9554D
PCA9554AD
002aac486
16
15
14
13
12
11
10
9
Fig 2. Pin configuration for DIP16 Fig 3. Pin configuration for SO16
IO0
IO1
IO2
IO3
V
A0
A1
A2
SS
1
2
3
4
5
6
7
8
PCA9554DB
PCA9554ADB
002aac487
16
V
DD
15
SDA
14
SCL
13
INT
12
IO7
11
IO6
10
IO5
IO4
9
IO0
IO1
IO2
IO3
V
A0
A1
A2
SS
1
2
3
4
5
6
7
8
PCA9554PW
PCA9554APW
002aac488
16
15
14
13
12
11
10
9
V
DD
SDA
SCL
INT
IO7
IO6
IO5
IO4
V
DD
SDA
SCL
INT
IO7
IO6
IO5
IO4
Fig 4. Pin configuration for SSOP16 Fig 5. Pin configuration for TSSOP16
PCA9554_9554A_7 © NXP B.V. 2006. All rights reserved.
Product data sheet Rev. 07 — 13 November 2006 4 of 30
NXP Semiconductors
PCA9554/PCA9554A
8-bit I2C-bus and SMBus I/O port with interrupt
1
INT IO7
2
SCL IO6
3
n.c. n.c.
4
SDA IO5
5
V
DD
6
A0 V
7
A1 IO3
8
n.c. n.c.
9
A2 IO2
10
IO0 IO1
Fig 6. Pin configuration for SSOP20
PCA9554BS
PCA9554ABS
terminal 1
index area
A2 SCL
IO0 INT
IO1 IO7
IO2
A1
16
1 12
2 11
3 10
4 9
A0
15
DD
SDA
V
14
13
PCA9554TS
PCA9554ATS
IO6
20
19
18
17
16
IO4
15
SS
14
13
12
11
002aac489
PCA9554BS3
PCA9554ABS3
terminal 1
index area
A2 SCL
IO0
IO1 IO7
IO2 IO6
A1
A0
16
15
1 12
2 11
3 10
4 9
DD
SDA
V
14
13
INT
5
IO3
Transparent top view
7
6
V
SS
IO4
8
IO5
002aac490
Fig 7. Pin configuration for HVQFN16
(SOT629-1)
5
IO3
Transparent top view
7
6
SS
V
IO4
8
IO5
002aac491
Fig 8. Pin configuration for HVQFN16
(SOT758-1)
PCA9554_9554A_7 © NXP B.V. 2006. All rights reserved.
Product data sheet Rev. 07 — 13 November 2006 5 of 30
NXP Semiconductors
5.2 Pin description
Table 2. Pin description
Symbol Pin Description
A0 1 15 6 address input 0
A1 2 16 7 address input 1
A2 3 1 9 address input 2
IO0 4 2 10 input/output 0
IO1 5 3 11 input/output 1
IO2 6 4 12 input/output 2
IO3 7 5 14 input/output 3
V
SS
IO4 9 7 16 input/output 4
IO5 10 8 17 input/output 5
IO6 11 9 19 input/output 6
IO7 12 10 20 input/output 7
INT 13 11 1 interrupt output (open-drain)
SCL 14 12 2 serial clock line
SDA 15 13 4 serial data line
V
DD
n.c. - - 3, 8, 13, 18 not connected
PCA9554/PCA9554A
8-bit I2C-bus and SMBus I/O port with interrupt
DIP16, SO16,
SSOP16, TSSOP16
86
16 14 5 supply voltage
HVQFN16 SSOP20
[1]
15 supply ground
[1] HVQFN package die supply groundis connected to both VSSpin and exposed center pad. VSSpin must be
connected to supply ground for proper device operation. For enhanced thermal, electrical, and board level
performance, the exposed pad needs to be soldered to the board using a corresponding thermal pad on the
board and forproper heat conduction through the board, thermal vias need to be incorporated in the PCB in
the thermal pad region.
6. Functional description
Refer to Figure 1 “Block diagram of PCA9554/PCA9554A”.
6.1 Registers
6.1.1 Command byte
Table 3. Command byte
Command Protocol Function
0 read byte Input Port register
1 read/write byte Output Port register
2 read/write byte Polarity Inversion register
3 read/write byte Configuration register
The command byte is the first byte to follow the address byte during a write transmission.
It is used as a pointer to determine which of the following registers will be written or read.
PCA9554_9554A_7 © NXP B.V. 2006. All rights reserved.
Product data sheet Rev. 07 — 13 November 2006 6 of 30
NXP Semiconductors
6.1.2 Register 0 - Input Port register
This register is a read-only port. It reflects the incoming logic levels of the pins, regardless
of whether the pin is defined as an input or an output by Register 3. Writes to this register
have no effect.
The default ‘X’ is determined by the externally applied logic level, normally ‘1’ when no
external signal externally applied because of the internal pull-up resistors.
Table 4. Register 0 - Input Port register bit description
Bit Symbol Access Value Description
7 I7 read only X determined by externally applied logic level
6 I6 read only X
5 I5 read only X
4 I4 read only X
3 I3 read only X
2 I2 read only X
1 I1 read only X
0 I0 read only X
PCA9554/PCA9554A
8-bit I2C-bus and SMBus I/O port with interrupt
6.1.3 Register 1 - Output Port register
This register reflects the outgoing logic levels of the pins defined as outputs by Register 3.
Bit values in this register have no effect on pins defined as inputs. Reads from this register
return the value that is in the flip-flop controlling the output selection, not the actual pin
value.
Table 5. Register 1 - Output Port register bit description
Legend: * default value.
Bit Symbol Access Value Description
7 O7 R 1* reflects outgoing logic levels of pins defined as
6O6 R 1*
5O5 R 1*
4O4 R 1*
3O3 R 1*
2O2 R 1*
1O1 R 1*
0O0 R 1*
outputs by Register 3
PCA9554_9554A_7 © NXP B.V. 2006. All rights reserved.
Product data sheet Rev. 07 — 13 November 2006 7 of 30
NXP Semiconductors
6.1.4 Register 2 - Polarity Inversion register
This register allows the user to invert the polarity of the Input Port register data. If a bit in
this register is set (written with ‘1’), the corresponding Input Port data is inverted. If a bit in
this register is cleared (written with a ‘0’), the Input Port data polarity is retained.
Table 6. Register 2 - Polarity Inversion register bit description
Legend: * default value.
Bit Symbol Access Value Description
7 N7 R/W 0* inverts polarity of Input Port register data
6 N6 R/W 0*
5 N5 R/W 0*
4 N4 R/W 0*
3 N3 R/W 0*
2 N2 R/W 0*
1 N1 R/W 0*
0 N0 R/W 0*
PCA9554/PCA9554A
8-bit I2C-bus and SMBus I/O port with interrupt
0 = Input Port register data retained (default value)
1 = Input Port register data inverted
6.1.5 Register 3 - Configuration register
This register configures the directions of the I/O pins. If a bit in this register is set, the
corresponding port pin is enabled as an input with high-impedance output driver.If a bit in
this register is cleared, the corresponding port pin is enabled as an output. At reset, the
I/Os are configured as inputs with a weak pull-up to VDD.
Table 7. Register 3 - Configuration register bit description
Legend: * default value.
Bit Symbol Access Value Description
7 C7 R/W 1* configures the directions of the I/O pins
6 C6 R/W 1*
5 C5 R/W 1*
4 C4 R/W 1*
3 C3 R/W 1*
2 C2 R/W 1*
1 C1 R/W 1*
0 C0 R/W 1*
6.2 Power-on reset
When power is applied to VDD, an internal Power-On Reset (POR) holds the
PCA9554/PCA9554A in a reset condition until VDD has reached V
reset condition is released and the PCA9554/PCA9554A registers and state machine will
initialize to their default states. Thereafter, VDD must be lowered below 0.2 V to reset the
device.
0 = corresponding port pin enabled as an output
1 = corresponding port pin configured as input
(default value)
. At that point, the
POR
For a power reset cycle, VDD must be lowered below 0.2 V and then restored to the
operating voltage.
PCA9554_9554A_7 © NXP B.V. 2006. All rights reserved.
Product data sheet Rev. 07 — 13 November 2006 8 of 30
NXP Semiconductors
6.3 Interrupt output
The open-drain interrupt output is activated when one of the port pins change state and
the pin is configured as an input. The interrupt is deactivated when the input returns to its
previous state or the Input Port register is read.
Note that changing an I/O from and output to an input may cause a false interrupt to occur
if the state of the pin does not match the contents of the Input Port register.
6.4 I/O port
When an I/O is configured as an input, FETs Q1 and Q2 are off, creating a
high-impedance input with a weak pull-up (100 kΩ typ.) to VDD. The input voltage may be
raised above VDD to a maximum of 5.5 V.
If the I/O is configured as an output, then either Q1 or Q2 is enabled, depending on the
state of the Output Port register. Care should be exercised if an external voltage is applied
to an I/O configured as an output because of the low-impedance paths that exist between
the pin and either VDD or VSS.
PCA9554/PCA9554A
8-bit I2C-bus and SMBus I/O port with interrupt
data from
shift register
data from
shift register
write configuration
pulse
write pulse
read pulse
data from
shift register
write polarity
pulse
configuration
register
DQ
FF
CK Q
DQ
FF
CK
output port
register
input port
register
DQ
FF
CK
polarity inversion
register
DQ
FF
CK
Q1
100 kΩ
Q2
output port
register data
V
DD
IO0 to IO7
V
SS
input port
register data
to INT
polarity inversion
register data
002aac493
Remark: At power-on reset, all registers return to default values.
Fig 9. Simplified schematic of IO0 to IO7
PCA9554_9554A_7 © NXP B.V. 2006. All rights reserved.
Product data sheet Rev. 07 — 13 November 2006 9 of 30
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