PCA9551
8-bit I2C-bus LED driver with programmable blink rates
Rev. 08 — 31 July 2008 Product data sheet
1. General description
The PCA9551 LED blinker blinks LEDs in I2C-bus and SMBus applications where it is
necessary to limit bus traffic or free up the I2C-bus master's (MCU, MPU, DSP, chip set,
etc.) timer. The uniqueness of this device is the internal oscillator with two programmable
blink rates. To blink LEDs using normal I/O expanders like the PCF8574 or PCA9554, the
bus master must send repeated commands to turn the LED on and off. This greatly
increases the amount of traffic on the I2C-bus and uses up one of the master's timers.
The PCA9551 LED blinker instead requires only the initial set-up command to program
BLINK RATE 1 and BLINK RATE 2 (i.e., the frequency and duty cycle) for each individual
output. From then on, only one command from the bus master is required to turn each
individual open-drain output on, off, or to cycle at BLINK RATE 1 or BLINK RATE 2.
Maximum output sink current is 25 mA per bit and 100 mA per package.
Any bits not used for controlling the LEDs can be used for General Purpose parallel
Input/Output (GPIO) expansion.
2. Features
The active LOW hardware reset pin (RESET) and Power-On Reset (POR) initializes the
registers to their default state, all zeroes, causing the bits to be set HIGH (LED off).
Three hardwareaddress pins on the PCA9551 allow eight devicesto operateon the same
bus.
The newer Fast-mode Plus PCA9634 8-bit LED controller offers an individual PWM
dimming control for each channel for better color mixing capabilities with a global PWM for
dimming or blinking all channels at the same time. There are 126 possible address
combinations and the maximum output sink current is 25 mA per bit and 200 mA per
package.
n 8 LED drivers (on, off, flashing at a programmable rate)
n 2 selectable, fully programmable blink rates (frequency and duty cycle) between
0.148 Hz and 38 Hz (6.74 seconds and 0.026 seconds)
n Input/outputs not used as LED drivers can be used as regular GPIOs
n Internal oscillator requires no external components
n I2C-bus interface logic compatible with SMBus
n Internal power-on reset
n Noise filter on SCL/SDA inputs
n Active LOW reset input
n 8 open-drain outputs directly drive LEDs to 25 mA
n Edge rate control on outputs
NXP Semiconductors
PCA9551
8-bit I2C-bus LED driver with programmable blink rates
n No glitch on power-up
n Supports hot insertion
n Low standby current
n Operating power supply voltage range of 2.3 V to 5.5 V
n 0 Hz to 400 kHz clock frequency
n ESD protection exceeds 2000 V HBM per JESD22-A114, 150 V MM per
JESD22-A115 and 1000 V CDM per JESD22-C101
n Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA
n Packages offered: SO16, TSSOP16, HVQFN16
3. Ordering information
Table 1. Ordering information
T
=−40°C to +85°C.
amb
Type number Topside
mark
PCA9551D PCA9551D SO16 plastic small outline package; 16 leads; body width 3.9 mm SOT109-1
PCA9551PW PCA9551 TSSOP16 plastic thin shrink small outline package; 16 leads;
PCA9551BS 9551 HVQFN16 plastic thermal enhanced very thin quad flat package;
Package
Name Description Version
SOT403-1
body width 4.4 mm
SOT629-1
no leads; 16 terminals; body 4 × 4 × 0.85 mm
4. Block diagram
PCA9551
SCL
SDA
V
DD
RESET
V
SS
Only one I/O shown for clarity.
Fig 1. Block diagram of PCA9551
INPUT
FILTERS
POWER-ON
RESET
OSCILLATOR
A0 A1 A2
I2C-BUS
CONTROL
PRESCALER 0
REGISTER
PRESCALER 1
REGISTER
PWM0
REGISTER
PWM1
REGISTER
REGISTER
LED SELECT (LSn)
REGISTER
0
1
BLINK0
BLINK1
INPUT
LEDn
002aac504
PCA9551_8 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 08 — 31 July 2008 2 of 26
NXP Semiconductors
5. Pinning information
5.1 Pinning
PCA9551
8-bit I2C-bus LED driver with programmable blink rates
A0
A1
A2
LED0
LED1
LED2
LED3
V
SS
1
2
3
4
5
6
7
8
PCA9551D
002aac500
16
15
14
13
12
11
10
9
V
DD
SDA
SCL
RESET
LED7
LED6
LED5
LED4
A0
A1
A2
LED0
LED1
LED2
LED3
V
SS
1
2
3
4
5
6
7
8
PCA9551PW
002aac501
16
15
14
13
12
11
10
9
V
DD
SDA
SCL
RESET
LED7
LED6
LED5
LED4
Fig 2. Pin configuration for SO16 Fig 3. Pin configuration for TSSOP16
terminal 1
index area
A2 SCL
LED0 RESET
LED1 LED7
LED2
A1
16
1 12
2 11
PCA9551BS
3 10
4 9
5
LED3
Transparent top view
A0
15
6
V
SS
DD
V
14
7
LED4
SDA
13
LED6
8
002aac502
LED5
Fig 4. Pin configuration for HVQFN16
5.2 Pin description
Table 2. Pin description
Symbol Pin Description
SO16, TSSOP16 HVQFN16
A0 1 15 address input 0
A1 2 16 address input 1
A2 3 1 address input 2
LED0 4 2 LED driver 0
LED1 5 3 LED driver 1
LED2 6 4 LED driver 2
LED3 7 5 LED driver 3
V
SS
86
LED4 9 7 LED driver 4
LED5 10 8 LED driver 5
LED6 11 9 LED driver 6
PCA9551_8 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 08 — 31 July 2008 3 of 26
[1]
supply ground
NXP Semiconductors
PCA9551
8-bit I2C-bus LED driver with programmable blink rates
Table 2. Pin description
Symbol Pin Description
SO16, TSSOP16 HVQFN16
LED7 12 10 LED driver 7
RESET 13 11 reset input (active LOW)
SCL 14 12 serial clock line
SDA 15 13 serial data line
V
DD
[1] HVQFN16 package die supply ground is connected to both VSS pin and exposed center pad. VSS pin must
16 14 supply voltage
be connected to supply ground for proper device operation. For enhanced thermal, electrical, and board
level performance, the exposed pad needs to be soldered to the board using a corresponding thermal pad
on the board and for proper heat conduction through the board, thermal vias need to be incorporated in the
PCB in the thermal pad region.
6. Functional description
Refer to Figure 1 “Block diagram of PCA9551”.
6.1 Device address
Following a START condition, the bus master must output the address of the slave it is
accessing. The address of the PCA9551 is shown in Figure 5. To conserve power, no
internal pull-up resistors are incorporated on the hardware selectable address pins and
they must be pulled HIGH or LOW.
…continued
slave address
1 1 0 0 A2 A1 A0 R/W
fixed
Fig 5. PCA9551 slave address
hardware
selectable
002aac505
The last bit of the address byte defines the operation to be performed. When set to logic 1
a read is selected, while a logic 0 selects a write operation.
6.2 Control register
Followingthe successful acknowledgement of the slave address, the bus master will send
a byte to the PCA9551, which will be stored in the Control register.
0 0 0 AI 0 B2 B1 B0
Auto-Increment flag
Reset state: 00h
Fig 6. Control register
register address
002aac506
The lowest 3 bits are used as a pointer to determine which register will be accessed.
PCA9551_8 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 08 — 31 July 2008 4 of 26
NXP Semiconductors
If the Auto-Increment (AI) flag is set, the three low order bits of the Control register are
automatically incremented after a read or write. This allows the user to program the
registers sequentially. The contents of these bits will rollover to ‘000’ after the last register
is accessed.
When the Auto-Increment flag is set (AI = 1) and a read sequence is initiated, the
sequence must start by reading a register different from ‘0' (B2 B1 B0 ≠ 000).
Only the 3 least significant bits are affected by the AI flag. Unused bits must be
programmed with zeroes.
6.2.1 Control register definition
Table 3. Register summary
B2 B1 B0 Symbol Access Description
0 0 0 INPUT read only input register
0 0 1 PSC0 read/write frequency prescaler 0
0 1 0 PWM0 read/write PWM register 0
0 1 1 PSC1 read/write frequency prescaler 1
1 0 0 PWM1 read/write PWM register 1
1 0 1 LS0 read/write LED0 to LED3 selector
1 1 0 LS1 read/write LED4 to LED7 selector
PCA9551
8-bit I2C-bus LED driver with programmable blink rates
6.3 Register descriptions
6.3.1 INPUT - Input register
The INPUT register reflects the state of the device pins. Writes to this register will be
acknowledged but will have no effect.
Table 4. INPUT - Input register description
Bit 7 6 5 4 3 2 1 0
Symbol LED7 LED6 LED5 LED4 LED3 LED2 LED1 LED0
Default XXXXXXXX
Remark: The default value ‘X’ is determined by the externally applied logic level (normally
logic 1) when used for directly driving LED with pull-up to VDD.
6.3.2 PSC0 - Frequency Prescaler 0
PSC0 is used to program the period of the PWM output.
The period of BLINK0 = (PSC0 + 1) / 38.
Remark: Prescaler calculation is different between the PCA9551 and other PCA955x
LED blinkers.A divider ratio of 38 instead of 44 is used. This different divider ratio causes
the blinking frequency to be 13 % (1 − 38 / 44) lower when the same 8-bit word is used.
The programmed value of FrequencyPrescaler 0 must be adjusted to compensate for this
difference in applications where the PCA9551 is used in conjunction with other PCA955x
LED blinkers and the observed blinking frequencies need to be the same.
PCA9551_8 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 08 — 31 July 2008 5 of 26
NXP Semiconductors
Table 5. PSC0 - Frequency Prescaler 0 register description
Bit 7 6 5 4 3 2 1 0
Symbol PSC0[7] PSC0[6] PSC0[5] PSC0[4] PSC0[3] PSC0[2] PSC0[1] PSC0[0]
Default 11111111
6.3.3 PWM0 - Pulse Width Modulation 0
The PWM0 register determines the duty cycle of BLINK0. The outputs are LOW (LED off)
when the count is less than the value in PWM0 and HIGH when it is greater. If PWM0 is
programmed with 00h, then the PWM0 output is always LOW.
The duty cycle of BLINK0 = (256 − PWM0) / 256.
Table 6. PWM0 - Pulse Width Modulation 0 register description
Bit 7 6 5 4 3 2 1 0
Symbol PWM0
Default 10000000
[7]
PWM0
[6]
PCA9551
8-bit I2C-bus LED driver with programmable blink rates
PWM0
[5]
PWM0
[4]
PWM0
[3]
PWM0
[2]
PWM0
[1]
PWM0
[0]
6.3.4 PSC1 - Frequency Prescaler 1
PSC1 is used to program the period of the PWM output.
The period of BLINK1 = (PSC1 + 1) / 38.
Remark: Prescaler calculation is different between the PCA9551 and other PCA955x
LED blinkers.A divider ratio of 38 instead of 44 is used. This different divider ratio causes
the blinking frequency to be 13 % (1 − 38 / 44) lower when the same 8-bit word is used.
The programmed value of FrequencyPrescaler 1 must be adjusted to compensate for this
difference in applications where the PCA9551 is used in conjunction with other PCA955x
LED blinkers and the observed blinking frequencies need to be the same.
Table 7. PSC1 - Frequency Prescaler 1 register description
Bit 7 6 5 4 3 2 1 0
Symbol PSC1[7] PSC1[6] PSC1[5] PSC1[4] PSC1[3] PSC1[2] PSC1[1] PSC1[0]
Default 11111111
6.3.5 PWM1 - Pulse Width Modulation 1
The PWM1 register determines the duty cycle of BLINK1. The outputs are LOW (LED off)
when the count is less than the value in PWM1 and HIGH when it is greater. If PWM1 is
programmed with 00h, then the PWM1 output is always LOW (LED off).
The duty cycle of BLINK1 = (256 − PWM1) / 256.
Table 8. PWM1 - Pulse Width Modulation 1 register description
Bit 7 6 5 4 3 2 1 0
Symbol PWM1
[7]
Default 10000000
PCA9551_8 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 08 — 31 July 2008 6 of 26
PWM1
[6]
PWM1
[5]
PWM1
[4]
PWM1
[3]
PWM1
[2]
PWM1
[1]
PWM1
[0]
NXP Semiconductors
6.3.6 LS0 to LS1 - LED selector registers
The LSn LED select registers determine the source of the LED data.
00 = output is set LOW (LED on)
01 = output is set high-impedance (LED off; default)
10 = output blinks at PWM0 rate
11 = output blinks at PWM1 rate
Table 9. LS0 to LS1 - LED selector registers bit description
Legend: * default value.
Register Bit Value Description
LS0 - LED0 to LED3 selector
LS0 7:6 01* LED3 selected
LS1 - LED4 to LED7 selector
LS1 7:6 01* LED7 selected
PCA9551
8-bit I2C-bus LED driver with programmable blink rates
5:4 01* LED2 selected
3:2 01* LED1 selected
1:0 01* LED0 selected
5:4 01* LED6 selected
3:2 01* LED5 selected
1:0 01* LED4 selected
6.4 Pins used as GPIOs
LED pins not used to control LEDs can be used as general purpose I/Os (GPIOs).
For use as input, set LEDn to high-impedance (01) and then read the pin state via the
Input register.
For use as output, connect external pull-up resistor to the pin and size it according to the
DC recommended operating characteristics. LEDn output pin is HIGH when the output is
programmed as high-impedance, and LOW when the output is programmed LOW through
the ‘LED selector’ register. The output can be pulse-width controlled when PWM0 or
PWM1 are used.
6.5 Power-on reset
When power is applied to VDD, an internal Power-On Reset (POR) holds the PCA9551 in
a reset condition until VDDhas reached V
. At that point, the reset condition is released
POR
and the PCA9551 registers are initialized to their default states, all the outputs in the
OFF state. Thereafter, VDD must be lowered below 0.2 V to reset the device.
6.6 External RESET
A reset can be accomplished by holding the RESET pin LOW for a minimum of t
PCA9551 registers and I2C-bus state machine will be held in their default states until the
RESET input is once again HIGH.
w(rst)
. The
This input requires a pull-up resistor to VDD if no active connection is used.
PCA9551_8 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 08 — 31 July 2008 7 of 26
NXP Semiconductors
7. Characteristics of the I2C-bus
The I2C-bus is for 2-way, 2-line communication between different ICs or modules. The two
lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be
connected to a positive supply via a pull-up resistor when connected to the output stages
of a device. Data transfer may be initiated only when the bus is not busy.
7.1 Bit transfer
One data bit is transferredduring each clock pulse. The data on the SDA line must remain
stable during the HIGH period of the clock pulse as changes in the data line at this time
will be interpreted as control signals (see Figure 7).
SDA
SCL
PCA9551
8-bit I2C-bus LED driver with programmable blink rates
Fig 7. Bit transfer
7.1.1 START and STOP conditions
Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW
transition of the data line while the clock is HIGH is defined as the START condition (S). A
LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP
condition (P) (see Figure 8).
SDA
SCL
S
START condition
Fig 8. Definition of START and STOP conditions
7.2 System configuration
data line
stable;
data valid
change
of data
allowed
mba607
SDA
SCL
P
STOP condition
mba608
A device generating a message is a ‘transmitter’; a device receiving is the ‘receiver’. The
device that controls the message is the ‘master’ and the devices which are controlled by
the master are the ‘slaves’ (see Figure 9).
PCA9551_8 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 08 — 31 July 2008 8 of 26
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