NXP PCA9536D Datasheet

PCA9536

4-bit I2C-bus and SMBus I/O port

Rev. 6 — 7 November 2017 Product data sheet

1. General description

The PCA9536 is an 8-pin CMOS device that provides 4 bits of General Purpose paralle l
Input/Output (GPIO) expansion for I
enhance the NXP Semiconductors family of I
provide a simple solution when additional I/O is needed for ACPI power switches,
sensors, push buttons, LEDs, fans, etc.

The PCA9536 consists of a 4-bit Configuration register (input or output selection), 4-bit
Input Port register, 4-bit Output Port register and a 4-bit Polarity Inversion register
(active HIGH or active LOW operation). The system master can enable the I/Os as either
inputs or outputs by writing to the I/O configuration bits. The data for each input or output
is kept in the corresponding Input Port or Output Port register. The polarity of the read
register can be inverted with the Polarity Inversion register. All registers can be read by
the system master.

The power-on reset sets the registers to their default values and initializes the device state
machine.

2

C-bus address is fixed and allows only one device on the same I2C-bus/SMBus.

The I

2. Features and benefits

 4-bit I2C-bus GPIO
 Operating power supply voltage range of 2.3 V to 5.5 V
 5 V tolerant I/Os
 Polarity Inversion register
 Low standby current
 Noise filter on SCL/SDA inputs
 No glitch on power-up
 Internal power-on reset
 4 I/O pins which default to 4 inputs with 100 k internal pull-up resistor
 0 Hz to 400 kHz clock frequency
 ESD protection exceeds 2000 V HBM per JESD22-A114, 200 V MM per

JESD22-A115 and 1000 V CDM per JESD22-C101

 Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA
 Packages offered: SO8, TSSOP8 (MSOP8), HVSON8

2

C-bus/SMBus applications and was developed to

2

C-bus I/O expanders. I/O expanders

NXP Semiconductors

3. Ordering information

PCA9536

4-bit I2C-bus and SMBus I/O port

Table 1. Ordering information

=40C to +85C

T

amb

Type
number

Topside
mark

Package
Name Description Version

PCA9536D PCA9536 SO8 plastic small outline package; 8 leads; body width 3.9 mm SOT96-1

[1]

PCA9536DP 9536 TSSOP8
PCA9536TK 9536 HVSON8 plastic thermal enhanced very thin small outline package; no leads;

plastic thin shrink small outline package; 8 leads; body width 3 m m SOT505-1

SOT908-1

8 terminals; bo dy 3  3  0.85 mm

[1] Also known as MSOP8.

3.1 Ordering options

Table 2. Ordering options

Type number Orderable

PCA9536D PCA9536D,112 SO8 ST ANDARD

PCA9536DP PCA9536DP,118 TSSOP8

PCA9536TK PCA9536TK,118 HVSON8 REEL 13" Q1/T1

Package Packing method Minimum

part number

MARKING * IC'S
TUBE - DSC BULK
PACK

PCA9536D,118 SO8 REEL 13" Q1/T1

*STANDARD MARK
SMD

[1]

REEL 13" Q1/T1
*STANDARD MARK
SMD

*STANDARD MARK
SMD

order quantity

2000 T

2500 T

2500 T

6000 T

Temperature

= 40 C to +85 C

amb

= 40 C to +85 C

amb

= 40 C to +85 C

amb

= 40 C to +85 C

amb

PCA9536 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved.

Product data sheet Rev. 6 — 7 November 2017 2 of 24

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PCA9536

POWER-ON

RESET

002aab851

I2C-BUS/SMBus

CONTROL

INPUT

FILTER

SCL
SDA

V

DD

INPUT/

OUTPUT

PORTS

IO0

V

SS

4-bit

write pulse

read pulse

IO1

IO2

IO3

4. Block diagram

Fig 1. Block diagram of PCA9536

PCA9536

4-bit I2C-bus and SMBus I/O port

All I/Os are set to inputs at reset.

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Product data sheet Rev. 6 — 7 November 2017 3 of 24

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PCA9536D

IO0 V

DD

IO1 SDA
IO2

SCL

V

SS

IO3

002aab849

1
2
3
4

6
5

8
7

PCA9536DP

IO0 V

DD

IO1 SDA
IO2 SCL

V

SS

IO3

002aab850

1
2
3
4

6
5

8
7

002aac459

IO3

SCLIO2

SDAIO1

V

DD

IO0

Transparent top view

54

63

72

81

terminal 1
index area

PCA9536TK

V

SS

5. Pinning information

5.1 Pinning

Fig 2. Pin configuration for SO8 Fig 3. Pin configuration for TSSOP8

PCA9536

4-bit I2C-bus and SMBus I/O port

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Product data sheet Rev. 6 — 7 November 2017 4 of 24

Fig 4. Pin configuration for HVSON8

5.2 Pin description

Table 3. Pin description

Symbol Pin Description

IO0 1 input/output 0
IO1 2 input/output 1
IO2 3 input/output 2
V

SS

IO3 5 input/output 3
SCL 6 serial clock line
SDA 7 serial data line
V

DD

4 supply ground

8 supply voltage

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6. Functional description

Refer to Figure 1 “Block diagram of PCA9536”.

6.1 Registers

6.1.1 Command byte

Table 4. Command byte

Command Protocol Function

0 read byte Input Port register
1 read/write byte Output Port register
2 read/write byte Polarity Inversion register
3 read/write byte Configuration register

The command byte is the first byte to follow the address byte during a write transmission.
It is used as a pointer to determine which of the following registers will be written or read.

PCA9536

4-bit I2C-bus and SMBus I/O port

6.1.2 Register 0 - Input Port register

This register is a read-only port. It reflects the incoming logic levels of the pins, regardless
of whether the pin is defined as an input or an output by Register 3. Writes to this register
have no effect.

The default ‘X’ is determined by the externally applied logic level, normally logic 1 when
no external signal externally applied because of the internal pull-up resistors.

Table 5. Register 0 - Input Port register bit description

Legend: * default value

Bit Symbol Access Value Description

7 I7 read only 1* not used
6 I6 read only 1*
5 I5 read only 1*
4 I4 read only 1*
3 I3 read only X determined by external ly applied logic level
2 I2 read only X
1 I1 read only X
0 I0 read only X

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Product data sheet Rev. 6 — 7 November 2017 5 of 24

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6.1.3 Register 1 - Output Port register

This register reflects the outgoing logic levels of the p ins defined as outpu ts by Register 3.
Bit values in this register have no effect on pins defined as input s. Reads from this register
return the value that is in the flip-flop controlling the output selection, not the actual pin
value.

‘Not used’ bits can be programmed with either logic 0 or logic 1.

Table 6. Register 1 - Output Port register bit description

Legend: * default value

Bit Symbol Access Value Description

7 O7 R 1* not used
6O6 R 1*
5O5 R 1*
4O4 R 1*
3 O3 R 1* reflects outgoing logic levels of pins defined as
2O2 R 1*
1O1 R 1*
0O0 R 1*

PCA9536

4-bit I2C-bus and SMBus I/O port

outputs by Register 3

6.1.4 Register 2 - Polarity Inversion register

This register allows the user to invert the polarity of the Input Port register data. If a bit in
this register is set (written with ‘1’), the corresponding Input Port data is inverted. If a bit in
this register is cleared (written with a ‘0’), the Input Port data polarity is retained.

‘Not used’ bits can be programmed with either logic 0 or logic 1.

Table 7. Register 2 - Polarity Inversion register bit description

Legend: * default value

Bit Symbol Access Value Description

7 N7 R/W 0* not used
6N6 R/W 0*
5N5 R/W 0*
4N4 R/W 0*
3 N3 R/W 0* inverts polarity of Input Port register data
2N2 R/W 0*
1N1 R/W 0*
0N0 R/W 0*

0 = Input Port register data retained (default
value)

1 = Input Port register data inverted

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Product data sheet Rev. 6 — 7 November 2017 6 of 24

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6.1.5 Register 3 - Configuration register

This register configures the directions of the I/O pins. If a bit in this register is set, the
corresponding port pin is enabled as an input with high-impedance output driver. If a bit in
this register is cleared, the corresponding port pin is enabled as an output. At reset, the
I/Os are configured as inputs with a weak pull-up to V

‘Not used’ bits can be programmed with either logic 0 or logic 1.

Table 8. Register 3 - Configuration register bit description

Legend: * default value

Bit Symbol Access Value Description

7 C7 R/W 1* not used
6C6 R/W 1*
5C5 R/W 1*
4C4 R/W 1*
3 C3 R/W 1* configures the directions of the I/O pins
2C2 R/W 1*
1C1 R/W 1*
0C0 R/W 1*

PCA9536

4-bit I2C-bus and SMBus I/O port

.

DD

0 = corresponding port pin enabled as an output
1 = corresponding port pin configured as input

(default value)

6.2 Power-on reset

When power is applied to VDD, an internal Power-On Reset (POR) holds the PCA9536 in
a reset condition until V

has reached V

DD

. At that point, the reset condition is released

POR

and the PCA9536 registers and state machine will initialize to their default states.
Thereafter, V

For a power reset cycle, V

must be lowered below 0.2 V to reset the device.

DD

must be lowered below 0.2 V and then restored to the

DD

operating voltage.

6.3 I/O port

When an I/O is configured as an input, FETs Q1 and Q2 are off, creating a
high-impedance input with a weak pull-up (100 k typical) to V
be raised above V

to a maximum of 5.5 V.

DD

If the I/O is configured as an output, then either Q1 or Q2 is enabled, depending on the
state of the Output Port register . Ca re should be exercised if an external volt age is app lied
to an I/O configured as an output because of the low-impedance paths that exist between
the pin and either V

or VSS.

DD

. The input voltage may

DD

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Product data sheet Rev. 6 — 7 November 2017 7 of 24

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V

DD

IO0 to IO3

output port
register data

configuration
register

DQ

CK Q

data from

shift register

write configuration

pulse

output port
register

DQ

CK

write pulse

polarity inversion
register

DQ

CK

data from

shift register

write polarity

pulse

input port
register

DQ

CK

read pulse

input port
register data

polarity inversion
register data

002aab852

FF

data from

shift register

FF

FF

FF

Q1

100 kΩ

Q2

V

SS

R/W

002aab853

1 0 0 0 0 0 1

fixed

slave address

PCA9536

4-bit I2C-bus and SMBus I/O port

Remark: At power-on reset, all registers return to default values.

Fig 5. Simplified schematic of IO0 to IO3

6.4 Device address

Fig 6. PCA9536 device address

6.5 Bus transactions

Data is transmitted to the PCA9536 registers using the Write mode as shown in Figure 7
and Figure 8

Figure 9

once a command byte has been sent, the register which was addressed will continue to
be accessed by reads until a new command byte has been sent.

. Data is read from the PCA953 6 reg isters usin g the Read mode a s shown in

and Figure 10. These devices do not implement an auto-increment function, so

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Product data sheet Rev. 6 — 7 November 2017 8 of 24