NXP PCA 9517 D Datasheet

PCA9517

Level translating I2C-bus repeater

Rev. 03 — 30 January 2007 Product data sheet

1. General description

The PCA9517 is a CMOS integrated circuit that provides level shifting between low
voltage(down to 0.9 V) and higher voltage(2.7 V to 5.5 V) I2C-bus or SMBus applications.
While retaining all the operating modes and features of the I2C-bus system during the
level shifts, it also permits extension of the I2C-bus by providing bidirectional buffering for
both the data (SDA) and the clock (SCL) lines, thus enabling two buses of 400 pF. Using
the PCA9517 enables the system designer to isolate two halves of a bus for both voltage
and capacitance. The SDA and SCL pins are over voltage tolerant and are
high-impedance when the PCA9517 is unpowered.

The 2.7 V to 5.5 V bus B-side drivers behave much like the drivers on the PCA9515A
device, while the adjustable voltage bus A-side drivers drive more current and eliminate
the static offset voltage. This results in a LOW on the B-side translating into a nearly 0 V
LOW on the A-side which accommodates smaller voltage swings of lower voltage logic.

The static offset design of the B-side PCA9517 I/O drivers prevent them from being
connected to another device that has rise time accelerator including the PCA9510,
PCA9511, PCA9512, PCA9513, PCA9514, PCA9515A, PCA9516A, PCA9517 (B-side),
or PCA9518. The A-side of two or more PCA9517s can be connected together, however,
to allow a star topography with the A-side on the common bus, and the A-side can be
connected directly to any other buffer with static or dynamic offset voltage. Multiple
PCA9517s can be connected in series, A-side to B-side, with no build-up in offset voltage
with only time of flight delays to consider.

2. Features

The PCA9517 driversare not enabledunless V
The EN pin can also be used to turn the drivers on and off under system control. Caution
should be observed to only change the state of the enable pin when the bus is idle.

The output pull-down on the B-side internal buffer LOW is set for approximately 0.5 V,
while the input threshold of the internal buffer is set about 70 mV lower (0.43 V). When the
B-side I/O is driven LOW internally, the LOW is not recognized as a LOW by the input.
This prevents a lock-up condition from occurring. The output pull-down on the A-side
drives a hard LOW and the input level is set at 0.3V
lower LOW level in systems where the low voltage side supply voltage is as low as 0.9 V.

n 2 channel, bidirectional buffer isolates capacitance and allows 400 pF on either side of

the device

n Voltage level translation from 0.9 V to 5.5 V and from 2.7 V to 5.5 V
n Footprint and functional replacement for PCA9515/15A
n I2C-bus and SMBus compatible

is above 0.8 V and VCCis above 2.5 V.

CCA

to accommodate the need for a

CCA

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n Active HIGH repeater enable input
n Open-drain input/outputs
n Lock-up free operation
n Supports arbitration and clock stretching across the repeater
n Accommodates Standard mode and Fast mode I2C-bus devices and multiple masters
n Powered-off high-impedance I2C-bus pins
n A-side operating supply voltage range of 0.9 V to 5.5 V
n B-side operating supply voltage range of 2.7 V to 5.5 V
n 5 V tolerant I2C-bus and enable pins
n 0 Hz to 400 kHz clock frequency (the maximum system operating frequency may be

less than 400 kHz because of the delays added by the repeater).

n ESD protection exceeds 2000 V HBM per JESD22-A114, 150 V MM per

JESD22-A115, and 1000 V CDM per JESD22-C101

n Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA
n Packages offered: SO8 and TSSOP8

3. Ordering information

PCA9517

Level translating I2C-bus repeater

Table 1. Ordering information

T

=−40°C to +85°C

amb

Type number Topside

mark

Package
Name Description Version

PCA9517D PCA9517 SO8 plastic small outline package; 8 leads; body width 3.9 mm SOT96-1

[1]

PCA9517DP 9517 TSSOP8

[1] Also known as MSOP8

plastic thin shrink small outline package; 8 leads; body width 3 mm SOT505-1

4. Functional diagram

SDAA

SCLA

EN

PCA9517

V

CCB

V

pull-up
resistor

CCA

GND

V

CCB

SDAB

SCLB

002aac200

Fig 1. Functional diagram of PCA9517

PCA9517_3 © NXP B.V. 2007. All rights reserved.

Product data sheet Rev. 03 — 30 January 2007 2 of 19

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5. Pinning information

5.1 Pinning

PCA9517

Level translating I2C-bus repeater

1

V

CCA

2

SCLA SCLB

SDAA SDAB

GND EN

3
4

PCA9517D

002aac198

8

V

CCB

7
6
5

Fig 2. Pin configuration for SO8 Fig 3. Pin configuration for TSSOP8

5.2 Pin description

Table 2. Pin description

Symbol Pin Description

V

CCA

SCLA 2 serial clock A-side bus
SDAA 3 serial data A-side bus
GND 4 supply ground (0 V)
EN 5 active HIGH repeater enable input
SDAB 6 serial data B-side bus
SCLB 7 serial clock B-side bus
V

CCB

1 A-side supply voltage (0.9 V to 5.5 V)

8 B-side supply voltage (2.7 V to 5.5 V)

1

V

CCA

2

SCLA SCLB
SDAA SDAB

GND EN

PCA9517DP

3
4

002aac199

8

V

CCB

7
6
5

(MSOP8)

6. Functional description

Refer to Figure 1 “Functional diagram of PCA9517”.
The PCA9517 enables I2C-bus or SMBus translation down to V

without degradation of system performance. The PCA9517 contains two bidirectional
open-drain buffers specifically designed to support up-translation/down-translation
between the low voltage (as low as 0.9 V) and a 3.3 V or 5 V I2C-bus or SMBus. All inputs
and I/Os are overvoltage tolerant to 5.5 V even when the device is unpowered (V
and/or V
drivers turned off until V

= 0 V). The PCA9517 includes a power-up circuit that keeps the output

CCA

is above 2.5 V and the V

CCB

is above 0.8 V. V

CCA

can be applied in any sequence at power-up. After power-up and with the enable (EN)
HIGH, a LOW level on the A-side (below 0.3V

) turns the corresponding B-side driver

CCA

(either SDA or SCL) on and drives the B-side down to about 0.5 V. When the A-side rises
above 0.3V

the B-side pull-down driver is turned off and the external pull-up resistor

CCA

pulls the pin HIGH. When the B-side fallsfirst and goes below 0.3V
turned on and the A-side pulls down to 0 V. The B-side pull-down is not enabled unless
the B-side voltagegoes below 0.4 V. If the B-side low voltage does not go below0.5 V, the
A-side driver will turn off when the B-side voltage is above 0.7V
voltage goes below 0.4 V, the B-side pull-down driver is enabled and the B-side will only

PCA9517_3 © NXP B.V. 2007. All rights reserved.

Product data sheet Rev. 03 — 30 January 2007 3 of 19

as low as 0.9 V

CCA

CCB

the A-side driver is

CCB

. If the B-side low

CCB

CCB

and V

CCA

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PCA9517

Level translating I2C-bus repeater

be able to rise to 0.5 V until the A-side rises above 0.3V
to rise being pulled up by the external pull-up resistor. The V
the 0.3V

reference to the A-side input comparators and for the power good detect

CCA

circuit. The PCA9517 logic and all I/Os are powered by the V

, then the B-side will continue

CCA

is only used to provide

CCA

pin.

CCB

6.1 Enable

The EN pin is active HIGH with an internal pull-up to V
when the repeater is active. This can be used to isolate a badly behaved slave on
power-up until after the system power-up reset. It should never change state during an
I2C-bus operation because disabling during a bus operation will hang the bus and
enabling part way through a bus cycle could confuse the I2C-bus parts being enabled.

The enable pin should only change state when the global bus and the repeater port are in
an idle state to prevent system failures.

and allows the user to select

CCB

6.2 I2C-bus systems

As with the standard I2C-bus system, pull-up resistors are required to provide the logic
HIGH levels on the buffered bus (standard open-collector configuration of the I2C-bus).
The size of these pull-up resistors depends on the system, but each side of the repeater
must have a pull-up resistor. This part designed to work with Standard mode and Fast
mode I2C-bus devices in addition to SMBus devices.Standard mode I2C-bus devices only
specify 3 mA output drive; this limits the termination current to 3 mA in a generic I2C-bus
system where Standard mode devices and multiple masters are possible. Under certain
conditions higher termination currents can be used.

Please see Application Note

AN255, I2C/SMBus Repeaters, Hubs and Expanders

for
additional information on sizing resistors and precautions when using more than one
PCA9517 in a system or using the PCA9517 in conjunction with other bus buffers.

PCA9517_3 © NXP B.V. 2007. All rights reserved.

Product data sheet Rev. 03 — 30 January 2007 4 of 19

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7. Application design-in information

A typical application is shown in Figure 4. In this example, the system master is running
on a 3.3 V I2C-bus while the slave is connected to a 1.2 V bus. Both busesrun at 400 kHz.
Master devices can be placed on either bus.

PCA9517

Level translating I2C-bus repeater

SDA

SCL

BUS

MASTER

400 kHz

3.3 V

10 kΩ

10 kΩ

CCB

PCA9517

V

CCA

V

SDAB SDAA
SCLB SCLA

EN

bus B bus A

10 kΩ

1.2 V

10 kΩ

SDA
SCL

SLAVE

400 kHz

002aac201

Fig 4. Typical application

The PCA9517 is 5 V tolerant, so it does not require any additional circuitry to translate
between 0.9 V to 5.5 V bus voltages and 2.7 V to 5.5 V bus voltages.

When the A-side of the PCA9517 is pulled LOW by a driver on the I2C-bus, a comparator
detects the falling edge when it goes below 0.3V

and causes the internal driver on the

CCA

B-side to turn on, causing the B-side to pull down to about 0.5 V. When the B-side of the
PCA9517 falls, first a CMOS hysteresis type input detects the falling edge and causes the
internal driver on the A-side to turn on and pull the A-side pin down to ground. In order to
illustrate what would be seen in a typical application, refer to Figure 8 and Figure 9. If the
bus master in Figure 4 were to write to the slave through the PCA9517, waveforms shown
in Figure 8 would be observed on the A bus. This looks like a normal I2C-bus transmission
except that the HIGH level may be as low as 0.9 V, and the turn on and turn off of the
acknowledge signals are slightly delayed.

On the B bus side of the PCA9517, the clock and data lines would have a positive offset
from ground equal to the VOL of the PCA9517. After the 8th clock pulse, the data line will
be pulled to the VOL of the slave device which is very close to ground in this example. At
the end of the acknowledge, the level rises only to the LOW level set by the driver in the
PCA9517 for a short delay while the A bus side rises above 0.3V

then it continues

CCA

HIGH. It is important to note that any arbitration or clock stretching events require that the
LOW level on the B bus side at the input of the PCA9517 (VIL) be at or below 0.4 V to be
recognized by the PCA9517 and then transmitted to the A bus side.

Multiple PCA9517 A-sidescan be connected in a star configuration (Figure 5), allowing all
nodes to communicate with each other.

Multiple PCA9517s can be connected in series (Figure 6) as long as the A-side is
connected to the B-side. I2C-bus slave devices can be connected to any of the bus
segments. The number of devices that can be connected in series is limited by repeater
delay/time-of-flight considerations on the maximum bus speed requirements.

PCA9517_3 © NXP B.V. 2007. All rights reserved.

Product data sheet Rev. 03 — 30 January 2007 5 of 19

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PCA9517

Level translating I2C-bus repeater

SDA

SCL

BUS

MASTER

10 kΩ

V

CCA

10 kΩ

CCA

V

CCB

V

SDAA SDAB
SCLA SCLB

PCA9517

EN

CCA

V

CCB

V

SDAA SDAB
SCLA SCLB

PCA9517

EN

CCA

V

CCB

V

SDAA SDAB
SCLA SCLB

10 kΩ

10 kΩ

10 kΩ

V

CCB

10 kΩ

SDA
SCL

SLAVE

400 kHz

10 kΩ

SDA
SCL

SLAVE

400 kHz

10 kΩ

SDA
SCL

Fig 5. Typical star application

10 kΩ 10 kΩ

SDA

SCL

BUS

MASTER

SDAA SDAB
SCLA SCLB

PCA9517

EN

Fig 6. Typical series application

PCA9517

EN

V

CC

10 kΩ 10 kΩ 10 kΩ 10 kΩ 10 kΩ 10 kΩ

SDAA SDAB
SCLA SCLB

PCA9517

EN

SDAA SDAB
SCLA SCLB

PCA9517

EN

SLAVE

400 kHz

002aac202

SDA
SCL

SLAVE

400 kHz

002aac203

PCA9517_3 © NXP B.V. 2007. All rights reserved.

Product data sheet Rev. 03 — 30 January 2007 6 of 19