NXP PCA9420 data sheet

PCA9420

Power management IC for low-power microcontroller
applications

Rev. 2 — 26 January 2021 Product data sheet

1 General description

The PCA9420 is a highly-integrated Power Management IC (PMIC), targeted to provide
a full power management solution for low power microcontroller applications or other
similar applications.

The device consists of a linear battery charger capable of charging up to 315 mA current.
It has an I2C programmable Constant Current (CC) and Constant Voltage (CV) values
for flexible configuration. Various built-in protection features such as input overvoltage
protection, overcurrent protection, thermal protection, etc. are also provided for safe
battery charging. It also features JEITA compliant charging.

The device also integrates two step-down (buck) DC/DC converters which have I2C
programmable output voltage. Both buck regulators have integrated high-side and low­side switches and related control circuitry, to minimize the external component counts;
a Pulse-Frequency Modulation (PFM) approach is utilized to achieve better efficiency
under light load condition. Other protection features such as overcurrent protection,
under-voltage lockout (UVLO), etc. are also provided. By default, the input for these
regulators is powered by either VIN or VBAT, whichever is greater.

In addition, two on-chip LDO regulators are provided to power up various voltage rails in
the system.

Other features such as FM+ I2C-bus interface, chip enable, interrupt signal, etc. are also
provided.

The chip is offered in 2.09 mm x 2.09 mm, 5 x 5 bump, 0.4 mm pitch WLCSP package;
and 3 mm x 3 mm, 24-pin QFN package.

2 Features and Benefits

• Linear battery charger for charging single cell li-ion battery
– 20 V tolerance on VIN pin
– Programmable input OVP (5.5 V or 6 V)
– Programmable constant current (up to 315 mA) and pre-charge low voltage current

threshold

– Programmable constant voltage regulation
– Programmable automatic recharge voltage and termination current threshold
– Built-in protection features such as input OVP, battery SCP, thermal protection
– JEITA compliant
– Battery attached detection
– Over-temperature protection

NXP Semiconductors

• Two step-down DC/DC converters
– Very low quiescent current
– Programmable output voltage
– SW1: core buck converter, 0.5 V~1.5 V output, 25 mV/step, and a fixed 1.8 V, up to

– SW2: system buck converter, 1.5 V~2.1 V/2.7 V~3.3 V output, 25 mV/step, up to

– Low power mode for extra power saving

• Two LDOs
– Programmable output voltage regulation
– LDO1: always-on LDO, 1.70 V~1.90 V output, 25 mV/step, up to 1 mA
– LDO2: system LDO, 1.5 V~2.1 V/2.7 V~3.3 V output, 25 mV/step, up to 250 mA

• 1 MHz I2C-bus slave interface

• -40 °C ~ +85 °C ambient temperature range

• Offered in 5 x 5 bump-array WLCSP and 24-pin QFN package

3 Applications

PCA9420

Power management IC for low-power microcontroller applications

250 mA

500 mA

• Low power microcontroller application

4 Ordering information

Table 1. Ordering information

PackageType number Topside

marking

PCA9420BS 420 HVQFN24 plastic thermal enhanced very thin quad flat package; no

PCA9420UK 9420 WLCSP25 wafer level chip-scale package, 25 terminals, 0.4 mm

4.1 Ordering options

Table 2. Ordering options

Type number Orderable part

number

PCA9420BS PCA9420BSAZ HVQFN24 REEL 7" Q2 NDP 1400 -40°C to +85°C

PCA9420UK PCA9420UKZ WLCSP25 REEL 7" Q1 DP CHIPS 3000 -40°C to +85°C

Name Description Version

SOT905-1

leads; 24 terminals; body 3 x 3 x 0.85 mm

SOT1401-4

pitch, 2.09 mm x 2.09 mm x 0.525 mm body

Package Packing method Minimum order

quantity

Temperature range

PCA9420 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2021. All rights reserved.

Product data sheet Rev. 2 — 26 January 2021

2 / 82

NXP Semiconductors

aaa-033067

Max 315mA

Linear Charger

O

VP

Detection

(5.5V default or

6V over I2C

)

PCA9420

Main

Contro

l

Blo

cks

VIN

ASY

S

VBA

T

1-Cel

l

Li-Io

n

Battery

+ (VBAT

)

- (GND)

STEP-DOWN

CONVERTER 1

250mA

(0.5V-1.5V

in 25mV steps

& fixed 1.8V)

STEP-DOWN

CONVERTER 2

500mA
(1.5V-2.1V in
25mV steps

)

(or 2.7V-3.3V

in 25mV steps

)

PSYS1

E

N

4.7

µF/

1

0V

PGND1

LX1

ASY

S

2.2µH

SW1_OU

T

50Ω

PSYS2

PGND2

LX2

2.2µH

SW2_OU

T

E

N

I

2

C

I2C

1µF/
1

0V

50Ω

VDDCORE

RT600

LDO

1

1

mA

(1.7V-1.9V

in 25mV steps

)

LDO

2

250mA
(1.5V-2.1V in
25mV steps)
(or 2.7V-3.3V

in 25mV steps

)

LDO1_OUT

50Ω

LDO2_OUT

50Ω

I

N

ASY

S

VBA

T_BKU

P

I

N

ASY

S

VIN

_

UVLO

T

herma

l

shutdow

n

O

FF

O

N

Debounc

e

Filter

(200µs)

On-Ke

y

1MΩ

+

-

2.5V
or VBAT

Long-Key
Debounce

Filter

(4s, 8s(default

)

,12s,16s

)

2.2µF/
10V

2.9V,3.1V(default)

,

3.3V,3.5

V

200m

V

ASYS_

Pre

-

warning

+

-

3.3V,3.4V

,

3.5V (default),3.6

V

100m

V

ASYS_

UVL

O

+

-

100mV

AGND1AGND

2

1µF/
1

0V

10µF/

6.3

V

2.2µF/
1

0V

10µF/

6.3

V

VBA

T

0.47µF

/

6.3

V

Coin

battery

O

N

Power-o

n

from off o

r

ship-mod

e

2.4V,2.5V, 2.6V,

2.7V (default

)

Recycle

Power rail

s

VBAT

_

BKUP_

UVLO

+

-

1.9

V

100m

V

Watchdog
(disable, 16s,
32s, 64s)

SCL

SDA

TS

N

TC

N

TC

C

ontrol

Block

Up to 1MHz

I2C Interface

VDD_AO1V8

Optio

n

ADC

MOD

E

SELECTION

MODESEL0

MODESEL1

AGND3

1µF/

6.3

V

2.2µF

/

6.3

V

Power-Good

&

Rese

t

SYSRS

Tn

Interrupts

INTB

R

1

R1=R2=20kΩ to 220kΩ

R

2

PMIC_IRQN
(VDD_AO1V8)

+

-

20°

C

T

DIE

Thermal
Regulatio

n

(80°C t

o

115°C

)

ASY

S

3-bit

programmable

(95°

C to 125°C

in 5°

C steps)

T

herma

l

warni

ng

+

-

20°

C

T

DIE

2-bit

programmabl

e

(75°C to 90°C

in 5°C steps)

50µA 5

µA

25-Bump WLCSP, 0.4mm pitch,

2.09mm x 2.09mm

ASY

S

E

N

I

2

C

E

N

I2C

E

N

I2C

SHI

P

MOD

E

ENTE

R

O

R

SHIP_EN_x=1

EXI

T

Valid VIN

Valid VIN

SHIP_WKUP_CFG=

0

Battery

absence

detection

E

N

I2C

1
2

A programme

d

I

CHG_CC

X

Power-down

sequence

PWR_DN_EN=

1

β selction

3-bit programmabl

e

From 3434k to 4750

k

Add 1.2V
offset

I

2

C

Add 1.2

V

offse

t

Default:1.

0V

Default:1.

8V

VDDIO_1,2,3,
and/or

4

Always-on

1.8V

Default:

3.3

V

Reverse
Blocking

Note: All directions for the arrows in the schematic are
made from the PCA9420 perspective.

Short on PCB

i.MXRT

*

RT60

0

i.MXRT

*

VDD1V8 and
other 1.8V powe

r

PMIC_I2C_SC

L

(VDDIO_1)

PMIC_I2C_SD

A

(VDDIO_1)

VDD_AO1V8

VDDIO_1,2,3,

and/or

4

USB1_VDD3V3

and other

3V powe

r

RESETN
(VDD_AO1V8)

PMIC_MODE0
(VDD_AO1V8)

PMIC_MODE1
(VDD_AO1V8)

Option: can be remove if an
internal pull-up R is availabl

e

on i.MXRT* device

VDDIO_1

MODESEL

1

MODESEL0

EN_MODE_SEL_BY_PIN_x=

1

Output Voltage Settin

g

LOW (0)

HIGH (1)

LOW (0)

LOW (0)

HIGH (1)LOW (0)

HIGH (1)HIGH (1

)

Mode Setting

0

Mode Setting

1

Mode Setting

2

Mode Setting

3

(x can be 0, 1, 2 or 3)

Can be connected to any AD

C

Regulator

Default (V)*Output Range

BUCK1

1.0

(MTP

)

0.5V to 1.5V and fixed 1.8

V

BUCK2

LDO1

LDO2

1.5V to 2.1V or 2.7V to 3.

3V

* : Regardless of mode setting

1.7V to 1.9V

1.5V to 2.1V or 2.7V to 3.

3V

Resolution

25mV

Max Curren

t

250mA

25mV

25mV

25mV

500mA

1m

A

250mA

Linear charger: 0mA to 315mA in 5mA steps for charge curre

nt

Input Current Limit (typical): 85mA, 255mA, 425mA, 595mA, 765mA, 935mA,

1105mA, or disable

1.8

(MTP

)

1.8

(MTP

)

3.3

(MTP

)

If VIN is greater than 6V, the

voltage rating on the capacitor of

2.2µF/10V shall be changed to a
higher voltage than a maximum

voltage in applications.

VIN ≤ 6V

5 Simplified block diagram

PCA9420

Power management IC for low-power microcontroller applications

PCA9420 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2021. All rights reserved.

Product data sheet Rev. 2 — 26 January 2021

Figure 1. Simplified block diagram

3 / 82

NXP Semiconductors

aaa-033076

17

Transparent top view

Exposed pad

2

4

P

G

N

D

2

232

2

201

9

1

8

V

B

A

T

2

1

terminal 1
index area

PCA9420BS

15

14

13

16

3

1

4

5

2

SDA 6

7

8

10

11

LDO1_OUT 12

9

SCL

ON

SW2_OUT

PSYS2

LX2

SYSRSTn

INTB

AGND1

MODESEL1

MODESEL0

VBAT_BKUP

TS

LDO2_OUT

VIN

ASYS

S

W

1

_

O

U

T

P

S

Y

S

1

A

G

N

D

2

LX

1

P

G

N

D

1

aaa-033077

A

SW2_

O

UT

AGND

2

AGN

D

1

T

S

INT

B

SYS

RSTn

B

C

1

2

3

4

VBAT_

BKUP

ASYS

O

N

LDO

2

_OU

T

VI

N

SW1_

O

UT

PS

YS

2

LX2

5

S

CL

PGND

1

LX1

VBA

T

PSYS

1

PGND

2

D

MODE

SEL

1

AGND

3

LDO

1

_OU

T

E

pin A1

index area

MOD

E

SEL0

S

DA

6 Pinning information

6.1 Pinning

PCA9420

Power management IC for low-power microcontroller applications

Figure 2. PCA9420BS pinout (HVQFN24) – top view

Figure 3. PCA9420UK pinout (WLCSP25) – top view

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Product data sheet Rev. 2 — 26 January 2021

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NXP Semiconductors

PCA9420

Power management IC for low-power microcontroller applications

6.2 Pin description

Table 3. Pin Description

PinSymbol

HVQFN24 WLCSP25

INPUT SUPPLY

VIN 16 C1 P Input supply voltage. Bypass with a 2.2µF/10V ceramic

ASYS 17 B1 P Bypass output of VIN and input supply voltage for LDO2,

VBAT_BKUP 13 D2 P Backup battery input voltage. LDO1 is powered by the

LINEAR CHARGER

VBAT 18 A1 P Battery (+) connection point. A typical 1µF/10V decoupling

TS 14 C2 I Battery temperature sensing pin. An external thermistor is

BUCK1 STEP_DOWN CONVERTER (SW1)

PSYS1 20 A2 P Input supply for SW1. Bypass with a typical 1µF/10V

LX1 22 A3 P Switching node for SW1. Connect to a 2.2µH inductor.

SW1_OUT 19 B2 I Feedback pin. Bypass with a 10µF/6.3V ceramic capacitor.

PGND1 23 A4 P Power ground for buck 1 (SW1). Connect ground nodes of

BUCK2 STEP_DOWN CONVERTER (SW2)

PSYS2 2 C5 P Input supply for SW2. Bypass with a typical 2.2µF/10V

LX2 1 B5 P Switching node for SW2. Connect to a 2.2µH inductor.

SW2_OUT 3 B4 I Feedback pin. Bypass with a 10µF/6.3V ceramic capacitor.

PGND2 24 A5 P Power ground for buck 2 (SW2). Connect ground nodes of

LOW_DROPOUT REGULATORS (LDO1 and LDO2)

LDO1_OUT 12 E1 P LDO1 output. It is always-ON supply. The input supply is a

Pin Type Description

capacitor. If VIN is greater than 6V, the voltage rating shall
be changed to a higher voltage than the maximum voltage
in applications.

connect with a typical 4.7µF or 10µF/10V decoupling
capacitor.

greater of ASYS or VAT_BKUP. If a back-up battery with a
coin cell is not connected, connect the pin to VBAT power
domain. Connect with a typical 0.47µF/6.3V decoupling
capacitor.

capacitor should be connected between VBAT to system
ground.

connected between TS pin and system ground.

ceramic capacitor. Connect to ASYS power domain as short
as possible in the system.

two bypass capacitors for PSYS1 and SW1_OUT as close
to PGND1 pin as possible in the system.

ceramic capacitor. Connect to ASYS power domain as short
as possible in the system.

two bypass capacitors for PSYS2 and SW2_OUT as close
to PGND2 pin as possible in the system.

higher voltage between ASYS and VBAT_BKUP. Bypass
with a 1µF/6.3V ceramic capacitor.

PCA9420 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2021. All rights reserved.

Product data sheet Rev. 2 — 26 January 2021

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NXP Semiconductors

PCA9420

Power management IC for low-power microcontroller applications

Table 3. Pin Description...continued

PinSymbol

HVQFN24 WLCSP25

LDO2_OUT 15 D1 P LDO2 output. The input supply is ASYS. Bypass with a

LOGIC INPUTS

ON 4 C4 I

MODESEL0 7 E4 I Mode selection input pin #1

MODESEL1 8 E3 I Mode selection input pin #2

LOGIC OUTPUTS

INTB 10 D4 O

SYSRSTn 11 D3 O

SERIAL I2C INTERFACE

SCL 5 D5 I

SDA 6 E5 I/O

DEVICE GROUND

AGND1 9 B3 P

AGND2 21 C3 P

AGND3 E2 P

Exposed
Pad

Pin Type Description

2.2µF/6.3V ceramic capacitor.

ON Pin with an internal pull-up resistor, 1MΩ typ, to either

2.5V or VBAT. Refer to Section 8.3 for more details.

Interrupt output, Open-drain type. Place a pull-up resistor
from 20kΩ to 220kΩ to a system I/O supply rail.

Reset output for external MCU, Open-drain type. Place a
pull-up resistor from 20kΩ to 220kΩ to a system I/O supply
rail.

I2C Interface clock pin. Place a pull-up resistor between

2.2kΩ and 10kΩ to a system I/O supply rail.

I2C Interface data pin. Place a pull-up resistor between

2.2kΩ and 10kΩ to a system I/O supply rail.

Analog ground. It shall be connected to system ground
through a via. Do not connect AGND1 and AGND2 to
PGND1 or PGND2 on the top PCB layer in the system.

Exposed pad. Connect to system ground

P = Power, I = Input, I/O = input/output

PCA9420 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2021. All rights reserved.

Product data sheet Rev. 2 — 26 January 2021

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NXP Semiconductors

aaa-033078

PCA9420

VIN

ASYS

VBAT

1-Cell

Li-Ion

Battery

+ (VBAT)

- (GND)

PSYS1

4.7µF/
10V

PGND1

LX1

2.2µH

SW1_OUT

PSYS2

PGND2

LX2

2.2µH

SW2_OUT

1µF/
10V

VDDCORE

LDO1_OUT

LDO2_OUT

VBAT_BKUP

OFF

ON

On-Key

button

2.2µF/
10V

AGND1 AGND2

1µF/
10V

10µF/

6.3V

2.2µF/
10V

10µF/

6.3V

VBAT

0.47µF/

6.3V

Coin

battery

ON

SCL

SDA

TS

NTC

VDD_AO1V8

Option

ADC

MODESEL0

MODESEL1

AGND3

1µF/

6.3V

2.2µF/

6.3V

SYSRSTn

INTB

R1

R1=R2=100-220kΩ

R2

PMIC_IRQN
(VDD_AO1V8)

25-Bump WLCSP, 0.4m m pi tch,

2.1mm x 2. 1mm

ASYS

Default:1.0V

Default:1.8V

VDDIO_1,2,3,
and/or 4

Always-on

1.8V

Default:

3.3V

Note: All dir ections f or t he arrows in the
schematic are made from the PCA9420
perspecti ve.

Short on PCB

i.MXRT

RT5xx
RT6xx

VDD1V8 and

other 1.8V power

PMIC_I2C_SCL

(VDDIO_1)

PMIC_I2C _SDA
(VDDIO_1)

VDD_AO1V8

VDDIO_1,2,3,

and/or 4

USB1_VDD3V3

and other

3V.3V power

RESETN
(VDD_AO1V8)

PMIC_MO DE0

(VDD_AO1V8)

PMIC_MO DE1
(VDD_AO1V8)

Option: can be removed if an
internal pull-up R is available
on i.MXRT* device

VDDIO_1

Input Supply

VBUS

GND

C1

C4

D2

E1

D1

E4

E3

B3 C3 E2

C2

D3

D4

E5

D5

B4

B5

A5

C5

B2

A3

A4

A2

B1

A1

If a coil cell is not used, tie

with the VBAT power domain

If the pin is not used,
leave the pin open

If the pin is not used,

leave the pin open

If the pin is not used,

leave the pin open

MODESEL1

MODESEL0

EN_MODE_SEL_BY_PIN_x=1

Output Voltage Setting

LOW (0)

HIGH (1)

LOW (0)

LOW (0)

HIGH (1) LOW (0)

HIGH (1) HIGH (1)

Mode Setting 0

Mode Setting 1

Mode Setting 2

Mode Setting 3

(x can be 0, 1, 2 or 3)

MODESEL1

MODESEL0

EN_MODE_SEL_BY_PIN_x=1

Output Voltage Setting

LOW (0)

HIGH (1)

LOW (0)

LOW (0)

HIGH (1) LOW (0)

HIGH (1) HIGH (1)

Mode Setting 0

Mode Setting 1

Mode Setting 2

Mode Setting 3

(x can be 0, 1, 2 or 3)

Can be connected to any ADC

Regulator

Default (V)

*

Output Range

BUCK1

1.0

(MTP)

0.5V to 1.5V and fixed 1.8V

BUCK2

LDO1

LDO2

1.5V to 2.1V or 2.7V to 3.3V

* : Regardless of mode setting

1.7V to 1.9V

1.5V to 2.1V or 2.7V to 3.3V

Resolution

25mV

Max Current

250mA

25mV

25mV

25mV

500mA

1mA

250mA

Linear charger: 0mA to 315mA in 5mA steps for charge current

Input Current Limit (typical): 85mA, 255mA, 425mA, 595mA, 765mA, 935mA,

1105mA, or disable

1.8

(MTP)

1.8

(MTP)

3.3

(MTP)

Regulator

Default (V)

*

Output Range

BUCK1

1.0

(MTP)

0.5V to 1.5V and fixed 1.8V

BUCK2

LDO1

LDO2

1.5V to 2.1V or 2.7V to 3.3V

* : Regardless of mode setting

1.7V to 1.9V

1.5V to 2.1V or 2.7V to 3.3V

Resolution

25mV

Max Current

250mA

25mV

25mV

25mV

500mA

1mA

250mA

Linear charger: 0mA to 315mA in 5mA steps for charge current

1.8

(MTP)

1.8

(MTP)

3.3

(MTP)

VIN ≤ 6V

If VIN is greater than 6V, the voltage
rating on the capacitor of 2.2µF/10V
shall be changed to a higher
voltage than a maximum voltage
in applications.

i.MXRT

RT5xx

RT6xx

7 System configuration diagram

Power management IC for low-power microcontroller applications

PCA9420

Figure 4. System configuration diagram; i.MXRT series

PCA9420 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2021. All rights reserved.

Product data sheet Rev. 2 — 26 January 2021

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NXP Semiconductors

aaa-033079

PCA9420

K4 Family MC

U

LDO

2_OUT

(Syst

em LDO)

LDO

1_OUT

(

AO_LDO)

SW1_OUT

(

Cor

e Buck)

LX1

SW2_OUT

(SY

S Buck)

LX2

SYSRSTn

M

ODESEL0

M

ODESEL1

ON

SCL

SDA

INTB

V

IN

ASYS
PSYS1
PSYS2

VBAT_

BKU

P

Battery

Pac

k

VBAT
T

S

PGND

AGND1/2

/3

LPI2Cn_S

CL

LPI2Cn_SD

A

GPIO_n

RESET_n

VDD_BA

T

VDD_IO

SPM_LPREQ

VDD_COR

E

VDD_SY

S

RTC_WAKEUP_n

T

PCA9420

Power management IC for low-power microcontroller applications

Figure 5. System configuration diagram; K4-family MCU

PCA9420 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2021. All rights reserved.

Product data sheet Rev. 2 — 26 January 2021

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NXP Semiconductors

8 Functional description

8.1 ASYS

The ASYS pin serves as the input power pin for SW1, SW2 and LDO2. Internally by
default it’s powered by either VIN or VBAT, whichever is greater. The internal ASYS input
selection circuit ensures a seamless transition when its input source changes from VIN to
VBAT, or vice versa.

Through I2C register setting selection (SYS_INPUT_SEL [1:0]), the user also has the
option to choose the ASYS input source. However, upon power cycling and/or chip reset,
the ASYS input source goes back to the default setting (option 1 below).

SYS_INPUT_SEL [1:0]

1. 2b’00: From either VBAT or VIN, whichever is greater (default setting);

2. 2b’01: From VBAT only;

3. 2b’10: From VIN only;

4. 2b’11: Disconnect from VBAT or VIN (not a normal operation condition, for test
purposes only).

PCA9420

Power management IC for low-power microcontroller applications

An I2C programmable pre-warning ASYS voltage threshold (ASYS_PRE_WARNING
[1:0]) can also be used to indicate when ASYS voltage drops below the ASYS pre­warning threshold voltage, which triggers an interrupt event.

If any peripheral regulators are connected to ASYS node, the ASYS node follows a VIN
voltage up to a programmed OVP threshold (either 5.5V or 6V) with a various voltage
difference depending on a load current.

8.2 VBAT_BKUP (back-up battery input)

Internally, the input power source for LDO1 is provided by either VBAT_BKUP or ASYS,
whichever is greater. When a coin cell battery (or similar battery) is used in the system
as a backup battery, it can be connected to VBAT_BKUP; thus the LDO1 is powered
by either ASYS or the backup battery. When no such backup battery is used, the
VBAT_BKUP pin should always be connected to VBAT.

8.3 ON

The ON pin has the following functions implemented:

1. ON pin has internal 1MΩ pull-up resistor to either 2.5V or VBAT depending on VBAT
voltage. If VBAT is less than 3V, ON is pulled up to 2.5V and if VBAT is greater than
3V, it is pulled to VBAT.
Falling edge (filtered after deglitching time, 200µs typ), active-low signal enables the
chip. If the chip stays in ship mode before applying ON falling edge, upon the filtered
falling edge of the ON pin, the chip exits ship mode to start up into Mode Setting 0.

If the device is already in the middle of power-up or power-down sequence, the falling
edge applied on the ON pin is ignored by the chip.

1. Long press (duration time, 4s, 8s, 12s or 16s, is programmable via I2C,
ON_GLT_LONG [1:0]). If the logic low signal is applied continuously over a
programmed duration, the chip gets reset and recycles all power rails to their default
values

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2. Also, in mode setting 0, 1, 2, or 3, an I2C bit “ON_CFG_x“ (x=0, 1, 2, or 3) is reserved;

3. The filtered falling edge on the ON pin resets the bit of EN_MODE_SEL_BY_PIN_A to

8.4 TS

With the temperature sensing pin, the external thermistor (NTC) is connected between
the TS pin and ground. The thermistor may be included in the battery pack to monitor the
battery pack temperature, or it may be an additional component user chooses to have on
the board level to monitor the temperature at a chosen area.

The voltage at TS pin is monitored, and the user can enable the feature through I2C-bus
interface (NTC_EN) to implement JEITA compliant charging at a safe temperature. Per
JEITA standard, there are four temperature threshold settings:

1. Cold threshold (T1, 0°C as example)

2. Cool threshold (T2, 10°C as example)

3. Warm threshold (T3, 45°C as example)

4. Hot threshold (T4, 60°C as example)

PCA9420

Power management IC for low-power microcontroller applications

by setting its value to either 0 or 1, the user can configure whether a mode setting
switches back to Mode Setting 0 or not, upon a valid falling edge detected from “ON”
pin. Refer to ON_CFG_x bit description in the relation registers for more details.

the default value, 0, at 22h register.

Each of the above temperature thresholds represents a voltage threshold. When the
monitored temperature, T, falls into a different temperature zone, the charger should
adjust the charging method accordingly:

1. T > T4 or T < T1, i.e., when the temperature is in a “cold” or “hot” zone, charging is
suspended, as well as the safety timer;

2. T1 < T < T2, charging current is reduced by 50% of the programmed current level;

3. T2 < T < T3, normal charging;

4. T3 < T < T4, the CV mode regulating voltage should be set as VBAT_REG [5:0] –
ΔVBAT_REG(HOT), 140mV typical

To disable this function, set NTC_EN to “0”.

8.5 Mode setting

When the MCU operates in different modes such as overdrive run mode or low power
mode, it may require the power supply to operate in different settings accordingly (for
example, enable/disable of each rail, output voltage of each rail, etc.) to achieve a better
performance and efficiency.

On the PCA9420, there are four modes of registers representing Mode Setting A/B/C/
D to accommodate such requirements from MCU, where Mode Setting A is the default
mode setting (i.e., the initial mode setting upon initial power up). Depending on the user’s
preference, switching among different mode settings can be controlled by either the
external signal (ON pin), external pins (MODESEL0/1) or I2C.

Within each mode setting, the user can program the follow parameters providing great
flexibility to accommodate different MCU operation modes:

1. Enable/disable of the four output voltage rails

2. Voltage setting of the four output voltage rails

3. Ship mode enable/disable

4. Watchdog timer setting

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5. Mode control selection (EN_MODE_SEL_BY_PIN_x, x=0, 1, 2, or 3)

EN_MODE_SEL_BY_PIN_x = 0: under current mode setting, mode setting switch is
controlled by internal I2C register bits MODE0_I2C and/or MODE1_I2C only; signal
applied on external MODESEL0/MODESEL1 pins is ignored.

EN_MODE_SEL_BY_PIN_x = 1: under current mode setting, mode setting switch is
controlled by signal applied on external MODESEL0 and/or MODESEL1 pins only, not by
internal I2C register bits MODE0_I2C and MODE1_I2C.

1. Mode setting switches back to Mode Setting A triggered by ON pin falling edge. Refer

In the event of switching from one mode setting (initial mode setting) to another mode
setting (target mode setting):

1. If one output rail remains enabled in both initial mode setting and target mode setting

2. If there are output rails which may be enabled or disabled from initial mode setting to

PCA9420

Power management IC for low-power microcontroller applications

to register description for “ON_CFG_x” bit for more details.

but with different output voltage in each setting, such voltage transition should happen
when the mode setting switch command (from either internal I2C setting or external
signal) is received;

target mode setting, then always make sure these rails which change from disabled
to enabled take higher priority over rails which change from enabled to disabled, i.e.,
make sure all the rails change from disabled status to enabled status (reaches 90% of
its target value) first, and then start to disable these rails, changing from enable status
to disable status.

8.6 Mode selection by external pins (MODESEL0, MODESEL1)

Up on initial power-up, PCA9420 enters its default setting (Mode Setting

0). While operating under Mode Setting 0, by default the I2C register bit,

EN_MODE_SEL_BY_PINEN_MODE_SEL_BY_PIN_0, is set to “0”, and the external
signal applied on the MODESEL0 and MODESEL1 pins are ignored. Only when the user
sets EN_MODE_SEL_BY_PINEN_MODE_SEL_BY_PIN_0 to “1”, can the mode control
on the chip be programmed via MODESEL0 and MODESEL1 pin signal settings.

Table 4. Mode Selection by external pins (MODESEL0, MODESEL1)

MODESEL1 pin voltage level MODESEL0 pin voltage level All Settings from

LOW (0) LOW (0) Mode Setting 0

LOW (0) HIGH (1) Mode Setting 1

HIGH (1) LOW (0) Mode Setting 2

HIGH (1) HIGH (1) Mode Setting 3

8.7 SYSRSTn

The SYSRSTn is implemented as an open-drain output signal. It is used as an output of
“power-good” indication as well as to reset the microcontroller system.

The SYSRSTn signal is held from high to low under one of following conditions:

1. When any of the enabled voltage rail output voltage drops below 90% (typ) of its
target value.

2. When any of the enabled voltage rail output voltage goes above 110% (typ) of its
target value

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Product data sheet Rev. 2 — 26 January 2021

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NXP Semiconductors

If any of the voltage rail is disabled by the user (by setting the corresponding enable
bit in I2C register in each mode setting, i.e., LDO1_EN_x, LDO2_EN_x, SW1_EN_x,
SW2_EN_x), the SYSRSTn signal should NOT assert (stays high) under such scenario.

This also applies during the power-up/power-down sequence events, i.e., during power­up or power-down event, the SYSRSTn signal should assert when any of the enabled rail
has not reaches the 90% ~ 110% of its target value. In other words, the SYSRSTn = 0
(low) needs to remain at such state until all enabled rails reach 90% of the target values.

1. When a programmed watchdog timer expires (only when watchdog timer is enabled)

Once the condition that caused the SYSRSTn signal to go low is removed, then the
SYSRSTn should refresh accordingly.

Meanwhile, during the voltage change on-the-fly, this could be caused by:

1. Mode setting remains the same, but the user chooses to change one or some of the

2. Mode setting changes by setting different values on MODESEL0/MODESEL1 pins or

In such case, the SYSRSTn signal does NOT assert when any of the enabled voltage
rail output voltage is in the middle of the transition from initial output voltage level to
target level.

PCA9420

Power management IC for low-power microcontroller applications

enabled output rail voltage by programming its output voltage I2C register setting

MODE0_I2C/MODE1_I2C bits, and it causes one or some of the output rail voltage
change

8.8 SHIP mode

PCA9420 features a “SHIP mode”, in which the chip provides the lowest quiescent
consumption.

To enter the SHIP mode, set the bit of SHIP_EN_x (x can be 0, 1, 2 or 3) in each Mode
register to 1. Once the bit is set to 1, the ship mode immediately takes place regardless
of any operation under any mode setting. It means that the SHIP mode has a higher
priority over any conditions and operations.

Upon request to enter the ship mode while the device is running in active mode, a power­down sequence should take place first and then enter the ship mode. Once the device

enters ship mode, all the I2C register values are reset to their default setting.

To exit ship mode, one of the following conditions must be satisfied:

1. ON pin falling edge (filtered) applied, less than the long-press duration of time

2. A valid VIN attached. For the VIN attached plugin event, depending on
OPERATION_SEL_FROM_SHIPMODE bit setting, there are two possible operations
as described below:

a. OPERATION_SEL_FROM_SHIPMODE=0, upon VIN attached, the chip enables

the charging process, as well as start the power-up sequence for LDO1/LDO2/
SW1/SW2 per the setting

b. OPERATION_SEL_FROM_SHIPMODE=1, upon VIN attached, the chip enables

the charging process, LDO1/LDO2/SW1/SW2 remains in shutdown mode and the
chip will only enable the power-up sequence upon ON pin falling edge signal.

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8.9 Watchdog timer

PCA9420 provides an on-chip watchdog timer, the duration of this watchdog can be
programmed via I2C register setting (WD_TIMER_x [1:0] in each mode configuration
registers), or disabled if needed in each mode setting.

Upon initial enable, the watchdog timer starts counting. If the watchdog timer expires
before reset, an interrupt signal is issued (WD_TIMER). Depending on the I2C register
setting (nEN_CHG_IN_WATCHDOG), the following action is also taken:

1. nEN_CHG_IN_WATCHDOG = 0: when the watchdog timer expires, the following

2. nEN_CHG_IN_WATCHDOG=1: when the watchdog timer expires, the following

PCA9420

Power management IC for low-power microcontroller applications

operations are expected.

• The SYSRSTn signal asserted (high to low)

• Charging is continued based on battery condition

• All settings for LDO1/LDO2/SW1/SW2 set to Mode 0 settings

operations are expected.

• The SYSRSTn signal asserted (high to low)

• Charging is suspended

• All settings for LDO1/LDO2/SW1/SW2 set to Mode 0 settings

The following events reset the watchdog timer:

1. When WD_TIMER_CLR bit is set to 3b’001 at 0Dh register

2. When the device changes the mode settings

8.10 Regulators

There are four regulators on PCA9420, which include two buck regulators and two LDOs.

Table 5 shows the outline for each regulator:

Table 5.  Regulator summary

Regulator name Output regulation voltage range Adjustable resolution Max output current

SW1 (Core Buck) 0.5V ~ 1.5V and a fixed 1.8V 25mV/step Up to 250mA

SW2 (System Buck) 1.5V ~ 2.1V or 2.7V~3.3V 25mV/step Up to 500mA

LDO1 (Always-on LDO) 1.7V ~ 1.9V 25mV/step Up to 1mA

LDO2 (System LDO) 1.5V ~ 2.1V or 2.7V~3.3V 25mV/step Up to 250mA

For each rail, its output target voltage can be set independently in mode setting 0, 1, 2 or

3. User can also choose to switch among any of the mode settings.

8.10.1 Enable/disable and active discharge

Enable/disable: Each rail can be enabled/disabled via I2C register setting independently

in each mode setting.

Active discharge: Additionally, there is an active discharge resistor on each rail, and
the user can choose to enable/disable such feature through I2C register setting, so that
when the output rail is disabled, it can quickly discharge the output voltage to ground.
In addition, the active discharge is also enabled during voltage step down. This can be
disabled by MTP bit.

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8.10.2 Power-good indication

There is an output voltage comparator for each rail, comparing the actual output voltage
against 90% and 110% of its target value; when the actual voltage is between 90% and
110% of its target value, the read-only related bits in I2C register, Regulator Status_1
(address: 20h) are updated accordingly to report the output voltage status (Power-good
Indication). These comparators can be enabled/disabled by setting I2C register bit,
PG_EN. A corresponding interrupt is triggered if unmasked. During steady state, only
90% threshold is monitored.

The power-good indication is shown as “not good”, and refreshes upon the completion of
any of the following events:

1. During the power-up sequence stage

2. During power-down sequence stage

3. During the on-the-fly change of output voltage

8.10.3 Power-up/down sequence and on-the-fly voltage change

Power-up sequence

PCA9420

Power management IC for low-power microcontroller applications

The device initiates the default power-up sequence in three different conditions.

Condition 1) The device is off with no any power supply (No valid VIN and No battery
with 2.7V or above attached). In this condition, two signals below are able to start the
default power-up sequence.

• A valid VIN supply on VIN pin

• A voltage on ASYS higher than ASYS_UVLO, a 2.8V typical

Condition 2) The device stays off by enabling SHIPMODE or in SHIP mode with a
battery ≥ 2.8V attached. In this condition, two signals are able to start the default power­up sequence.

• A valid VIN supply on VIN pin

• A falling edge on ON key over a 200µs

Condition 3) The device stays off by enabling PWR_DN_EN bit setting to 1 with a
battery ≥ 2.8V attached. In this condition, only one signal is able to start the default
power-up sequence.

• A falling edge on ON key over a 200µs

Condition 4) The device stays at VIN OVP condition with no any valid supply attached
at VBAT. In result, all enabled power rails have been off. The following condition re­initiates the power-up sequence.

• The VIN goes below its VIN OVP hysteresis (typ 100mV)

The power-up sequence by ON key=Low over the debounce time is described as shown
in Figure 6.

For the power-up sequence, the chip can set the default sequence per the customer
requirement at factory setting (i.e. MTP option), from one of the 64 options. Once the chip
enters the power-down stage, the power-down sequence is implemented as the reverse
of the power-up sequence (i.e., first up, last down).

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Product data sheet Rev. 2 — 26 January 2021

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aaa-033080

POWER-UP SEQUENC

E

ON Key

Default-On Rail

s

Position

1

=1m

s

SYSRSTn

POWER-OFF STATE

CONTROL BY PROCESSOR

T

PWUP_DLY_INTERVAL

(ON Long-Press Timer, 4s,8s,12s or 16s)

t

ON_LONG_PRESS

90%

2

3

4

T

ON_DEBOUNCE

=200µs

NOTE: BUCK1, BUCK2, LDO1 and LDO2 can be assigned to any of position 1-

4

(NOTE

)

3

2

1

=2m

s

The ON Key shall be pulled high
to avoid power recycle initiated
by a programmed ON long-Press
timer expired

PWR_DN_EN bit=1

O

R

SHIP_EN_x bit=1

Position

4

POWER-DOWN SEQUENCE

T

PWDOWN_DLY_INTERVAL

Figure 6. Power-up/down sequence

On-the-fly output voltage change sequence

PCA9420

Power management IC for low-power microcontroller applications

On-the-fly output voltage change is defined as the following: for any output rail, its
output voltage changes from one level (initial level) to another level (target level). Note
this assumes the output rail is always enabled before and after the on-the-fly change
transition. It does not include the case when any output rail is changed from disabled
state to enabled state, or vice versa.

If a user prefers to change any rail voltage on-the-fly, depending on the scenarios listed
below, the chip behavior is described as the following:

1. While the chip remains in its current operation mode, and the user programs the

2. While the user chooses to switch modes, i.e. change mode between any of the two

CAUTION: The user should not send an I2C command related to changing the setting of
the output rails during the power up/down or mode setting change process.

8.10.4 BUCK1 (SW1, core buck regulator)

The SW1 supplies the core power.

Its output voltage can be programmed via I2C from 0.5V to 1.5V at 25mV step and a fixed

1.8V, which is capable of providing up to 250mA loading. The application circuit uses

8.10.5 BUCK2 (SW2, system buck regulator)

typical 2.2µH inductor and 10µF/6.3V output capacitor.

output voltage setting I2C register value or enables/disables any or some of output
voltage rail(s), the chip simply executes the I2C command

mode settings among Mode 0/1/2/3, and if this involves on-the-fly voltage change for
one or some output rails, such change should occur simultaneously when the chip
switches from initial mode to the target mode.

The SW2 output voltage can be programmed via I2C register from 1.5V to 2.1V, or from

2.7V to 3.3V in both at 25mV/step and is capable of providing up to 500mA loading. The

application circuit uses a 2.2µH inductor and 10µF output capacitor.

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NXP Semiconductors

aaa-033081

V

SW2_Regulatio

n

V

PSYS2

(

V

PSYS2

- V

SW2_Regulatio

n

)=200mV

50m

V

SW2 in regulation mode

SW2 in pass-through mo

de

SW2 in regulation mode

Delta V

=R

RDS_ON_High_side

x

I

LOA

D

Delta V

In SW2, a pass-through mode is implemented. When its input (ASYS) is close to the
output voltage (within typical 200mV), the SW2 enters the pass-through mode operation;
the high-side switch is fully turned on and the low-side switch is turned off, and the output
voltage can be calculated as input voltage – (RDSON*I
resistance of the high-side switch, and the I
input voltage rises again, so that the voltage different between input and output crosses
the typical 250mV threshold, the SW2 exits the pass-through mode and re- enters the
normal switching mode operation.

While SW2 operates in pass-through mode, protection features such as over-current
protection are also implemented as well.

PCA9420

Power management IC for low-power microcontroller applications

), where RDSON is the on-

LOAD

refers to the load current. When the

LOAD

Figure 7. Pass-Through mode of BUCK2 (SW2)

8.10.6 LDO1 (always-on LDO)

The LDO1 (Always-on LDO) output can be programmed from 1.7V to 1.9V at 25mV step,
depending on the system requirements (selectable through I2C register). Typically, a
1µF/6.3V MLCC output capacitor providing at least 1mA loading capability is needed.

8.10.7 LDO2 (system LDO)

The LDO2 (system LDO) output can be programmed via the I2C register from 1.5V
to 2.1V, or 2.7V to 3.3V at 25mV/step. Typically, a 2.2µF/6.3V MLCC output capacitor
providing at least 250mA loading current is needed.

8.11 Linear battery charger

The battery charger is a linear charger. Its charging is done through a linear switch with
the following output protections:

• Reverse current protection

– (triggers when VIN < VBAT+ VIN2BAT_HEADROOM*)

• Charging current limiting

– (a function of programmed threshold and battery temperature)

• VBAT short circuit protection

– short circuit output voltage threshold: (typ 0.8V with 80mV hysteresis)
– Maximum output sourcing current during “short circuit” detection ~ 13mA

(VIN2BAT_HEADROOM = 100mV, typical)

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Product data sheet Rev. 2 — 26 January 2021

If the battery voltage is below the V
discharged and a preconditioning cycle begins. The amount of pre-charge current
(ICHG_LOW) can be programmed through I2C register setting. This feature is useful
when there is a load connected directly across the battery (at VBAT pin) “stealing” the

BAT_LOW

threshold, the battery is considered

16 / 82

NXP Semiconductors

battery current. The pre-charge current can be set higher to account for the system
loading while allowing the battery to be properly conditioned. Once the battery voltage
has charged to the V
charge current (I
using I2C register. The constant current provides the bulk of the charge. Power
dissipation in the device is greatest in fast charge with a lower battery voltage.

If the device reaches a programmed thermal regulation threshold temperature from 85°C
to 115°C in 5°C steps, the device enters thermal regulation. Thermal regulation increases
the safe-charging-timer period by 2x and reduces the charge current in half (if the initial
current is 5mA, it will remain unchanged) to keep the temperature from rising any further
when battery charger works in constant current charging mode, or at a reduced regulated
voltage when battery charger works in constant voltage charging mode.

Figure 8 shows the charging profile with a dead battery condition. Once the cell has

charged to the regulation voltage (V
the battery at the regulation voltage until the current tapers to the termination threshold
(I

CHG_TOPOFF

8.11.1 Battery charging management

PCA9420

Power management IC for low-power microcontroller applications

BAT_LOW

CHG_CC

).

threshold, fast charge is initiated and a programmed fast

) is applied. The fast charge constant current is programmed

BAT_REG

) the voltage loop takes control and holds

Battery charging management supports typical constant current/constant voltage
charging profile for single cell Li-Ion battery, as well as pre-qualification (dead battery, low
battery), top-off mode, etc.; JEITA and thermal regulation compliant.

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aaa-033082

VBAT

V

BAT_REG

3.6V to 4.6V, 20mV steps, 4.2V Default

V

BAT_DEA

D

1.9V

(1.7V,1.8V,2V by

MTP)

VBA

T

Trickle Charge
(Dead Battery)

Mode

Fast Charge Mode

Top-OFF

Mode

Charging Done Mode

I

CHG_DEA

D

I

CHG_C

C

Input & Charge Curren

t

Current to battery

I

CHG_TOPO

FF

I

CHG

=0m

A

I

VIN__LI

M

0mA

V

BAT_RESTAR

T

Recharge Mod

e

(Fast Charge Mode)

0V

V

BAT_LOW

2.5V

(2.3V,2.4V,2.6V by MTP)

I

CHG_LOW

t

DGL_BAT_LOW2CC=50µs

Pre-charge

(Low-Voltage

)

Mode

5mA to 315mA programmable in 5mA step

s

t

DGL_BAT_CC2TOPOFF=20ms

(=V

BAT_REG

-140mV or 240mVtyp)

t

DGL_BAT_RESTART

=50ms

I

CHG_TOPOFF

Tim

e

Tim

e

di/dt=3mA/µ

s

85mA to 1105mA programmable

1mA to 63mA programmable
in 1mA steps

1mA to 63mA programmable
in 1mA steps

1mA to 63mA programmabl

e

in 1mA step

s

Shall be updated with 1mA to 20mA Programmabl

e

in 1mA steps due to top-off proble

m

reset

t

DGL_BAT_DEAD2LOW=50µs

T

CHG_FAS

T

T

CHG_TOPOFF

3, 5, 7, or 9 hours

reset

0, 6.4, 12.8, or 19.2min

T

CHG_TOPOFF

starte

d

T

CHG_TOPOFF

expired

T

CHG_TOPOF

F

T

CHG_PRE

Q

15, 30, 45,

or 60mi

n

reset

OFF

O

N

OFF

OFF

O

N

O

N

Fast Charge Mod

e

PCA9420

Power management IC for low-power microcontroller applications

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Product data sheet Rev. 2 — 26 January 2021

Figure 8. Typical Charging Profile Example

18 / 82

NXP Semiconductors

aaa-033083

Device in non-charging mode

- VIN < VI

N

UVL

O

- CHG_EN=0 or 1

- TJ <

T

J(OFF

)

, 150°C

Any Charging Stat

e

VBAT >

V

BAT_DEA

D

&

&

t

DGL_BAT_DEAD2LOW, 50µs

Charging Stopped

A programmed watchdog timer expired in
nEN_CHG_IN_WATCHDOG=1
&& WD_TIMER_A/B/C/D=2b01, 10, or 1

1

o

r
TJ ≥ a programmed TSHDN
o

r
One of the safety timers (TCHG_PREQ & TCHG_FAST) expire

d

VIN has been validated
&

&

Battery attache

d

&

&

CHG_EN=1

Device in Dead Battery Chargin

g

- Charge current=

I

CHG_DEA

D

- T

CHG_PREQ

started counting

Device in Pre-Charge

(Low Voltage) Mod

e

- Charge current=

I

CHG_LOW

Device in Fast Charge Mode

- Charge current=

I

CHG_C

C

- T

CHG_PREQ

reset

- T

CHG_FAST

started countin

g

VBAT >

V

BAT_LOW

&

&

t

DGL_BAT_LOW2CC, 50µ

s

Device in Top-Off Mod

e

- T

CHG_FAST

reset

- T

CHG_TOPOFF

started countin

g

I

CHG

<

I

CHG_TOPOF

F

for

t

DGL_BAT_CC2TOPOFF, 20ms

T

CHG_TOPOF

F

expire

d

Device in DONE Mo

de

- T

CHG_TOPOFF

reset

- I

CHG

=0mA

I

C

HG

> 2x I

CHG_TOPOFF

or

20mA, whichever is lowe

r

VBAT-

V

BAT_REG

≤

V

BAT_RESTART

, 140mV typ
(240mV by MTP)
&

&

t

DGL_BAT_RESTART, 50ms

TJ = A programmed

T

THEM_REGULATION

Charging in Thermal Regulation

- ICHG= (A programmed

I

CHG_C

C

) x

1_
2

VBAT ≤

V

BAT_DEA

D

VBAT ≤> V

BAT_LOW

&

&

t

DGL_BAT_CC2LOW, 50ms

Any Charging State

PCA9420

Power management IC for low-power microcontroller applications

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Figure 9. Charger State Diagram

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aaa-033084

45°C

10°C

Programmed VBAT_REG

0°C

Hot fault

charge disable

No operation

during cold fault

Programmed ICHG

(100%)

50%

Cold fault

0

0.2

VHOT VWARM

0.4

0.6

0.8 1.0

VCOOL

1.2 1.4

VCOLD

1.6

Termination

disable

1.8

TS voltage-V

8.11.2 Battery temperature sensing and JEITA-compliant charging profile

PCA9420

Power management IC for low-power microcontroller applications

Figure 10. Operation over TS bias voltage for JEITA

8.11.3 Low-battery/dead-battery (pre-qualification) charging

If the battery is detected and VBAT < VBAT_LOW, the charger initiates pre-charging
using a predefined (I2C register) current.

When it is under the dead-battery condition, the charging current I

CHG_DEAD

is
programmed by ICHG_DEAD [5:0]; and when it is under the low-battery condition, the
charging current I

CHG_LOW

is programmed by ICHG_LOW [5:0]. When V

BAT

≥ V

BAT_LOW

the charger moves to the next state, fast charging mode.

8.11.4 Constant current charging/constant voltage charging (fast charging) and termination

When V
state, the battery voltage VBAT continues to rise, while the battery is being charged with
the current set by ICHG_CC [5:0], until VBAT reaches the maximum allowable voltage
set by VBAT_REG [5:0].

At this time, the charger enters the Constant Voltage (CV) mode. While operating in
the CV mode, the voltage is still regulated at the level set by VBAT_REG [5:0], and the
charging current continues to decrease.

When the charging current drops below the top-off current threshold, set by
ICHG_TOPOFF [5:0], the charger enters TOPOFF mode, and upon expiration of
TOPOFF timer (set by T_TOPOFF [1:0]), the charger enters DONE mode.

BAT

≥ V

BAT_LOW

, the charger enters Fast Charge Mode (Constant Current). In this

,

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8.11.5 Charger safety timers

Two sets of charging safety timers are implemented on PCA9420. These timers
ensure the charging is terminated if the charging time is longer than its predefined limit
(programmed via I2C registers) at given states:

• Pre-qualification timer, set by ICHG_PREQ_TIMER [1:0], 15min ~ 60min

• Fast charge timer, set by ICHG_FAST_TIMER [1:0], 3hr ~ 9hr

8.11.6 Recharging

While in DONE mode, if the voltage of VBAT stays below (a programmed VBAT_REG –
140mV or 240mV) over the deglitch time (t
resumes back to Constant Current (CC) Mode.

8.11.7 Starting a new charge cycle

When a VIN plug in, VBAT attached, or CHG_EN are set to “1”, the device initializes a
new charging process.

PCA9420

Power management IC for low-power microcontroller applications

DGL_BAT_RESTART

), 50ms the battery charger

8.11.8 Battery attach detection

The device has a unique battery detection scheme with two comparators, 1.9V and 3.4V.
when the detection scheme is executed, a 5mA current sink is activated to determine
battery presence by detection the fall threshold, V
a 5mA current source is used to detect battery voltage whether it stays above the
threshold, V

BAT_DET_UP

, 3.4V. if both conditions are met, absence of battery is declared.

8.12 Hardware and software reset

Please refer to description for ON pin for the hardware reset function by a long time
ON key pressed. The "software reset” is achieved by setting “1” to SW_RST bit in I2C
register. If the user writes a “1” to this bit, it resets all other I2C register bits to their default
setting; this bit is cleared and reset back to “0” as well.

9 I2C-bus interface and register

The PCA9420 implements an I2C-bus slave interface to communicate with the host
system. The interface supports Fast Mode plus Fm+ with up to 1 Mbit/s. A detailed
description of the I2C-bus specification is given in UM10204, Rev. 06, 4 April 2014 ,“ I2C­bus specification and user manual”.

Features such as clock-stretching and 10-bit slave address are not supported; general
call is supported by default but can be disabled via metal option. Auto increment with
address wrap-around is supported as well.

BAT_DET_LOW

, 1.9V typ. In addition,

9.1 I2C slave address

Following a START condition, the bus master must send the target slave address
followed by a read or write operation. The slave address of the PCA9420 is shown below:

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PCA9420

Power management IC for low-power microcontroller applications

Table 6. I2C Slave Address

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

1 1 0 0 0 0 1 0/1

Fixed Fixed Fixed MTP option Fixed Fixed Fixed R/W

Bit 4 should be reserved as MTP option, with its default value set as “0” but can be
trimmed to “1” when needed.

9.2 General call and device ID addresses

The device implements two different addresses for general call and device ID.

9.3 Register type

There are four register types used on the device:

• Read and Write (R/W)

• Read Only (R)

• Write Only (W)

• Write and Clear (W/C)

For Write and Clear (W/C), a write to a register with a bit-mask specifies which interrupts
to clear.

For example, if the status register shows 8’b0000_1001 as an interrupt status (i.e.
interrupt [0] and interrupt [3] are both set), user may write 8’b0000_1000, meaning the
intent is to only clear interrupt [3] (but interrupt [0] should NOT be “cleared”). If the intent
is to clear both interrupts, then the user could write back 8’b0000_1001.

9.4 Register map

Table 7. Register map

Address
(Hex)

System Control Registers

00 Device Information, DEV_INFO Device ID, revision R 0000 0000

01 Top Level Interrupt Status, TOP_INT Top level interrupt event status R/C 0000 0000

02 Sub Level Interrupt_0, SUB_INT0 Sub-level interrupt indication_0 W/C 0000 0000

03 Sub Level Interrupt_0 Mask, SUB_

04 Sub Level Interrupt_1, SUB_INT1 Sub-level interrupt indication_1 W/C 0000 0000

05 Sub Level Interrupt_1 Mask, SUB_

06 Sub Level Interrupt_2, SUB_INT2 Sub-level interrupt indication_2 W/C 0000 0000

07 Sub Level Interrupt_2 Mask, SUB_

08 RSVD Reserved R/W 0000 0000

09 Top Level Control_0, TOP_CNTL0 Top level system control_0 R/W 0100 0001

Register Name Description Type Reset

Value
(Binary)

INT0_MASK

INT1_MASK

INT2_MASK

Sub-level interrupt mask for SUB_
INT0

Sub-level interrupt mask for SUB_
INT1

Sub-level interrupt mask for SUB_
INT2

R/W 0011 1111

R/W 0111 1111

R/W 1111 1111

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PCA9420

Power management IC for low-power microcontroller applications

Table 7. Register map...continued

Address
(Hex)

0A Top Level Control_1, TOP_CNTL1 Top level system control_1 R/W 1000 1001

0B Top Level Control_2, TOP_CNTL2 Top level system control_2 R/W 1100 1110

0C Top Level Control_3, TOP_CNTL3 Top level system control_3 R/W 0000 0001

0D Top Level Control_4, TOP_CNTL4 Top level system control_4 W 0000 0000

0E – 0F RSVD Reserved

Battery Charger Control

10 Battery Charger Control_0, CHG_

11 Battery Charger Control_1, CHG_

12 Battery Charger Control_2, CHG_

13 Battery Charger Control_3, CHG_

14 Battery Charger Control_4, CHG_

15 Battery Charger Control_5, CHG_

16 Battery Charger Control_6, CHG_

17 Battery Charger Control_7, CHG_

18 Battery Charger Status_0, CHG_

19

1A

1B

1C – 1F RSVD Reserved

Regulator Control

20 Regulator Status, REG_STATUS Regulators status indication R 0000 0000

21

22

23

24

Register Name Description Type Reset

Value
(Binary)

Battery charger control register_0 R/W 0000 0011

CNTL0

Battery charger control register_1 R/W 0000 1000

CNTL1

Battery charger control register_2 R/W 0000 0100

CNTL2

Battery charger control register_3 R/W 0000 1000

CNTL3

Battery charger control register_4 R/W 0000 0100

CNTL4

Battery charger control register_5 R/W 0001 1110

CNTL5

Battery charger control register_6 R/W 1001 0101

CNTL6

Battery charger control register_7 R/W 0010 0100

CNTL7

Battery charger status indication_0 R 0001 0000

STATUS_0

Battery Charger Status_1, CHG_
STATUS_1

Battery Charger Status_2, CHG_
STATUS_2

Battery Charger Status_3, CHG_
STATUS_3

Active Discharge Control, ACT_
DISCHARGE_CNTL_1

Mode Configuration Mode Setting 0_
0, MODECFG_0_0

Mode Configuration Mode Setting 0_
1, MODECFG_0_1

Mode Configuration Mode Setting 0_
2, MODECFG_0_2

Battery charger status indication_1 R 0000 0000

Battery charger status indication_2 R 0111 1000

Battery charger status indication_3 R 0000 0000

Active Discharge control register R/W 0000 0000

Mode configuration settings for
Mode 0_0

Mode configuration settings for
Mode 0_1

Mode configuration settings for
Mode 0_2

R/W 0001 0100

R/W 0000 1100

R/W 0100 1111

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Table 7. Register map...continued

Address
(Hex)

25

26

27

28

29

2A

2B

2C

2D

2E

2F

30

31

Register Name Description Type Reset

Mode Configuration Mode Setting 0_
3, MODECFG_0_3

Mode Configuration Mode Setting 1_
0, MODECFG_1_0

Mode Configuration Mode Setting 1_
1, MODECFG_1_1

Mode Configuration Mode Setting 1_
2, MODECFG_1_2

Mode Configuration Mode Setting 1_
3, MODECFG_1_3

Mode Configuration Mode Setting 2_
0, MODECFG_2_0

Mode Configuration Mode Setting 2_
1, MODECFG_2_1

Mode Configuration Mode Setting 2_
2, MODECFG_2_2

Mode Configuration Mode Setting 2_
3, MODECFG_2_3

Mode Configuration Mode Setting 3_
0, MODECFG_3_0

Mode Configuration Mode Setting 3_
1, MODECFG_3_1

Mode Configuration Mode Setting 3_
2, MODECFG_3_2

Mode Configuration Mode Setting 3_
3, MODECFG_3_3

PCA9420

Power management IC for low-power microcontroller applications

Value
(Binary)

Mode configuration settings for
Mode 0_3

Mode configuration settings for
Mode 1_0

Mode configuration settings for
Mode 1_1

Mode configuration settings for
Mode 1_2

Mode configuration settings for
Mode 1_3

Mode configuration settings for
Mode 2_0

Mode configuration settings for
Mode 2_1

Mode configuration settings for
Mode 2_2

Mode configuration settings for
Mode 2_3

Mode configuration settings for
Mode 3_0

Mode configuration settings for
Mode 3_1

Mode configuration settings for
Mode 3_2

Mode configuration settings for
Mode 3_3

R/W 0011 1001

R/W 0001 1100

R/W 0100 1100

R/W 0100 1111

R/W 0000 1100

R/W 0001 1100

R/W 0100 1100

R/W 0100 1111

R/W 0000 1100

R/W 0001 1100

R/W 0100 1100

R/W 0100 1111

R/W 0000 1100

9.5 Register description

9.5.1 Device information (DEV_INFO, address 00h)

The device identification code stores a unique identifier for each version and/or revision
of device, so that the connected MCU recognizes it automatically.

This is a READ ONLY register.

Table 8. DEV_INFO register bit description

Bit Symbol Default value Type Function

7 DEV_ID [4] 0 R

6 DEV_ID [3] 0 R

5 DEV_ID [2] 0 R

4 DEV_ID [1] 0 R

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Device ID

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Power management IC for low-power microcontroller applications

Table 8. DEV_INFO register bit description...continued

Bit Symbol Default value Type Function

3 DEV_ID [0] 0 R

2 DEV_REV [2] 0 R

1 DEV_REV [1] 0 R

0 DEV_REV [0] 0 R

9.5.2 Top level interrupt status (TOP_INT, address 01h)

The top-level interrupt register contains flags indicating various top level interrupt events
as indicated below. An event will be latched and only its first occurrence triggers the
interrupt signal INTB (if it is not being masked). Reoccurring events will not change the
flag's status or trigger an additional interrupt. If multiple interrupt events happen, its
corresponding interrupt bits in the related registers will be “triggered”, however, the INTB
signal will be only triggered upon the first interrupt event.

The interrupt event reporting on the device is structured in a two-layer configuration. The
interrupt events are grouped as (1) system level; (2) charger block; (3) buck regulator
block; (4) LDO block. When any interrupt event is triggered, based on which mode it
falls into, the related bit for that mode in TOP_INT flags “1”. Any of the related bits in
TOP_INT will only change back to 0 when all the interrupt events in its affiliated mode
have been cleared.

Device revision

PCA9420

This is READ Only register.

Table 9. TOP_INT register bit description

Bit Symbol Default value Type Function

7 RSVD 0 R Reserved bit

6 RSVD 0 R Reserved bit

5 RSVD 0 R Reserved bit

4 RSVD 0 R Reserved bit

3 SYS_INT 0 R System level interrupt event trigger indication 0: no system level

interrupt event triggered 1: system level interrupt event triggered

2 CHG_INT 0 R Linear battery charger block interrupt event trigger indication 0: no

linear battery charger block interrupt event triggered
1: linear battery charger block interrupt event triggered

1 SW_INT 0 R Buck regulator blocks (SW1, SW2) interrupt event trigger indication 0:

no interrupt event on SW1 and/or SW2 blocks triggered
1: interrupt event on SW1 and/or SW2 blocks triggered

0 LDO_INT 0 R LDO block (LDO1, LDO2) interrupt event trigger indication 0: no

interrupt event on LDO1 and/or LDO2 blocks triggered 1: interrupt
event on LDO1 and/or LDO2 blocks triggered

9.5.3 Sub level interrupt_0 (SUB_INT0, address 02h)

The sub-level interrupt register contains flags indicating the second-tier interrupt event.
For this register, it contains system level related interrupt events.

This is WRITE AND CLEAR register.

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