NXP PBSS4160U Schematic [ru]
PBSS4160U
60 V, 1 A NPN low V
Rev. 03 — 11 December 2009 Product data sheet
1. Product profile
1.1 General description
NPN low V
Surface Mounted Device (SMD) plastic package.
PNP complement: PBSS5160U.
1.2 Features
Low collector-emitter saturation voltage V
High collector current capability: IC and I
High collector current gain (hFE) at high I
High efficiency due to less heat generation
Smaller required Printed-Circuit Board (PCB) area than for conventional transistors
(BISS) transistor
CEsat
Breakthrough In Small Signal (BISS) transistor in a SOT323 (SC-70)
CEsat
CEsat
CM
C
1.3 Applications
High voltage DC-to-DC conversion
High voltage MOSFET gate driving
High voltage motor control
High voltage power switches (e.g. motors, fans)
Automotive applications
1.4 Quick reference data
Table 1. Quick reference data
Symbol Parameter Conditions Min Typ Max Unit
V
CEO
I
C
I
CM
R
CEsat
[1] Device mounted on a ceramic PCB, Al2O3, standard footprint.
[2] Pulse test: t
collector-emitter voltage open base - - 60 V
collector current (DC)
peak collector current single pulse; tp≤ 1ms--2A
collector-emitter saturation
resistance
≤ 300 μs; δ ≤ 0.02.
p
IC=1A; IB=100mA
[1]
--1A
[2]
- 230 280 mΩ
NXP Semiconductors
1
PBSS4160U
2. Pinning information
Table 2. Pinning
Pin Description Simplified outline Symbol
1base
2emitter
3 collector
3. Ordering information
Table 3. Ordering information
Type number Package
PBSS4160U SC-70 plastic surface mounted package; 3 leads SOT323
60 V, 1 A NPN low V
3
12
(BISS) transistor
CEsat
1
sym02
3
2
Name Description Version
4. Marking
Table 4. Marking codes
Type number Marking code
PBSS4160U 52*
[1] * = -: made in Hong Kong
* = p: made in Hong Kong
* = t: made in Malaysia
* = W: made in China
[1]
PBSS4160U_3 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 03 — 11 December 2009 2 of 14
NXP Semiconductors
006aaa501
PBSS4160U
5. Limiting values
Table 5. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter Conditions Min Max Unit
V
CBO
V
CEO
V
EBO
I
C
I
CM
I
B
I
BM
P
tot
T
j
T
amb
T
stg
[1] Device mounted on an FR4 PCB, single-sided copper, tin-plated and standard footprint.
[2] Device mounted on an FR4 PCB, single-sided copper, tin-plated, mounting pad for collector 1 cm
[3] Device mounted on a ceramic PCB, Al
60 V, 1 A NPN low V
(BISS) transistor
CEsat
collector-base voltage open emitter - 80 V
collector-emitter voltage open base - 60 V
emitter-base voltage open collector - 5 V
collector current (DC)
[1]
-750mA
[2]
-930mA
[3]
-1A
peak collector current single pulse; tp≤ 1ms - 2 A
base current (DC) - 300 mA
peak base current single pulse; tp≤ 1ms - 1 A
total power dissipation T
≤ 25 °C
amb
[1]
-250mW
[2]
-350mW
[3]
-415mW
junction temperature - 150 °C
ambient temperature −65 +150 °C
storage temperature −65 +150 °C
2
, standard footprint.
2O3
.
0.5
P
tot
(W)
(1)
0.4
(2)
0.3
(3)
0.2
0.1
0
0 16012040 80
(1) Ceramic PCB, Al2O3, standard footprint
(2) FR4 PCB, mounting pad for collector 1 cm
(3) FR4 PCB, standard footprint
Fig 1. Power derating curves
T
(°C)
amb
2
PBSS4160U_3 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 03 — 11 December 2009 3 of 14
NXP Semiconductors
PBSS4160U
6. Thermal characteristics
Table 6. Thermal characteristics
Symbol Parameter Conditions Min Typ Max Unit
thermal resistance from
junction to ambient
thermal resistance from
junction to solder point
Z
th(j-a)
(K/W)
R
th(j-a)
R
th(j-sp)
[1] Device mounted on an FR4 PCB, single-sided copper, tin-plated and standard footprint.
[2] Device mounted on an FR4 PCB, single-sided copper, tin-plated, mounting pad for collector 1 cm
[3] Device mounted on a ceramic PCB, Al
3
10
δ = 1
0.75
0.50
0.33
0.20
2
10
0.10
0.05
60 V, 1 A NPN low V
in free air
, standard footprint.
2O3
(BISS) transistor
CEsat
[1]
--500K/W
[2]
--357K/W
[3]
--301K/W
--150K/W
2
.
006aaa502
0.02
10
0.01
0
1
−5
10
−4
10
−3
10
−2
−1
10
1
1010
2
10
tp (s)
10
FR4 PCB, standard footprint
Fig 2. Transi en t the rmal impe da n ce from junc tio n to ambient as a function of pulse time; typical values
3
PBSS4160U_3 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 03 — 11 December 2009 4 of 14
NXP Semiconductors
PBSS4160U
3
10
Z
(K/W)
th(j-a)
10
δ = 1
0.75
0.50
2
10
1
10
−5
0.20
0.10
0.05
0.02
0.01
0.33
0
−4
10
FR4 PCB, mounting pad for collector 1 cm
60 V, 1 A NPN low V
−3
10
−2
2
−1
10
1
1010
(BISS) transistor
CEsat
006aaa503
2
10
tp (s)
10
Fig 3. Transi en t the rmal impe da n ce from junc tio n to ambient as a function of pulse time; typical values
3
10
006aaa504
3
Z
th(j-a)
(K/W)
δ = 1
0.75
0.50
2
10
10
1
10
−5
0.20
0.10
0.05
0.02
0.01
0.33
0
−4
10
−3
10
−2
−1
10
1
1010
2
10
tp (s)
10
Ceramic PCB, Al2O3, standard footprint
Fig 4. Transi en t the rmal impe da n ce from junc tio n to ambient as a function of pulse time; typical values
3
PBSS4160U_3 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 03 — 11 December 2009 5 of 14