NXP 74AHC2G125DC, 74AHC2G125DP, 74AHC2G125GD, 74AHCT2G125DC, 74AHCT2G125DP Schematic [ru]

...

74AHC2G125; 74AHCT2G125

Dual buffer/line driver; 3-state

Rev. 3 — 6 May 2013 Product data sheet

1. General description

The 74AHC2G125 and 74AHCT2G125 are high-speed Si-gate CMOS devices. They provide a dual non-inverting buffer/line driver with 3-state output. The 3-state output is controlled by the output enable input (nOE a high-impedance OFF-state.

The AHC device has CMOS input switching levels and supply voltage range 2 V to 5.5 V. The AHCT device has TTL input switching levels and supply voltage range 4.5 V to 5.5 V.

2. Features and benefits

 Symmetrical output impedance  High noise immunity  Low power dissipation  Balanced propagation delays  Multiple package options  ESD protection:

 HBM JESD22-A114E: exceeds 2000 V  MM JESD22-A115-A: exceeds 200 V  CDM JESD22-C101C: exceeds 1000 V

 Specifie d from 40 C to +125 C

). A HIGH at nOE causes the output to assume

3. Ordering information

Table 1. Ordering information

Type number Package

74AHC2G125DP 40 C to +125 C TSSOP8 plastic thin shrink small outline package; 8 leads; 74AHCT2G125DP 74AHC2G125DC 40 C to +125 C VSSOP8 plastic very thin shrink small outline package; 74AHCT2G125DC 74AHC2G125GD 40 C to +125 C XSON8 plastic extremely thin small outline package; no 74AHCT2G125GD

Temperature range Name Description Version

body width 3 mm; lead length 0.5 mm

8 leads; body width 2.3 mm

leads; 8 terminals; body 3  2  0.5 mm

SOT505-2

SOT765-1

SOT996-2

NXP Semiconductors

mce185

1A 1Y

1OE

2A 2Y

2OE

mce186

EN1

EN2

mna227

nOE

74AHC2G125

74AHCT2G125

1OE V

1A 2OE 2Y 1Y

GND 2A

001aaj260

1 2 3 4

6 5

8 7

001aaj261

74AHC2G125

74AHCT2G125

Transparent top view

1OE

GND

2OE

4. Marking

74AHC2G125; 74AHCT2G125

Dual buffer/line driver; 3-state

Table 2. Marking codes

Type number Marking

74AHC2G125DP A25 74AHCT2G125DP C25 74AHC2G125DC A25 74AHCT2G125DC C25 74AHC2G125GD A25 74AHCT2G125GD C25

5. Functional diagram

Fig 1. Logic symbol Fig 2. IEC logic symbol Fig 3. Logic diagram (one buffer)

6. Pinning information

6.1 Pinning

Fig 4. Pin configuration SOT505-2 (TSSOP8) and

SOT765-1 (VSSOP8)

Fig 5. Pin configuration SOT996-2 (XSON8)

Product data sheet Rev. 3 — 6 May 2013 2 of 16

NXP Semiconductors

74AHC2G125; 74AHCT2G125

Dual buffer/line driver; 3-state

6.2 Pin description

Table 3. Pin description

Symbol Pin Description

, 2OE 1, 7 output enable input (active LOW)

1OE 1A, 2A 2, 5 data input GND 4 ground (0 V) 1Y, 2Y 6 , 3 data output V

8 supply voltage

7. Functional description

Table 4. Function table

Control Input Output nOE nA nY

LLL LHH HXZ

[1]

[1] H = HIGH voltage level; L = LOW voltage level; X = don’t care; Z = high-impedance OFF-state.

8. Limiting values

Table 5. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).

Symbol Parameter Conditions Min Max Unit

GND

stg

tot

[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed. [2] For TSSOP8 package: above 55 C the value of P

For VSSOP8 package: above 110 C the value of P For XSON8 package: above 45 C the value of P

supply voltage 0.5 +7.0 V input voltage 0.5 +7.0 V input clamping current VI < 0.5 V output clamping current VO < 0.5 V or VO>VCC+0.5V output current 0.5 V < VO <VCC+0.5V - 25 mA supply current - 75 mA ground current 75 - mA storage temperature 65 +150 C total power dissipation T

[1]

20 - mA

[1]

- 20 mA

= 40 C to +125 C

amb

derates linearly with 2.5 mW/K.

tot

derates linearly with 8 mW/K.

tot

derates linearly with 2.4 mW/K.

tot

[2]

- 250 mW

Product data sheet Rev. 3 — 6 May 2013 3 of 16

NXP Semiconductors

74AHC2G125; 74AHCT2G125

9. Recommended operating conditions

Dual buffer/line driver; 3-state

Table 6. Recommended operating conditions

Voltages are referenced to GND (ground = 0 V).

Symbol Parameter Conditions 74AHC2G125 74AHCT2G125 Unit

Min Typ Max Min Typ Max

amb

t/V input transition rise

supply voltage 2.0 5.0 5.5 4.5 5.0 5.5 V input voltage 0 - 5.5 0 - 5.5 V output voltage 0 - V

0-VCCV

ambient temperature 40 +25 +125 40 +25 +125 C

= 3.3 V  0.3 V - - 100 - - - ns/V

and fall rate

= 5.0 V  0.5 V - - 20 - - 20 ns/V

10. Static characteristics

Table 7. Static characteristics

Voltages are referenced to GND (ground = 0 V).

Symbol Parameter Conditions 25 C 40 C to +85 C 40 C to +125 C Unit

74AHC2G125

HIGH-level input voltage

LOW-level input voltage

HIGH-level output voltage

LOW-level output voltage

OFF-state output current

input leakage current

supply current VI=VCCor GND; IO = 0 A;

Min Typ Max Min Max Min Max

= 2.0 V 1.5 - - 1.5 - 1.5 - V

= 3.0 V 2.1 - - 2.1 - 2.1 - V

= 5.5 V 3.85 - - 3.85 - 3.85 - V

= 2.0 V - - 0.5 - 0.5 - 0.5 V

= 3.0 V - - 0.9 - 0.9 - 0.9 V

= 5.5 V - - 1.65 - 1.65 - 1.65 V

VI= VIH or V

IO= 50 A; VCC= 2.0 V 1.9 2.0 - 1.9 - 1.9 - V

= 50 A; VCC= 3.0 V 2.9 3.0 - 2.9 - 2.9 - V

= 50 A; VCC= 4.5 V 4.4 4.5 - 4.4 - 4.4 - V

= 4.0 mA; VCC= 3.0 V 2.58 - - 2.48 - 2.40 - V

= 8.0 mA; VCC= 4.5 V 3.94 - - 3.8 - 3.70 - V

VI= VIH or V

IO= 50 A; VCC= 2.0 V - 0 0.1 - 0.1 - 0.1 V

= 50 A; VCC= 3.0 V - 0 0.1 - 0.1 - 0.1 V

= 50 A; VCC= 4.5 V - 0 0.1 - 0.1 - 0.1 V

= 4.0 mA; VCC= 3.0 V - - 0.36 - 0.44 - 0.55 V

= 8.0 mA; VCC= 4.5 V - - 0.36 - 0.44 - 0.55 V

VI=VCC or GND;

=5.5V

VI= 5.5 V or GND;

=0Vto5.5V

- - 0.25 - 2.5 - 10 A

- - 0.1 - 1.0 - 2.0 A

- - 1.0 - 10 - 40 A

VCC= 5.5 V

Product data sheet Rev. 3 — 6 May 2013 4 of 16

NXP Semiconductors

74AHC2G125; 74AHCT2G125

Dual buffer/line driver; 3-state

Table 7. Static characteristics …continued

Voltages are referenced to GND (ground = 0 V).

Symbol Parameter Conditions 25 C 40 C to +85 C 40 C to +125 C Unit

Min Typ Max Min Max Min Max

74AHCT2G125

I

input capacitance

HIGH-level

= 4.5 V to 5.5 V 2.0 - - 2.0 - 2.0 - V

input voltage LOW-level

= 4.5 V to 5.5 V - - 0.8 - 0.8 - 0.8 V

input voltage HIGH-level

output voltage

LOW-level output voltage

OFF-state output current

input leakage current

VI= VIH or VIL; VCC= 4.5 V

= 50 A 4.4 4.5 - 4.4 - 4.4 - V

= 8.0 mA 3.94 - - 3.8 - 3.70 - V

VI= VIH or VIL; VCC= 4.5 V

= 50 A - 0 0.1 - 0.1 - 0.1 V

= 8.0 mA - - 0.36 - 0.44 - 0.55 V

VI=VCC or GND; VCC=5.5V

VI= 5.5 V or GND; VCC=0Vto5.5V

supply current VI=VCCor GND; IO = 0 A;

= 5.5 V

additional supply current

per input pin; VI=3.4V; other inputs at VCCor GND;

=0 A; VCC = 5.5 V

input capacitance

- 1.5 10 - 10 - 10 pF

- - 0.25 - 2.5 - 10 A

- - 0.1 - 1.0 - 2.0 A

- - 1.0 - 10 - 40 A

- - 1.35 - 1.5 - 1.5 mA

- 1.5 10 - 10 - 10 pF

11. Dynamic characteristics

Table 8. Dynamic characteristics

GND = 0 V; for test circuit see Figure 8.

Symbol Parameter Conditions 25 C 40 C to +85 C 40 C to +125 C Unit

74AHC2G125

propagation delay

Product data sheet Rev. 3 — 6 May 2013 5 of 16

Min Typ Max Min Max Min Max

nA to nY; see Figure 6

VCC = 3.0 V to 3.6 V

[1] [2]

CL= 15 pF - 4.7 8.0 1.0 9.5 1.0 11.5 ns

= 50 pF - 6.6 11.5 1.0 13.0 1.0 14.5 ns

= 4.5 V to 5.5 V

[3]

CL= 15 pF - 3.4 5.5 1.0 6.5 1.0 7.0 ns

= 50 pF - 4.8 7.5 1.0 8.5 1.0 9.5 ns

NXP Semiconductors

74AHC2G125; 74AHCT2G125

Dual buffer/line driver; 3-state

Table 8. Dynamic characteristics

…continued

GND = 0 V; for test circuit see Figure 8.

Symbol Parameter Conditions 25 C 40 C to +85 C 40 C to +125 C Unit

Min Typ Max Min Max Min Max

enable time nOE to nY; see Figure 7

VCC = 3.0 V to 3.6 V

[1] [2]

CL= 15 pF - 5.0 8.0 1.0 9.5 1.0 11.5 ns

= 50 pF - 6.9 11.5 1.0 13.0 1.0 14.5 ns

= 4.5 V to 5.5 V

[3]

CL= 15 pF - 3.6 5.1 1.0 6.0 1.0 6.5 ns

= 50 pF - 4.9 7.5 1.0 8.5 1.0 9.5 ns

dis

disable time nOE to nY; see Figure 7

VCC = 3.0 V to 3.6 V

[1] [2]

CL= 15 pF - 6.0 9.7 1.0 11.5 1.0 12.5 ns

= 50 pF - 8.3 13.2 1.0 15.0 1.0 16.5 ns

= 4.5 V to 5.5 V

[3]

CL= 15 pF - 4.1 6.8 1.0 8.0 1.0 8.5 ns

= 50 pF - 5.7 8.8 1.0 10.0 1.0 11.0 ns

power dissipation capacitance

per buffer; CL=50pF;fi=1 MHz; VI=GNDtoV

[4]

-9- - - - -pF

74AHCT2G125

propagation delay

nA to nY; see Figure 6

VCC = 4.5 V to 5.5 V

[1] [3]

CL= 15 pF - 3.4 5.5 1.0 6.5 1.0 6.5 ns

= 50 pF - 4.8 7.5 1.0 8.5 1.0 8.5 ns

enable time nOE to nY; see Figure 7

VCC = 4.5 V to 5.5 V

[1] [3]

CL= 15 pF - 3.9 5.1 1.0 6.0 1.0 6.0 ns

= 50 pF - 5.1 7.5 1.0 8.5 1.0 8.5 ns

dis

disable time nOE to nY; see Figure 7

VCC = 4.5 V to 5.5 V

[1] [3]

CL= 15 pF - 4.5 6.8 1.0 8.0 1.0 8.0 ns

= 50 pF - 6.1 8.8 1.0 10.0 1.0 10.0 ns

Product data sheet Rev. 3 — 6 May 2013 6 of 16

NXP Semiconductors

mna230

PHL

PLH

nA input

nY output

GND

74AHC2G125; 74AHCT2G125

Dual buffer/line driver; 3-state

Table 8. Dynamic characteristics

…continued

GND = 0 V; for test circuit see Figure 8.

Symbol Parameter Conditions 25 C 40 C to +85 C 40 C to +125 C Unit

Min Typ Max Min Max Min Max

[1] tpd is the same as t

power dissipation capacitance

is the same as t

dis

per buffer; CL=50pF;fi=1 MHz; VI=GNDtoV

PLH PZL

PLZ

and t

PHL

PZH

PHZ

. .

[2] Typical values are measured at V [3] Typical values are measured at V [4] C

is used to determine the dynamic power dissipation PD(W).

D=CPD

= input frequency in MHz;

= output frequency in MHz;

= output load capacitance in pF;

= supply voltage in Volts.

 V

 fi+  (CL V

= 3.3 V.

= 5.0 V.

 fo)where:

[4]

-11- - - - - pF

12. Waveforms

Measurement points are given in Table 9. Logic levels: V

and VOH are typical output voltage levels that occur with the output load.

Fig 6. Input (nA) to output (nY) propagation delays

Product data sheet Rev. 3 — 6 May 2013 7 of 16

NXP Semiconductors

mna362

PLZ

PHZ

outputs

disabled

outputs enabled

outputs

enabled

output

LOW-to-OFF

OFF-to-LOW

output HIGH-to-OFF OFF-to-HIGH

nOE input

GND

PZL

PZH

Measurement points are given in Table 9. Logic levels: V

Fig 7. Enable and disable times

and VOH are typical output voltage levels that occur with the output load.

74AHC2G125; 74AHCT2G125

Dual buffer/line driver; 3-state

Table 9. Measurement points

Type Input Output

74AHC2G125 0.5V

74AHCT2G125 1.5 V 0.5V

Product data sheet Rev. 3 — 6 May 2013 8 of 16

0.5V

CC CC

VOL 0.3 V VOH 0.3 V VOL 0.3 V VOH 0.3 V

NXP Semiconductors

10 %

90 %

0 V

negative

pulse

positive

pulse

0 V

90 %

10 %

001aad983

DUT

RLS1

open

74AHC2G125; 74AHCT2G125

Dual buffer/line driver; 3-state

Fig 8. Test circuit for measuring switching times

Table 10. Test data

Type Input Load S1 position

74AHC2G125 V 74AHCT2G125 3 V  3 ns 15 pF, 50 pF 1 k open GND V

Test data is given in Table 10. Definitions test circuit:

= Termination resistance should be equal to output impedance Zo of the pulse generator.

= Load capacitance including jig and probe capacitance.

= Load resistance.

S1 = Test selection switch.

tr, t

PHL

 3 ns 15 pF, 50 pF 1 k open GND V

, t

PLH

PZH

, t

PHZ

PZL

CC CC

, t

PLZ

Product data sheet Rev. 3 — 6 May 2013 9 of 16

NXP Semiconductors

UNIT

max.

A2A3b

wyv

ceD

(1)E(1)

(1)

REFERENCES

OUTLINE VERSION

EUROPEAN

PROJECTION

ISSUE DATE

IEC JEDEC JEITA

0.15

0.00

0.95

0.75

0.38

0.22

0.18

0.08

3.1

2.9

3.1

2.9

0.65

4.1

3.9

0.70

0.35

8° 0°

0.13 0.10.20.5

DIMENSIONS (mm are the original dimensions)

Note

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

0.47

0.33

SOT505-2 - - -

02-01-16

w M

0.25

(A3)

detail X

v M

2.5 5 mm0

scale

TSSOP8: plastic thin shrink small outline package; 8 leads; body width 3 mm; lead length 0.5 mm

SOT505-2

1.1

pin 1 index

13. Package outline

74AHC2G125; 74AHCT2G125

Dual buffer/line driver; 3-state

Fig 9. Package outline SOT505-2 (TSSOP8)

Product data sheet Rev. 3 — 6 May 2013 10 of 16

NXP Semiconductors

UNIT

max.

A2A3b

wyv

ceD

(1)E(2)

(1)

REFERENCES

OUTLINE VERSION

EUROPEAN

PROJECTION

ISSUE DATE

IEC JEDEC JEITA

0.15

0.00

0.85

0.60

0.27

0.17

0.23

0.08

2.1

1.9

2.4

2.2

0.5

3.2

3.0

0.4

0.1

8° 0°

0.13 0.10.20.4

DIMENSIONS (mm are the original dimensions)

Notes

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

2. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

0.40

0.15

0.21

0.19

SOT765-1 MO-187

02-06-07

w M

0.12

(A3)

detail X

v M

2.5 5 mm0

scale

VSSOP8: plastic very thin shrink small outline package; 8 leads; body width 2.3 mm

SOT765-1

pin 1 index

74AHC2G125; 74AHCT2G125

Dual buffer/line driver; 3-state

Fig 10. Package outline SOT765-1 (VSSOP8)

Product data sheet Rev. 3 — 6 May 2013 11 of 16

NXP Semiconductors

74AHC2G125; 74AHCT2G125

XSON8: plastic extremely thin small outline package; no leads; 8 terminals; body 3 x 2 x 0.5 mm

Dual buffer/line driver; 3-state

SOT996-2

terminal 1 index area

B A

detail X

0 1 2 mm

scale

Dimensions (mm are the original dimensions)

(1)

Unit

Outline version

SOT996-2

max nom

min

0.5

A1b

0.05

0.00

DEee1LL1L2v

0.35

2.1

3.1

0.15

1.9

IEC JEDEC JEITA

0.5 1.5

2.9

0.5

0.3

References

0.15

0.05

0.6

0.4

0.1

0.05

0.1

sot996-2_po

European projection

Issue date

07-12-21 12-11-20

Fig 11. Package outline SOT996-2 (XSON8)

Product data sheet Rev. 3 — 6 May 2013 12 of 16

NXP Semiconductors

14. Abbreviations

74AHC2G125; 74AHCT2G125

Dual buffer/line driver; 3-state

Table 11. Abbreviations

Acronym Description

CMOS Complementary Metal Oxide Semiconductor CDM Charged Device Model DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model TTL Transistor-Transistor Logic

15. Revision history

Table 12. Revision history

Document ID Release date Data sheet status Change

notice

74AHC_AHCT2G125 v.3 20130506 Product data sheet - 74AHC_AHCT2G125 v.2 Modifications:

74AHC_AHCT2G125 v.2 20081222 Product data sheet - 74AHC_AHCT2G125 v.1 Modifications:

• For type number 74AHC2G125GD and 74AHCT2G125GD XSON8U has changed to

XSON8.

• The format of this data sheet has been redesigned to comply with the new identity

guidelines of NXP Semiconductors.

• Legal texts have been adapted to the new company name where appropriate.

• Added type number 74AHC2G125GD and 74AHCT2G125GD (XSON8U package).

74AHC_AHCT2G125 v.1 20040113 Product specification - -

Supersedes

Product data sheet Rev. 3 — 6 May 2013 13 of 16

NXP Semiconductors

74AHC2G125; 74AHCT2G125

Dual buffer/line driver; 3-state

16. Legal information

16.1 Data sheet status

Document status

Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification.

[1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since thi s document w as publish ed and ma y diffe r in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

[1][2]

Product status

[3]

Definition

16.2 Definitions

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information.

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be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. NXP Semiconductors takes no responsibility for the content in this document if provided by an information source outside of NXP Semiconductors.

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Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device.

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, unless otherwise

Product data sheet Rev. 3 — 6 May 2013 14 of 16

NXP Semiconductors

74AHC2G125; 74AHCT2G125

Dual buffer/line driver; 3-state

Export control — This document as well as the item(s) described herein

may be subject to export control regulations. Export might require a prior authorization from competent authorities.

Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It i s neit her qua lif ied nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications.

In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, custome r (a) shall use the product without NXP Semiconductors’ warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond

NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, da mages or failed produ ct claims result ing from custome r design and use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications.

Translations — A non-English (t ranslated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions.

16.4 Trademarks

Notice: All referenced brands, prod uct names, service names and trademarks are the property of their respective owners.

17. Contact information

For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com

Product data sheet Rev. 3 — 6 May 2013 15 of 16

NXP Semiconductors

74AHC2G125; 74AHCT2G125

18. Contents

1 General description. . . . . . . . . . . . . . . . . . . . . . 1

2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1

3 Ordering information. . . . . . . . . . . . . . . . . . . . . 1

4 Marking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

5 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2

6 Pinning information. . . . . . . . . . . . . . . . . . . . . . 2

6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3

7 Functional description . . . . . . . . . . . . . . . . . . . 3

8 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 3

9 Recommended operating conditions. . . . . . . . 4

10 Static characteristics. . . . . . . . . . . . . . . . . . . . . 4

11 Dynamic characteristics . . . . . . . . . . . . . . . . . . 5

12 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

13 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 10

14 Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 13

15 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 13

16 Legal information. . . . . . . . . . . . . . . . . . . . . . . 14

16.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 14

16.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

16.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 14

16.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 15

17 Contact information. . . . . . . . . . . . . . . . . . . . . 15

18 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Dual buffer/line driver; 3-state

Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’.

For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com

Document identifier: 74AHC_AHCT2G125

Date of release: 6 May 2013

NXP 74AHC2G125DC, 74AHC2G125DP, 74AHC2G125GD, 74AHCT2G125DC, 74AHCT2G125DP Schematic [ru]

Specifications and Main Features

Frequently Asked Questions

User Manual

1. General description

2. Features and benefits

3. Ordering information

4. Marking

5. Functional diagram

6. Pinning information

6.1 Pinning

6.2 Pin description

7. Functional description

8. Limiting values

9. Recommended operating conditions

10. Static characteristics

11. Dynamic characteristics

12. Waveforms

13. Package outline

14. Abbreviations

15. Revision history

16. Legal information

16.1 Data sheet status

16.2 Definitions

16.3 Disclaimers

16.4 Trademarks

17. Contact information

18. Contents