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74AHC2G125DC
Schematic [ru]
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NXP 74AHC2G125DC, 74AHC2G125DP, 74AHC2G125GD, 74AHCT2G125DC, 74AHCT2G125DP Schematic [ru]

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74AHC2G125; 74AHCT2G125
Dual buffer/line driver; 3-state
Rev. 3 — 6 May 2013 Product data sheet

1. General description

The 74AHC2G125 and 74AHCT2G125 are high-speed Si-gate CMOS devices. They provide a dual non-inverting buffer/line driver with 3-state output. The 3-state output is controlled by the output enable input (nOE a high-impedance OFF-state.
The AHC device has CMOS input switching levels and supply voltage range 2 V to 5.5 V. The AHCT device has TTL input switching levels and supply voltage range 4.5 V to 5.5 V.

2. Features and benefits

Symmetrical output impedanceHigh noise immunityLow power dissipationBalanced propagation delaysMultiple package optionsESD protection:
HBM JESD22-A114E: exceeds 2000 VMM JESD22-A115-A: exceeds 200 VCDM JESD22-C101C: exceeds 1000 V
Specifie d from 40 C to +125 C
). A HIGH at nOE causes the output to assume

3. Ordering information

Table 1. Ordering information
Type number Package
74AHC2G125DP 40 C to +125 C TSSOP8 plastic thin shrink small outline package; 8 leads; 74AHCT2G125DP 74AHC2G125DC 40 C to +125 C VSSOP8 plastic very thin shrink small outline package; 74AHCT2G125DC 74AHC2G125GD 40 C to +125 C XSON8 plastic extremely thin small outline package; no 74AHCT2G125GD
Temperature range Name Description Version
body width 3 mm; lead length 0.5 mm
8 leads; body width 2.3 mm
leads; 8 terminals; body 3 2 0.5 mm
SOT505-2
SOT765-1
SOT996-2
NXP Semiconductors
mce185
1A 1Y
2
1
6
1OE
2A 2Y
5
7
3
2OE
mce186
1
1
2
6
2
EN1
7
3
5
EN2
mna227
nOE
nA
nY
74AHC2G125
74AHCT2G125
1OE V
CC
1A 2OE 2Y 1Y
GND 2A
001aaj260
1 2 3 4
6 5
8 7
001aaj261
74AHC2G125
74AHCT2G125
Transparent top view
8
7
6
5
1
2
3
4
1OE
1A
2Y
GND
V
CC
2OE
1Y
2A

4. Marking

74AHC2G125; 74AHCT2G125
Dual buffer/line driver; 3-state
Table 2. Marking codes
Type number Marking
74AHC2G125DP A25 74AHCT2G125DP C25 74AHC2G125DC A25 74AHCT2G125DC C25 74AHC2G125GD A25 74AHCT2G125GD C25

5. Functional diagram

Fig 1. Logic symbol Fig 2. IEC logic symbol Fig 3. Logic diagram (one buffer)

6. Pinning information

6.1 Pinning

Fig 4. Pin configuration SOT505-2 (TSSOP8) and
SOT765-1 (VSSOP8)
Fig 5. Pin configuration SOT996-2 (XSON8)
74AHC_AHCT2G125 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 3 — 6 May 2013 2 of 16
NXP Semiconductors
74AHC2G125; 74AHCT2G125
Dual buffer/line driver; 3-state

6.2 Pin description

Table 3. Pin description
Symbol Pin Description
, 2OE 1, 7 output enable input (active LOW)
1OE 1A, 2A 2, 5 data input GND 4 ground (0 V) 1Y, 2Y 6 , 3 data output V
CC
8 supply voltage

7. Functional description

Table 4. Function table
Control Input Output nOE nA nY
LLL LHH HXZ
[1]
[1] H = HIGH voltage level; L = LOW voltage level; X = don’t care; Z = high-impedance OFF-state.

8. Limiting values

Table 5. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Min Max Unit
V
CC
V
I
I
IK
I
OK
I
O
I
CC
I
GND
T
stg
P
tot
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed. [2] For TSSOP8 package: above 55 C the value of P
For VSSOP8 package: above 110 C the value of P For XSON8 package: above 45 C the value of P
supply voltage 0.5 +7.0 V input voltage 0.5 +7.0 V input clamping current VI < 0.5 V output clamping current VO < 0.5 V or VO>VCC+0.5V output current 0.5 V < VO <VCC+0.5V - 25 mA supply current - 75 mA ground current 75 - mA storage temperature 65 +150 C total power dissipation T
[1]
20 - mA
[1]
- 20 mA
= 40 C to +125 C
amb
derates linearly with 2.5 mW/K.
tot
derates linearly with 8 mW/K.
tot
derates linearly with 2.4 mW/K.
tot
[2]
- 250 mW
74AHC_AHCT2G125 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 3 — 6 May 2013 3 of 16
NXP Semiconductors
74AHC2G125; 74AHCT2G125

9. Recommended operating conditions

Dual buffer/line driver; 3-state
Table 6. Recommended operating conditions
Voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions 74AHC2G125 74AHCT2G125 Unit
Min Typ Max Min Typ Max
V
CC
V
I
V
O
T
amb
t/V input transition rise
supply voltage 2.0 5.0 5.5 4.5 5.0 5.5 V input voltage 0 - 5.5 0 - 5.5 V output voltage 0 - V
CC
0-VCCV
ambient temperature 40 +25 +125 40 +25 +125 C
= 3.3 V 0.3 V - - 100 - - - ns/V
V
and fall rate
CC
= 5.0 V 0.5 V - - 20 - - 20 ns/V
V
CC

10. Static characteristics

Table 7. Static characteristics
Voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions 25 C 40 C to +85 C 40 C to +125 C Unit
74AHC2G125
V
IH
HIGH-level input voltage
V
IL
LOW-level input voltage
V
OH
HIGH-level output voltage
V
OL
LOW-level output voltage
I
OZ
OFF-state output current
I
I
input leakage current
I
CC
supply current VI=VCCor GND; IO = 0 A;
Min Typ Max Min Max Min Max
V
= 2.0 V 1.5 - - 1.5 - 1.5 - V
CC
= 3.0 V 2.1 - - 2.1 - 2.1 - V
V
CC
= 5.5 V 3.85 - - 3.85 - 3.85 - V
V
CC
V
= 2.0 V - - 0.5 - 0.5 - 0.5 V
CC
= 3.0 V - - 0.9 - 0.9 - 0.9 V
V
CC
= 5.5 V - - 1.65 - 1.65 - 1.65 V
V
CC
VI= VIH or V
IL
IO= 50 A; VCC= 2.0 V 1.9 2.0 - 1.9 - 1.9 - V
= 50 A; VCC= 3.0 V 2.9 3.0 - 2.9 - 2.9 - V
I
O
= 50 A; VCC= 4.5 V 4.4 4.5 - 4.4 - 4.4 - V
I
O
= 4.0 mA; VCC= 3.0 V 2.58 - - 2.48 - 2.40 - V
I
O
= 8.0 mA; VCC= 4.5 V 3.94 - - 3.8 - 3.70 - V
I
O
VI= VIH or V
IL
IO= 50 A; VCC= 2.0 V - 0 0.1 - 0.1 - 0.1 V
= 50 A; VCC= 3.0 V - 0 0.1 - 0.1 - 0.1 V
I
O
= 50 A; VCC= 4.5 V - 0 0.1 - 0.1 - 0.1 V
I
O
= 4.0 mA; VCC= 3.0 V - - 0.36 - 0.44 - 0.55 V
I
O
= 8.0 mA; VCC= 4.5 V - - 0.36 - 0.44 - 0.55 V
I
O
VI=VCC or GND;
=5.5V
V
CC
VI= 5.5 V or GND;
=0Vto5.5V
V
CC
- - 0.25 - 2.5 - 10 A
- - 0.1 - 1.0 - 2.0 A
- - 1.0 - 10 - 40 A
VCC= 5.5 V
74AHC_AHCT2G125 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 3 — 6 May 2013 4 of 16
NXP Semiconductors
74AHC2G125; 74AHCT2G125
Dual buffer/line driver; 3-state
Table 7. Static characteristics …continued
Voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions 25 C 40 C to +85 C 40 C to +125 C Unit
Min Typ Max Min Max Min Max
C
I
74AHCT2G125
V
IH
V
IL
V
OH
V
OL
I
OZ
I
I
I
CC
I
CC
C
I
input capacitance
HIGH-level
V
= 4.5 V to 5.5 V 2.0 - - 2.0 - 2.0 - V
CC
input voltage LOW-level
V
= 4.5 V to 5.5 V - - 0.8 - 0.8 - 0.8 V
CC
input voltage HIGH-level
output voltage
LOW-level output voltage
OFF-state output current
input leakage current
VI= VIH or VIL; VCC= 4.5 V
= 50 A 4.4 4.5 - 4.4 - 4.4 - V
I
O
= 8.0 mA 3.94 - - 3.8 - 3.70 - V
I
O
VI= VIH or VIL; VCC= 4.5 V
= 50 A - 0 0.1 - 0.1 - 0.1 V
I
O
= 8.0 mA - - 0.36 - 0.44 - 0.55 V
I
O
VI=VCC or GND; VCC=5.5V
VI= 5.5 V or GND; VCC=0Vto5.5V
supply current VI=VCCor GND; IO = 0 A;
= 5.5 V
V
CC
additional supply current
per input pin; VI=3.4V; other inputs at VCCor GND;
=0 A; VCC = 5.5 V
I
O
input capacitance
- 1.5 10 - 10 - 10 pF
- - 0.25 - 2.5 - 10 A
- - 0.1 - 1.0 - 2.0 A
- - 1.0 - 10 - 40 A
- - 1.35 - 1.5 - 1.5 mA
- 1.5 10 - 10 - 10 pF

11. Dynamic characteristics

Table 8. Dynamic characteristics
GND = 0 V; for test circuit see Figure 8.
Symbol Parameter Conditions 25 C 40 C to +85 C 40 C to +125 C Unit
74AHC2G125
t
pd
propagation delay
74AHC_AHCT2G125 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 3 — 6 May 2013 5 of 16
Min Typ Max Min Max Min Max
nA to nY; see Figure 6
VCC = 3.0 V to 3.6 V
[1] [2]
CL= 15 pF - 4.7 8.0 1.0 9.5 1.0 11.5 ns
= 50 pF - 6.6 11.5 1.0 13.0 1.0 14.5 ns
C
L
= 4.5 V to 5.5 V
V
CC
[3]
CL= 15 pF - 3.4 5.5 1.0 6.5 1.0 7.0 ns
= 50 pF - 4.8 7.5 1.0 8.5 1.0 9.5 ns
C
L
NXP Semiconductors
74AHC2G125; 74AHCT2G125
Dual buffer/line driver; 3-state
Table 8. Dynamic characteristics
…continued
GND = 0 V; for test circuit see Figure 8.
Symbol Parameter Conditions 25 C 40 C to +85 C 40 C to +125 C Unit
Min Typ Max Min Max Min Max
t
en
enable time nOE to nY; see Figure 7
VCC = 3.0 V to 3.6 V
[1] [2]
CL= 15 pF - 5.0 8.0 1.0 9.5 1.0 11.5 ns
= 50 pF - 6.9 11.5 1.0 13.0 1.0 14.5 ns
C
L
= 4.5 V to 5.5 V
V
CC
[3]
CL= 15 pF - 3.6 5.1 1.0 6.0 1.0 6.5 ns
= 50 pF - 4.9 7.5 1.0 8.5 1.0 9.5 ns
C
L
t
dis
disable time nOE to nY; see Figure 7
VCC = 3.0 V to 3.6 V
[1] [2]
CL= 15 pF - 6.0 9.7 1.0 11.5 1.0 12.5 ns
= 50 pF - 8.3 13.2 1.0 15.0 1.0 16.5 ns
C
L
= 4.5 V to 5.5 V
V
CC
[3]
CL= 15 pF - 4.1 6.8 1.0 8.0 1.0 8.5 ns
= 50 pF - 5.7 8.8 1.0 10.0 1.0 11.0 ns
C
L
C
PD
power dissipation capacitance
per buffer; CL=50pF;fi=1 MHz; VI=GNDtoV
CC
[4]
-9- - - - -pF
74AHCT2G125
t
pd
propagation delay
nA to nY; see Figure 6
VCC = 4.5 V to 5.5 V
[1] [3]
CL= 15 pF - 3.4 5.5 1.0 6.5 1.0 6.5 ns
= 50 pF - 4.8 7.5 1.0 8.5 1.0 8.5 ns
C
L
t
en
enable time nOE to nY; see Figure 7
VCC = 4.5 V to 5.5 V
[1] [3]
CL= 15 pF - 3.9 5.1 1.0 6.0 1.0 6.0 ns
= 50 pF - 5.1 7.5 1.0 8.5 1.0 8.5 ns
C
L
t
dis
disable time nOE to nY; see Figure 7
VCC = 4.5 V to 5.5 V
[1] [3]
CL= 15 pF - 4.5 6.8 1.0 8.0 1.0 8.0 ns
= 50 pF - 6.1 8.8 1.0 10.0 1.0 10.0 ns
C
L
74AHC_AHCT2G125 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 3 — 6 May 2013 6 of 16
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