NXP 74AHC1G00GV, 74AHC1G00GW, 74AHCT1G00GV, 74AHCT1G00GW Schematic [ru]

74AHC1G00; 74AHCT1G00

2-input NAND gate

Rev. 06 — 30 May 2007 Product data sheet

1. General description

74AHC1G00 and 74AHCT1G00 are high-speed Si-gate CMOS devices. They provide a
2-input NAND function.

The AHC device has CMOS input switching levels and supply voltage range 2 V to 5.5 V.
The AHCT device has TTL input switching levels and supply voltage range 4.5 V to 5.5 V.

2. Features

n Symmetrical output impedance
n High noise immunity
n Low power dissipation
n Balanced propagation delays
n SOT353-1 and SOT753 package options
n ESD protection:

u HBM JESD22-A114E: exceeds 2000 V
u MM JESD22-A115-A: exceeds 200 V
u CDM JESD22-C101C: exceeds 1000 V

n Specified from −40 °C to +125 °C

3. Ordering information

Table 1. Ordering information

Type number Package

Temperature range Name Description Version

74AHC1G00GW −40 °C to +125 °C TSSOP5 plastic thin shrink small outline package;
74AHCT1G00GW
74AHC1G00GV −40 °C to +125 °C SC-74A plastic surface-mounted package; 5 leads SOT753
74AHCT1G00GV

5 leads; body width 1.25 mm

SOT353-1

NXP Semiconductors

74AHC1G00; 74AHCT1G00

4. Marking

Table 2. Marking codes

Type number Marking

74AHC1G00GW AA
74AHC1G00GV A00
74AHCT1G00GW CA
74AHCT1G00GV C00

5. Functional diagram

2-input NAND gate

1

B

2

A

mna097

4

Y

1
2

&

mna098

4

B

A

Fig 1. Logic symbol Fig 2. IEC logic symbol Fig 3. Logic diagram

6. Pinning information

6.1 Pinning

74AHC1G00

74AHCT1G00

Fig 4. Pin configuration

1

BV

2

A

3

GND Y

001aaf092

5

CC

4

Y

mna099

6.2 Pin description

Table 3. Pin description

Symbol Pin Description

B 1 data input
A 2 data input
GND 3 ground (0 V)
Y 4 data output
V

CC

74AHC_AHCT1G00_6 © NXP B.V. 2007. All rights reserved.

Product data sheet Rev. 06 — 30 May 2007 2 of 11

5 supply voltage

NXP Semiconductors

74AHC1G00; 74AHCT1G00

2-input NAND gate

7. Functional description

Table 4. Function table

H = HIGH voltage level; L = LOW voltage level

Inputs Output
A B Y

LLH
LHH
HLH
HHL

8. Limiting values

Table 5. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol Parameter Conditions Min Max Unit

V
V
I

IK

I

OK

I

O

I

CC

I

GND

T
P

CC
I

stg
tot

supply voltage −0.5 +7.0 V
input voltage −0.5 +7.0 V
input clamping current VI < −0.5 V −20 - mA
output clamping current VO < −0.5 V or VO>VCC+ 0.5 V

[1]

- ±20 mA
output current −0.5 V < VO <VCC+ 0.5 V - ±25 mA
supply current - 75 mA
ground current −75 - mA
storage temperature −65 +150 °C
total power dissipation T

= −40 °C to +125 °C

amb

[2]

- 250 mW

[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] For both TSSOP5 and SC-74A packages: above 87.5 °C the value of P

derates linearly with 4.0 mW/K.

tot

9. Recommended operating conditions

Table 6. Recommended operating conditions

Voltages are referenced to GND (ground = 0 V).

Symbol Parameter Conditions 74AHC1G00 74AHCT1G00 Unit

Min Typ Max Min Typ Max

V

CC

V

I

V

O

T

amb

∆t/∆V input transition rise

74AHC_AHCT1G00_6 © NXP B.V. 2007. All rights reserved.

Product data sheet Rev. 06 — 30 May 2007 3 of 11

supply voltage 2.0 5.0 5.5 4.5 5.0 5.5 V
input voltage 0 - 5.5 0 - 5.5 V
output voltage 0 - V

CC

0-VCCV

ambient temperature −40 +25 +125 −40 +25 +125 °C

= 3.3 V ± 0.3 V - - 100 - - - ns/V

V

and fall rate

CC

= 5.0 V ± 0.5 V - - 20 - - 20 ns/V

V

CC

NXP Semiconductors

74AHC1G00; 74AHCT1G00

2-input NAND gate

10. Static characteristics

Table 7. Static characteristics

Voltages are referenced to GND (ground = 0 V).

Symbol Parameter Conditions 25 °C −40 °C to +85 °C −40 °C to +125 °C Unit

Min Typ Max Min Max Min Max

For type 74AHC1G00

V

IH

HIGH-level
input voltage

V

IL

LOW-level
input voltage

V

OH

HIGH-level
output voltage

V

OL

LOW-level
output voltage

I

I

input leakage
current

I

CC

C

I

supply current VI=VCCor GND; IO = 0 A;

input
capacitance

For type 74AHCT1G00

V

IH

HIGH-level
input voltage

V

IL

LOW-level
input voltage

V

OH

HIGH-level
output voltage

V

OL

LOW-level
output voltage

I

I

input leakage
current

VCC= 2.0 V 1.5 - - 1.5 - 1.5 - V

= 3.0 V 2.1 - - 2.1 - 2.1 - V

V

CC

= 5.5 V 3.85 - - 3.85 - 3.85 - V

V

CC

VCC= 2.0 V - - 0.5 - 0.5 - 0.5 V

= 3.0 V - - 0.9 - 0.9 - 0.9 V

V

CC

= 5.5 V - - 1.65 - 1.65 - 1.65 V

V

CC

VI= VIH or V

IL

IO= −50 µA; VCC= 2.0 V 1.9 2.0 - 1.9 - 1.9 - V

= −50 µA; VCC= 3.0 V 2.9 3.0 - 2.9 - 2.9 - V

I

O

= −50 µA; VCC= 4.5 V 4.4 4.5 - 4.4 - 4.4 - V

I

O

= −4.0 mA; VCC= 3.0 V 2.58 - - 2.48 - 2.40 - V

I

O

= −8.0 mA; VCC= 4.5 V 3.94 - - 3.8 - 3.70 - V

I

O

VI= VIH or V

IL

IO= 50 µA; VCC= 2.0 V - 0 0.1 - 0.1 - 0.1 V

= 50 µA; VCC= 3.0 V - 0 0.1 - 0.1 - 0.1 V

I

O

= 50 µA; VCC= 4.5 V - 0 0.1 - 0.1 - 0.1 V

I

O

= 4.0 mA; VCC= 3.0 V - - 0.36 - 0.44 - 0.55 V

I

O

= 8.0 mA; VCC= 4.5 V - - 0.36 - 0.44 - 0.55 V

I

O

VI= 5.5 V or GND;
V

= 0 V to 5.5 V

CC

- - 0.1 - 1.0 - 2.0 µA

- - 1.0 - 10 - 40 µA

V

= 5.5 V

CC

- 1.5 10 - 10 - 10 pF

VCC= 4.5 V to 5.5 V 2.0 - - 2.0 - 2.0 - V

VCC= 4.5 V to 5.5 V - - 0.8 - 0.8 - 0.8 V

VI= VIH or VIL; VCC= 4.5 V

= −50 µA 4.4 4.5 - 4.4 - 4.4 - V

I

O

= −8.0 mA 3.94 - - 3.8 - 3.70 - V

I

O

VI= VIH or VIL; VCC= 4.5 V

= 50 µA - 0 0.1 - 0.1 - 0.1 V

I

O

= 8.0 mA - - 0.36 - 0.44 - 0.55 V

I

O

VI= 5.5 V or GND;
V

= 0 V to 5.5 V

CC

- - 0.1 - 1.0 - 2.0 µA

74AHC_AHCT1G00_6 © NXP B.V. 2007. All rights reserved.

Product data sheet Rev. 06 — 30 May 2007 4 of 11

NXP Semiconductors

74AHC1G00; 74AHCT1G00

2-input NAND gate

Table 7. Static characteristics

…continued

Voltages are referenced to GND (ground = 0 V).

Symbol Parameter Conditions 25 °C −40 °C to +85 °C −40 °C to +125 °C Unit

Min Typ Max Min Max Min Max

I

∆I

C

CC

CC

I

supply current VI=VCCor GND; IO = 0 A;

V

= 5.5 V

CC

additional
supply current

per input pin; VI= 3.4 V;
other inputs at V
I

= 0 A; VCC = 5.5 V

O

or GND;

CC

input

- - 1.0 - 10 - 40 µA

- - 1.35 - 1.5 - 1.5 mA

- 1.5 10 - 10 - 10 pF

capacitance

11. Dynamic characteristics

Table 8. Dynamic characteristics

GND = 0 V; tr = tf =≤ 3.0 ns. For test circuit see Figure 6.

Symbol Parameter Conditions 25 °C −40 °C to +85 °C −40 °C to +125 °C Unit

Min Typ Max Min Max Min Max

For type 74AHC1G00

t

pd

propagation
delay

C

PD

power
dissipation
capacitance

For type 74AHCT1G00

t

pd

propagation
delay

C

PD

power
dissipation
capacitance

A and B to Y; see Figure 5

VCC = 3.0 V to 3.6 V

CL= 15 pF - 4.5 7.9 1.0 9.5 1.0 10.5 ns

= 50 pF - 6.5 11.4 1.0 13.0 1.0 14.5 ns

C

L

= 4.5 V to 5.5 V

V

CC

CL= 15 pF - 3.5 5.5 1.0 6.5 1.0 7.0 ns

= 50 pF - 4.9 7.5 1.0 8.5 1.0 9.5 ns

C

L

per buffer;
C

=50pF;f=1 MHz;

L

V

= GND to V

I

CC

A and B to Y;
see

Figure 5;

V

= 4.5 V to 5.5 V

CC

CL= 15 pF - 3.6 6.2 1.0 7.1 1.0 8.0 ns

= 50 pF - 5.0 7.9 1.0 9.0 1.0 10.0 ns

C

L

per buffer;
V

= GND to V

I

CC

[1]
[2]

[3]

[4]

-17- - - - - pF

[1]
[3]

[4]

-18- - - - - pF

[1] tpd is the same as t
[2] Typical values are measured at VCC = 3.3 V.
[3] Typical values are measured at VCC = 5.0 V.
[4] CPDis used to determine the dynamic power dissipation PD(µW).

PD=CPD× V
fi= input frequency in MHz;
fo= output frequency in MHz;
CL= output load capacitance in pF;
VCC= supply voltage in Volts.

74AHC_AHCT1G00_6 © NXP B.V. 2007. All rights reserved.

Product data sheet Rev. 06 — 30 May 2007 5 of 11

CC

and t

PLH

2

× fi+ ∑ (CL× V

PHL

.

2

CC

× fo) where:

NXP Semiconductors

12. Waveforms

74AHC1G00; 74AHCT1G00

2-input NAND gate

A, B input

Y output

V

M

t

PHL

V

M

t

PLH

mna106

Measurement points are given in Table 9.

Fig 5. The inputs (A and B) to output (Y) propagation delays

Table 9. Measurement point

Type Input Output

V

I

74AHC1G00 GND to V

CC

V

M

0.5 × V

CC

V

M

0.5 × V

74AHCT1G00 GND to 3.0 V 1.5 V 0.5 × V

V

CC

PULSE

GENERATOR

V

I

R

T

DUT

V

O

C

L

mna101

CC
CC

Test data is given in Table 8. Definitions for test circuit:
CL = Load capacitance including jig and probe capacitance.
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.

Fig 6. Load circuitry for switching times

74AHC_AHCT1G00_6 © NXP B.V. 2007. All rights reserved.

Product data sheet Rev. 06 — 30 May 2007 6 of 11

NXP Semiconductors

13. Package outline

74AHC1G00; 74AHCT1G00

2-input NAND gate

TSSOP5: plastic thin shrink small outline package; 5 leads; body width 1.25 mm

D

y

Z

5

4

13

e

e

1

w M

b

p

c

A

2

E

H

E

A

1

L

p

L

detail X

SOT353-1

A

X

v M

A

(A3)

A

θ

1.5 3 mm0

scale

DIMENSIONS (mm are the original dimensions)

A

A

UNIT

max.

mm

1.1

Note

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

OUTLINE
VERSION

SOT353-1 MO-203 SC-88A

A2A3b

1

0.101.0

0.8

p

0.30

0.15

0.15

IEC JEDEC JEITA

ceD

0.25

0.08

REFERENCES

(1)E(1)

2.25

1.85

1.35

1.15

0.65

e

1.3

LH

1

E

2.25

2.0

L

p

0.46

0.21

PROJECTION

EUROPEAN

wyv

0.1 0.10.30.425

(1)

Z

0.60

0.15

ISSUE DATE

00-09-01
03-02-19

θ

7°
0°

Fig 7. Package outline SOT353-1 (TSSOP5)

74AHC_AHCT1G00_6 © NXP B.V. 2007. All rights reserved.

Product data sheet Rev. 06 — 30 May 2007 7 of 11

NXP Semiconductors

74AHC1G00; 74AHCT1G00

2-input NAND gate

Plastic surface-mounted package; 5 leads SOT753

D

y

E

H

E

AB

X

v M

A

45

Q

A

A

1

c

132

e

detail X

b

p

wBM

L

p

0 1 2 mm

scale

DIMENSIONS (mm are the original dimensions)

A

UNIT

A

1.1

mm

0.9

OUTLINE
VERSION

SOT753 SC-74A

0.100

0.013

b

cD

p

1

0.40

0.26

0.25

0.10

IEC JEDEC JEITA

3.1

2.7

E

1.7

1.3

REFERENCES

e

0.95

H

3.0

2.5

L

Qywv

p

E

0.6

0.2

0.33

0.23

0.2 0.10.2

EUROPEAN

PROJECTION

ISSUE DATE

02-04-16
06-03-16

Fig 8. Package outline SOT753 (SC-74A)

74AHC_AHCT1G00_6 © NXP B.V. 2007. All rights reserved.

Product data sheet Rev. 06 — 30 May 2007 8 of 11

NXP Semiconductors

74AHC1G00; 74AHCT1G00

2-input NAND gate

14. Abbreviations

Table 10. Abbreviations

Acronym Description

CDM Charged Device Model
DUT Device Under Test
ESD ElectroStatic Discharge
HBM Human Body Model
MM Machine Model
TTL Transistor-Transistor Logic

15. Revision history

Table 11. Revision history

Document ID Release date Data sheet status Change notice Supersedes

74AHC_AHCT1G00_6 20070530 Product data sheet - 74AHC_AHCT1G00_5
Modifications:

74AHC_AHCT1G00_5 20020527 Product specification - 74AHC_AHCT1G00_4
74AHC_AHCT1G00_4 20020227 Product specification - 74AHC_AHCT1G00_3
74AHC_AHCT1G00_3 20010131 Product specification - 74AHC_AHCT1G00_2
74AHC_AHCT1G00_2 19990127 Product specification - 74AHC_AHCT1G00_N_1
74AHC_AHCT1G00_N_1 19981125 Preliminary specification - -

• The format of this data sheet has been redesigned to comply with the new identity

guidelines of NXP Semiconductors.

• Legal texts have been adapted to the new company name where appropriate.

• Package SOT353 changed to SOT353-1 in Section 3 and Section 13.

• Quick reference data and Soldering sections removed.

74AHC_AHCT1G00_6 © NXP B.V. 2007. All rights reserved.

Product data sheet Rev. 06 — 30 May 2007 9 of 11

NXP Semiconductors

16. Legal information

16.1 Data sheet status

74AHC1G00; 74AHCT1G00

2-input NAND gate

Document status

Objective [short] data sheet Development This document contains data from the objective specification for product development.
Preliminary [short] data sheet Qualification This document contains data from the preliminary specification.
Product [short] data sheet Production This document contains the product specification.

[1] Please consult the most recently issued document before initiating or completing a design.
[2] The term ‘short data sheet’ is explained in section “Definitions”.
[3] Theproduct statusof device(s) described in this document may have changed since this document was published and may differin case of multiple devices. Thelatest product status

information is available on the Internet at URL

[1][2]

Product status

16.2 Definitions

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information includedherein and shall haveno liability forthe consequences of
use of such information.

Short data sheet — A short data sheet is an extract from a full data sheet
with thesame product type number(s)and title. Ashort datasheet is intended
for quickreference only and should notbe relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.

16.3 Disclaimers

General — Information in this document is believed to be accurate and

reliable. However,NXP Semiconductors does not giveany representations or
warranties, expressed or implied, asto the accuracy or completenessof such
information and shall have no liability for the consequences of use of such
information.

Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This documentsupersedes and replaces all information supplied prior
to the publication hereof.

Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or

[3]

http://www.nxp.com.

Definition

malfunction ofa NXP Semiconductorsproduct can reasonablybe expected to
result in personal injury, death or severe property or environmental damage.
NXP Semiconductors accepts no liability for inclusion and/or use of NXP
Semiconductors products in such equipment or applications and therefore
such inclusion and/or use is at the customer’s own risk.

Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.

Limiting values — Stress above one or more limiting values (as defined in
the Absolute MaximumRatings System of IEC 60134) maycause permanent
damage to thedevice. Limiting valuesare stress ratings onlyand operation of
the device at these or any other conditions above those given in the
Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may affect device reliability.

Terms and conditions of sale — NXP Semiconductors products are sold
subject to the general terms and conditions of commercial sale, as published
at

http://www.nxp.com/profile/terms, including those pertaining to warranty,

intellectual property rights infringement and limitation of liability, unless
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of
any inconsistency or conflict between information in this document and such
terms and conditions, the latter will prevail.

No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or the
grant, conveyance or implication ofany license under any copyrights, patents
or other industrial or intellectual property rights.

16.4 Trademarks

Notice: Allreferenced brands,product names, service namesand trademarks
are the property of their respective owners.

17. Contact information

For additional information, please visit: http://www.nxp.com
For sales office addresses, send an email to: [e-mail]

74AHC_AHCT1G00_6 © NXP B.V. 2007. All rights reserved.

Product data sheet Rev. 06 — 30 May 2007 10 of 11

NXP Semiconductors

18. Contents

1 General description . . . . . . . . . . . . . . . . . . . . . . 1

2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

3 Ordering information. . . . . . . . . . . . . . . . . . . . . 1

4 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

5 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2

6 Pinning information. . . . . . . . . . . . . . . . . . . . . . 2

6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 2

7 Functional description . . . . . . . . . . . . . . . . . . . 3

8 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 3

9 Recommended operating conditions. . . . . . . . 3

10 Static characteristics. . . . . . . . . . . . . . . . . . . . . 4

11 Dynamic characteristics . . . . . . . . . . . . . . . . . . 5

12 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

13 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 7

14 Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . . 9

15 Revision history. . . . . . . . . . . . . . . . . . . . . . . . . 9

16 Legal information. . . . . . . . . . . . . . . . . . . . . . . 10

16.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 10

16.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

16.3 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

16.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 10

17 Contact information. . . . . . . . . . . . . . . . . . . . . 10

18 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

74AHC1G00; 74AHCT1G00

2-input NAND gate

Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.

© NXP B.V. 2007. All rights reserved.

For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [e-mail]

Document identifier: 74AHC_AHCT1G00_6

Date of release: 30 May 2007