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ISD94100 Series Technical Reference Manual
ISD ARM® Cortex®-M4F SoC
ISD94100 Series
Technical Reference Manual
The information described in this document is the exclusive intellectual property of
Nuvoton Technology Corporation and shall not be reproduced without permission from Nuvoton.
Nuvoton is providing this document only for reference purposes of microcontroller based system design.
Nuvoton assumes no responsibility for errors or omissions.
All data and specifications are subject to change without notice.
For additional information or questions, please contact: Nuvoton Technology Corporation.
ISD94100 SERIES TECHNICAL REFERENCE MANUAL
www.nuvoton.com
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ISD94100 Series Technical Reference Manual
TABLE OF CONTENTS
1 GENERAL DESCRIPTION ............................................................ 18
2 FEATURES .............................................................................. 19
2.1 ISD94100 Series Features ................................................................ 19
3 ABBREVIATIONS ....................................................................... 26
3.1 Abbreviations ................................................................................ 26
4 PARTS INFORMATION LIST AND PIN CONFI GURATION ..................... 28
4.1 Parts Information ............................................................................ 28
4.2 Ordering Information ....................................................................... 29
4.3 Pin Configuration ............................................................................ 31
4.3.1 QFN48 (6x6 mm) Pin Diagram ................................................................... 31
4.3.2 LQFP64 (7x7 mm) Pin Diagram .................................................................. 32
4.3.3 LQFP64 (10x10 mm) Pin Diagram ............................................................... 33
4.4 Pin Description .............................................................................. 34
4.5 GPIO Alternate Function Summary ...................................................... 43
ISD94100 SERIES TECHNICAL REFERENCE MANUAL
5 BLOCK DIAGRAM ...................................................................... 45
5.1 ISD94100 Series Block Diagram ......................................................... 45
6 FUNCTIONAL DESCRIPTION ........................................................ 46
6.1 ARM® Cortex®-M4 Core .................................................................... 46
6.2 System Manager ............................................................................ 49
6.2.1 Overview ............................................................................................. 49
6.2.2 System Reset........................................................................................ 49
6.2.3 System Power Distribution ........................................................................ 53
6.2.4 Power Modes ........................................................................................ 54
6.2.5 Power Modes Settings and Wake-up Sources ................................................. 56
6.2.6 Brown-out Detector and Low Voltage Reset Controller Configuration ..................... 61
6.2.7 System Memory Map ............................................................................... 62
6.2.8 SRAM Memory Organization ..................................................................... 63
6.2.9 HIRC Auto Trim ..................................................................................... 64
6.2.10 Register Map...................................................................................... 66
6.2.11 Register Description ............................................................................. 67
6.2.12 System Timer (SysTick) ......................................................................... 98
6.2.13 Nested Vectored Interrupt Controller (NVIC) .............................................. 102
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6.2.14 System Control Register ...................................................................... 131
6.3 Clock Controller ............................................................................ 140
6.3.1 Overview ........................................................................................... 140
6.3.2 Clock Generator ................................................................................... 142
6.3.3 System Clock and SysTick Clock .............................................................. 143
6.3.4 Peripheral Clock .................................................................................. 145
6.3.5 Power-down Mode Clock ........................................................................ 145
6.3.6 Clock Output ....................................................................................... 145
6.3.7 Clock Setting Limitation .......................................................................... 146
6.3.8 Register Map ...................................................................................... 147
6.3.9 Register Description .............................................................................. 149
6.4 Flash Memory Controller (FMC) ......................................................... 191
6.4.1 Overview ........................................................................................... 191
6.4.2 Features ............................................................................................ 191
6.4.3 Block Diagram ..................................................................................... 192
6.4.4 Functional Description ........................................................................... 194
6.4.5 Register Map ...................................................................................... 215
6.4.6 Register Description .............................................................................. 217
6.5 General Purpose I/O (GPIO) ............................................................. 240
6.5.1 Overview ........................................................................................... 240
6.5.2 Features ............................................................................................ 240
6.5.3 Block Diagram ..................................................................................... 240
6.5.4 Basic Configuration ............................................................................... 241
6.5.5 Functional Description ........................................................................... 242
6.5.6 Register Map ...................................................................................... 246
6.5.7 Register Description .............................................................................. 248
6.6 PDMA Controller (PDMA) ................................................................ 264
6.6.1 Overview ........................................................................................... 264
6.6.2 Features ............................................................................................ 264
ISD94100 SERIES TECHNICAL REFERENCE MANUAL
6.6.3 Block Diagram ..................................................................................... 264
6.6.4 Basic Configuration ............................................................................... 265
6.6.5 Functional Description ........................................................................... 265
6.6.6 Register Map ...................................................................................... 273
6.6.7 Register Description .............................................................................. 278
6.7 Timer Controller (TMR) ................................................................... 338
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6.7.1 Overview ........................................................................................... 338
6.7.2 Features ............................................................................................ 338
6.7.3 Block Diagram ..................................................................................... 340
6.7.4 Basic Configuration ............................................................................... 344
6.7.5 Timer Functional Description ................................................................... 345
6.7.6 PWM Functional Description .................................................................... 350
6.7.7 Register Map ...................................................................................... 363
6.7.8 Register Description .............................................................................. 368
6.8 PWM Generator and Capture Timer (PWM) .......................................... 402
6.8.1 Overview ........................................................................................... 402
6.8.2 Features ............................................................................................ 402
6.8.3 Block Diagram ..................................................................................... 404
6.8.4 Basic Configuration ............................................................................... 407
6.8.5 Functional Description ........................................................................... 408
6.8.6 Register Map ...................................................................................... 439
6.8.7 Register Description .............................................................................. 443
ISD94100 SERIES TECHNICAL REFERENCE MANUAL
6.9 Watchdog Timer (WDT)................................................................... 525
6.9.1 Overview ........................................................................................... 525
6.9.2 Features ............................................................................................ 525
6.9.3 Block Diagram ..................................................................................... 525
6.9.4 Basic Configuration ............................................................................... 525
6.9.5 Functional Description ........................................................................... 526
6.9.6 Register Map ...................................................................................... 529
6.9.7 Register Description .............................................................................. 530
6.10 Window Watchdog Timer (WWDT) ..................................................... 533
6.10.1 Overview ........................................................................................ 533
6.10.2 Features ......................................................................................... 533
6.10.3 Block Diagram .................................................................................. 533
6.10.4 Basic Configuration ............................................................................ 534
6.10.5 Functional Description ......................................................................... 534
6.10.6 Register Map.................................................................................... 538
6.10.7 Register Description ........................................................................... 539
6.11 Real Time Clock (RTC) ................................................................... 544
6.11.1 Overview ........................................................................................ 544
6.11.2 Features ......................................................................................... 544
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6.11.3 Block Diagram .................................................................................. 545
6.11.4 Basic Configuration ............................................................................ 545
6.11.5 Functional Description ......................................................................... 545
6.11.6 Register Map.................................................................................... 549
6.11.7 Register Description ........................................................................... 550
6.12 UART Interface Controller (UART) ...................................................... 566
6.12.1 Overview ........................................................................................ 566
6.12.2 Features ......................................................................................... 566
6.12.3 Block Diagram .................................................................................. 567
6.12.4 Basic Configuration ............................................................................ 570
6.12.5 Functional Description ......................................................................... 571
6.12.6 Register Map.................................................................................... 588
6.12.7 Register Description ........................................................................... 589
6.13 I2C Serial Interface Controller (I2C) ..................................................... 617
6.13.1 Overview ........................................................................................ 617
6.13.2 Features ......................................................................................... 617
6.13.3 Block Diagram .................................................................................. 617
6.13.4 Basic Configuration ............................................................................ 618
6.13.5 Functional Description ......................................................................... 619
6.13.6 Register Map.................................................................................... 650
6.13.7 Register Description ........................................................................... 652
6.14 Serial Peripheral Interface (SPI) ......................................................... 674
6.14.1 Overview ........................................................................................ 674
6.14.2 Features ......................................................................................... 674
6.14.3 Block Diagram .................................................................................. 676
6.14.4 Basic Configuration ............................................................................ 678
6.14.5 Functional Description ......................................................................... 680
6.14.6 Timing Diagram ................................................................................ 704
6.14.7 Programming Examples ...................................................................... 706
ISD94100 SERIES TECHNICAL REFERENCE MANUAL
6.14.8 Register Map.................................................................................... 708
6.14.9 Register Description ........................................................................... 710
6.15 CRC Controller (CRC) .................................................................... 746
6.15.1 Overview ........................................................................................ 746
6.15.2 Features ......................................................................................... 746
6.15.3 Block Diagram .................................................................................. 747
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6.15.4 Basic Configuration ............................................................................ 747
6.15.5 Functional Description ......................................................................... 747
6.15.6 Register Map.................................................................................... 749
6.15.7 Register Description ........................................................................... 750
6.16 Enhanced 12-bit Analog-to-Digital Converter (EADC) ............................... 755
6.16.1 Overview ........................................................................................ 755
6.16.2 Features ......................................................................................... 755
6.16.3 Block Diagram .................................................................................. 756
6.16.4 Basic Configuration ............................................................................ 756
6.16.5 Functional Description ......................................................................... 757
6.16.6 Register Map.................................................................................... 771
6.16.7 Register Description ........................................................................... 774
6.17 I2S Controller (I2S) ......................................................................... 801
6.17.1 Overview ........................................................................................ 801
6.17.2 Features ......................................................................................... 801
6.17.3 Block Diagram .................................................................................. 802
ISD94100 SERIES TECHNICAL REFERENCE MANUAL
6.17.4 Basic Configuration ............................................................................ 802
6.17.5 Functional Description ......................................................................... 803
6.17.6 Register Map.................................................................................... 814
6.17.7 Register Description ........................................................................... 815
6.18 USB 1.1 Device Controller (USBD) ..................................................... 833
6.18.1 Overview ........................................................................................ 833
6.18.2 Features ......................................................................................... 833
6.18.3 Block Diagram .................................................................................. 834
6.18.4 Basic Configuration ............................................................................ 834
6.18.5 Functional Description ......................................................................... 835
6.18.6 Register Map.................................................................................... 839
6.18.7 Register Description ........................................................................... 842
6.19 Digital Microphone Inputs (DMIC) ....................................................... 866
6.19.1 Overview ........................................................................................ 866
6.19.2 Features ......................................................................................... 866
6.19.3 Block Diagram .................................................................................. 866
6.19.4 Basic Configuration ............................................................................ 866
6.19.5 Functional Description ......................................................................... 867
6.19.6 Register Map.................................................................................... 871
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6.19.7 Register Description ........................................................................... 872
6.20 Voice Active Detection (VAD) ............................................................ 879
6.20.1 Overview ........................................................................................ 879
6.20.2 Features ......................................................................................... 879
6.20.3 Block Diagram .................................................................................. 879
6.20.4 Basic Configuration ............................................................................ 879
6.20.5 Functional Description ......................................................................... 879
6.20.6 Register Map.................................................................................... 885
6.20.7 Register Description ........................................................................... 886
6.21 Audio DPWM Modulator (DPWM) ....................................................... 897
6.21.1 Overview ........................................................................................ 897
6.21.2 Features ......................................................................................... 897
6.21.3 Block Diagram .................................................................................. 897
6.21.4 Basic Configuration ............................................................................ 897
6.21.5 Functional Description ......................................................................... 898
6.21.6 Register Map.................................................................................... 905
6.21.7 Register Description ........................................................................... 910
7 ELECTRICAL CHARACTERISTICS ................................................922
8 APPLICATION CIRCUIT ..............................................................923
9 PACKAGE DIMENSIONS ............................................................924
9.1 QFN 48L (6x6x0.8 mm3 Pitch 0.4 mm) ................................................. 924
9.2 LQFP 64L (7x7x1.4 mm footprint 2.0 mm) ............................................. 925
9.3 LQFP 64L (10x10x1.4 mm footprint 2.0 mm) ......................................... 926
10 REVISION HISTORY ..................................................................927
ISD94100 SERIES TECHNICAL REFERENCE MANUAL
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List of Figure
Figure 4.2-1 Ordering Information Scheme ................................................................................... 29
Figure 4.3-1 QFN48 (6x6 mm) Pin Diagram .................................................................................. 31
Figure 4.3-2 LQFP64 (7x7 mm) Pin Diagram ................................................................................ 32
Figure 4.3-3 LQFP64 (10x10 mm) Pin Diagram ............................................................................ 33
Figure 5.1-1 ISD94100 Series Block Diagram ............................................................................... 45
Figure 6.1-1 Cortex®-M4 Block Diagram ........................................................................................ 46
Figure 6.2-1 System Reset Sources .............................................................................................. 50
Figure 6.2-2 nRESET Reset Waveform ......................................................................................... 51
Figure 6.2-3 Brown-out Detector (BOD) Waveform ....................................................................... 52
Figure 6.2-4 ISD94100 Series Power Distribution Diagram .......................................................... 54
Figure 6.2-5 ISD94100 Series Power Mode State Machine .......................................................... 57
Figure 6.2-6 SRAM Block Diagram ................................................................................................ 63
Figure 6.2-7 SRAM Memory Organi zat ion ..................................................................................... 64
Figure 6.3-1 Clock Generator Global View Diagram .................................................................... 141
Figure 6.3-2 Clock Generator Block Diagram .............................................................................. 142
ISD94100 SERIES TECHNICAL REFERENCE MANUAL
Figure 6.3-3 System Clock Block Diagram .................................................................................. 143
Figure 6.3-4 HXT Stop Protect Procedure ................................................................................... 144
Figure 6.3-5 SysTick Clock Control Block Diagram ..................................................................... 144
Figure 6.3-6 Clock Output Block Diagram ................................................................................... 145
Figure 6.4-1 Flash Memory Controller Block Diagram ................................................................. 192
Figure 6.4-2 Memory Organization .............................................................................................. 194
Figure 6.4-3 Data Flash Shared with 512 KB APRM example .................................................... 194
Figure 6.4-4 Boot from LDROM with IAP support ........................................................................ 196
Figure 6.4-5 Boot from APROM with IAP support ........................................................................ 197
Figure 6.4-6 Boot from LDROM without IAP support ................................................................... 198
Figure 6.4-7 Boot from APROM without IAP support ................................................................... 198
Figure 6.4-8 ISP Procedure Example .......................................................................................... 201
Figure 6.4-9 flash 32-bit write procedure ..................................................................................... 203
Figure 6.4-10 Flash 64-bit write procedure .................................................................................. 204
Figure 6.4-11 Timeline comparison for write operations .............................................................. 205
Figure 6.4-12 Firmware in SRAM for Multi-word Programming ................................................... 205
Figure 6.4-13 Multi-word programming flow chart ....................................................................... 207
Figure 6.4-14 Fast Flash Programming Verification Flow ............................................................ 208
Figure 6.4-15 Verification Flow .................................................................................................... 209
Figure 6.4-16 Flash CRC32 Checksum Calculation .................................................................... 209
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Figure 6.4-17 Flash access cycle auto-tuning flow ...................................................................... 213
Figure 6.5-1 GPIO Controller Block Diagram ............................................................................... 241
Figure 6.5-2 Push-Pull Output ...................................................................................................... 242
Figure 6.5-3 Open-Drain Output .................................................................................................. 243
Figure 6.5-4 Quasi-Bidirectional I/O Mode ................................................................................... 243
Figure 6.5-5 GPIO Rising Edge Trigger Interrupt ........................................................................ 244
Figure 6.5-6 GPIO Falling Edge Trigger Interrupt ........................................................................ 245
Figure 6.6-1 PDMA Controller Block Diagram ............................................................................. 264
Figure 6.6-2 Descriptor Table Entry Structure ............................................................................. 265
Figure 6.6-3 Basic Mode Finite State Machine ............................................................................ 267
Figure 6.6-4 Descriptor Table Link List Structure ........................................................................ 268
Figure 6.6-5 Scatter-Gather Mode Finite State Machine ............................................................. 268
Figure 6.6-6 Example of Single Transfer Type and Burst Transfer Type in Basic Mode ............ 270
Figure 6.6-7 Example of PDMA Channel 0 Time-out Counter Operation .................................... 271
Figure 6.6-8 Stride Function Block Transfer ................................................................................ 271
Figure 6.7-1 Timer Controller Block Diagram .............................................................................. 340
Figure 6.7-2 Clock Source of Timer Controller ............................................................................ 341
Figure 6.7-3 PWM Generator Overview Block Diagram .............................................................. 342
Figure 6.7-4 PWM System Clock Source Control ........................................................................ 342
Figure 6.7-5 PWM Counter Clock Source Control ....................................................................... 343
Figure 6.7-6 PWM Independent Mod e Arc hitec t ur e Dia gram ...................................................... 343
Figure 6.7-7 PWM Complementary Mode Architecture Diagram ................................................ 344
Figure 6.7-8 Continuous Counting Mode ..................................................................................... 347
Figure 6.7-9 External Capture Mode ............................................................................................ 348
Figure 6.7-10 External Reset Counter Mode ......................................................................... 348
Figure 6.7-11 Internal Timer Trigger ............................................................................................ 349
Figure 6.7-12 Inter-Timer Trigger Capture Timing ....................................................................... 350
Figure 6.7-13 PWM Prescale Waveform in Up Count Type ........................................................ 351
Figure 6.7-14 PWM Up Count Type ............................................................................................. 351
Figure 6.7-15 PWM Down Count Type ........................................................................................ 352
Figure 6.7-16 PWM Up-Down Count Type .................................................................................. 352
ISD94100 SERIES TECHNICAL REFERENCE MANUAL
Figure 6.7-17 PWM Comparator Events in Up-Down Count Type .............................................. 353
Figure 6.7-18 Period Loading Mode with Up Count Type ............................................................ 354
Figure 6.7-19 Immediately Loading Mode with Up Count Type ................................................... 355
Figure 6.7-20 PWM Pulse Generation in Up-Down Count Type ................................................. 355
Figure 6.7-21 PWM Pulse Generation in Up Count Type ............................................................ 356
Figure 6.7-22 PWM Pulse Generation in Down Count Type ....................................................... 356
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Figure 6.7-23 PWM 0% to 100% Duty Cycle in Up Count Type and Up-Down Count Type ....... 357
Figure 6.7-24 PWM Independent Mode Output Waveform ......................................................... 358
Figure 6.7-25 PWM Complementary Mode Output Waveform .................................................... 358
Figure 6.7-26 PWMx_CH0 Output Control in Independent Mode ............................................... 358
Figure 6.7-27 PWMx_CH0 and PWMx_CH1 Output Control in Complementary Mode .............. 359
Figure 6.7-28 Dead-Time Insertion .............................................................................................. 359
Figure 6.7-29 PWM Output Mask Control Waveform .................................................................. 360
Figure 6.7-30 PWMx_CH0 and PWMx_CH1 Polarity Control with Dead-Time Insertion ............ 361
Figure 6.7-31 PWM Interrupt Architecture Di agram ..................................................................... 362
Figure 6.7-32 PWM Trigger ADC Block Diagram ........................................................................ 362
Figure 6.8-1 PWM Generator Overview Block Diagram .............................................................. 404
Figure 6.8-2 PWM System Clock Source Control ........................................................................ 404
Figure 6.8-3 PWM Clock Source Control ..................................................................................... 405
Figure 6.8-4 PWM Independent Mod e Arc hitec t ur e Dia gram ...................................................... 406
Figure 6.8-5 PWM Complementary Mode Architecture Diagram ................................................ 407
Figure 6.8-6 PWM0_CH0 Prescaler Waveform in Up Counter Type ........................................... 408
Figure 6.8-7 PWM0 Counter Waveform when set clear counter ................................................. 409
ISD94100 SERIES TECHNICAL REFERENCE MANUAL
Figure 6.8-8 PWM Up Counter Type............................................................................................ 409
Figure 6.8-9 PWM Down Counter Type ....................................................................................... 410
Figure 6.8-10 PWM Up-Down Counter Type ............................................................................... 411
Figure 6.8-11 PWM Compared point Events in Up-Down Counter Type .................................... 412
Figure 6.8-12 PWM Double Buffering Illustration ......................................................................... 413
Figure 6.8-13 Period Loading in Up-Count Mode ........................................................................ 414
Figure 6.8-14 Immediately Loading in Up-Count Mode ............................................................... 415
Figure 6.8-15 Window Loading in Up-Count Mode ...................................................................... 416
Figure 6.8-16 Center Loading in Up-Down-Count Mode ............................................................. 417
Figure 6.8-17 PWM One-shot Mode Output Waveform ............................................................... 418
Figure 6.8-18 PWM Pulse Generation ......................................................................................... 419
Figure 6.8-19 PWM 0% to 100% Pulse Generation ..................................................................... 419
Figure 6.8-20 PWM Independent Mode Waveform ..................................................................... 421
Figure 6.8-21 PWM Complementary Mode Waveform ................................................................ 421
Figure 6.8-22 PWM Group Function Waveform ........................................................................... 422
Figure 6.8-23 PWM SYNC_IN Noise Filter Block Diagram ......................................................... 423
Figure 6.8-24 PWM Counter Synchronous Function Block Diagram ........................................... 424
Figure 6.8-25 PWM Synchronous Function with Synchronize source from SYNC_IN Signal ..... 425
Figure 6.8-26 PWM0_CH0 Output Control in Independent Mode ............................................... 425
Figure 6.8-27 PWM0_CH0 and PWM0_CH1 Output Control in Complementary Mode .............. 426
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ISD94100 Series Technical Reference Manual
Figure 6.8-28 Dead-Time Insertion .............................................................................................. 427
Figure 6.8-29 Illustration of Mask Control Waveform ................................................................... 427
Figure 6.8-30 Brake Noise Filter Block Diagram .......................................................................... 428
Figure 6.8-31 Brake Block Diagram for PWM0_CH0 and PWM0_CH1 Pair ............................... 429
Figure 6.8-32 Edge Detector Waveform for PWM0_CH0 and PWM0_CH1 Pair ........................ 430
Figure 6.8-33 Level Detector Waveform for PWM0_CH0 and PWM0_CH1 Pair ........................ 430
Figure 6.8-34 Brake Source Block Diagram ................................................................................ 431
Figure 6.8-35 Brake System Fail Block Diagram ......................................................................... 431
Figure 6.8-36 Initial State and Polarity Control with Rising Edge Dead-Time Insertion .............. 432
Figure 6.8-37 PWM0_CH0 and PWM0_CH1 Pair Interrupt Architecture Diagram ...................... 433
Figure 6.8-38 PWM0_CH0 and PWM0_CH1 Pair Trigger EADC Block Diagram ....................... 434
Figure 6.8-39 PWM Trigger EADC in Up-Down Counter Type Timing Waveform ...................... 434
Figure 6.8-40 PWM0_CH0 Capture Block Diagram .................................................................... 435
Figure 6.8-41 Capture Operation Waveform ................................................................................ 436
Figure 6.8-42 Capture PDMA Operation Waveform of Channel 0 ............................................... 438
Figure 6.9-1 Watchdog Timer Block Diagram .............................................................................. 525
Figure 6.9-2 Watchdog Timer Clock Control ................................................................................ 526
Figure 6.9-3 Watchdog Timer Time-out Interval and Reset Period Timing ................................. 527
Figure 6.10-1 WWDT Block Diagram ........................................................................................... 533
Figure 6.10-2 WWDT Clock Control............................................................................................. 534
Figure 6.10-3 WWDT Reset and Reload Behavior ...................................................................... 535
Figure 6.10-4 WWDT Reload Counter When CNTDAT > CMPDAT ........................................... 536
Figure 6.10-5 WWDT Reload Counter When WWDT_CNT < WINCMP ..................................... 537
Figure 6.10-6 WWDT Interrupt and Reset Signals ...................................................................... 537
Figure 6.11-1 RTC Block Diagram ............................................................................................... 545
Figure 6.12-1 UART Clock Control Diagram ................................................................................ 567
Figure 6.12-2 UART Block Diagram............................................................................................. 568
Figure 6.12-3 Auto-Baud Rate Measurement .............................................................................. 574
Figure 6.12-4 Transmit Delay Time Operation ............................................................................. 575
Figure 6.12-5 UART nCTS Wake-up Case1 ................................................................................ 576
Figure 6.12-6 UART nCTS Wake-up Case2 ................................................................................ 576
ISD94100 SERIES TECHNICAL REFERENCE MANUAL
Figure 6.12-7 UART Data Wake-up ............................................................................................. 577
Figure 6.12-8 UART RX FIFO reached threshold wake-up ......................................................... 577
Figure 6.12-9 UART RS-485 AAD Mode Address Match Wake-up ............................................. 578
Figure 6.12-10 UART RX FIFO threshold time-out wake-up ....................................................... 578
Figure 6.12-11 Auto-Flow Control Block Diagram ....................................................................... 582
Figure 6.12-12 UART nCTS Auto-Flow Control Enabled ............................................................ 583
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Figure 6.12-13 UART nRTS Auto-Flow Control Enabled ............................................................ 583
Figure 6.12-14 UART nRTS Auto-Flow with Soft ware Contro l .................................................... 584
Figure 6.12-15 RS-485 nRTS Driving Level in Auto Direction Mode ........................................... 586
Figure 6.12-16 RS-485 nRTS Driving Level with Software Control ............................................. 586
Figure 6.12-17 Structure of RS-485 Frame ................................................................................. 587
Figure 6.13-1 I2C Controller Block Diagram ................................................................................. 618
Figure 6.13-2 I2C Bus Timing ...................................................................................................... 620
Figure 6.13-3 I2C Protocol ............................................................................................................ 620
Figure 6.13-4 Bit Transfer on the I2C Bus .................................................................................... 621
Figure 6.13-5 Acknowledge on the I2C Bus ................................................................................. 621
Figure 6.13-6 Bit Transfer on the I2C Bus .................................................................................... 622
Figure 6.13-7 Acknowledge on the I2C Bus ................................................................................. 623
Figure 6.13-8 Master Transmits Data to Slave by 7-bit ............................................................... 623
Figure 6.13-9 Master Reads Data from Slave by 7-bit................................................................. 623
Figure 6.13-10 Master Transmits Data to Slave by 10-bit ........................................................... 624
Figure 6.13-11 Master Reads Data from Slave by 10-bit ............................................................ 624
Figure 6.13-12 Control I2C Bus according to the current I2C Status ............................................ 625
ISD94100 SERIES TECHNICAL REFERENCE MANUAL
Figure 6.13-13 Master Transmitter Mode Control Flow ............................................................... 627
Figure 6.13-14 Master Receiver Mode Control Flow ................................................................... 629
Figure 6.13-15 Slave Mode Control Flow .................................................................................... 631
Figure 6.13-16 GC Mode ............................................................................................................. 634
Figure 6.13-17 Arbitration L ost ..................................................................................................... 636
Figure 6.13-18 Bus Management Packet Protocol Diagram Element Key .................................. 638
Figure 6.13-19 7-Bit Addressable Device to Host Communication .............................................. 639
Figure 6.13-20 7-Bit Addressable Device Responds to an ARA ................................................ 639
Figure 6.13-21 Bus Management ALERT function ...................................................................... 640
Figure 6.13-22 Bus Management Time Out Timing ..................................................................... 641
Figure 6.13-23 Bus Clock Low Time Out Timing ......................................................................... 641
Figure 6.13-24 Setup Time Wrong Adjustment ............................................................................ 643
Figure 6.13-25 Hold Time Wrong Adjustment .............................................................................. 643
Figure 6.13-26 I2C Data Shifting Direction ................................................................................... 644
Figure 6.13-27 I2C Time-out Count Block Diagram ..................................................................... 646
Figure 6.13-28 I2C Wake-Up Related Signals Waveform ............................................................ 647
Figure 6.13-29 EEPROM Random Read ..................................................................................... 648
Figure 6.13-30 Protocol of EEPROM R an dom Read................................................................... 649
Figure 6.14-1 SPI Block Diagram (SPI0) ..................................................................................... 676
Figure 6.14-2 SPI Block Diagram (SPI1/2) .................................................................................. 676
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Table 6.14-3 SPI/I2S Interface Controller Pin Description (SPI1~SPI2) ..................................... 680
Figure 6.14-4 SPI Peripheral Clock .............................................................................................. 680
Figure 6.14-5 SPI0 Full-Duplex Master Mode Application Block Diagram .................................. 681
Figure 6.14-6 SPI0 Full-Duplex Slave Mode Application Block Diagram .................................... 681
Figure 6.14-7 SPI1 ~ SPI2 Full-Duplex Master Mode Application Block Diagram ...................... 682
Figure 6.14-8 SPI1 ~ SPI2 Full-Duplex Slave Mode Application Block Diagram ........................ 682
Figure 6.14-9 32-Bit in One Transaction ...................................................................................... 683
Figure 6.14-10 Automatic Slave Selection (SSACTPOL = 0, SUSPITV > 0x2)........................... 684
Figure 6.14-11 Automatic Slave Selection (SSACTPOL = 0, SUSPITV < 0x3)........................... 685
Figure 6.14-12 Byte Reorder Function ......................................................................................... 686
Figure 6.14-13 Timing Waveform for Byte Suspend .................................................................... 686
Figure 6.14-14 SPI Half-Duplex Master Mode Application Block Diagram .................................. 687
Figure 6.14-15 SPI Half-Duplex Slave Mode Application Block Diagram .................................... 687
Figure 6.14-16 Two-Bit Transfer Mode System Architecture ....................................................... 689
Figure 6.14-17 Two-Bit Transfer Mode Timing (Master Mode) .................................................... 689
Figure 6.14-18 Bit Sequence of Dual Output Mode ..................................................................... 690
Figure 6.14-19 Bit Sequence of Dual Input Mode ........................................................................ 690
Figure 6.14-20 Bit Sequence of Quad Output Mode.................................................................... 691
Figure 6.14-21 Bit Sequence of Quad Input Mode ...................................................................... 692
Figure 6.14-22 FIFO Threshold Comparator ............................................................................... 693
Figure 6.14-23 Transmit FIFO Buffer Example ............................................................................ 694
Figure 6.14-24 Receive FIFO Buffer Example ............................................................................. 695
Figure 6.14-25 TX Underflow Event and Slave Under Run Event ............................................... 696
Figure 6.14-26 Two-Bit Transfer Mode FIFO Buffer Example (SPI0 Only) ................................. 696
Figure 6.14-27 TX Underflow Event (SPI0 Slave 3-Wire Mode Enabled) ................................... 696
Figure 6.14-28 Slave Mode Bit Count Error ................................................................................. 697
Figure 6.14-29 Slave Time-out Event (for SPI0) .......................................................................... 697
Figure 6.14-30 I2S Data Format Timing Diagram......................................................................... 700
Figure 6.14-31 MSB Justified Data Format Timing Diagram ....................................................... 701
Figure 6.14-32 PCM Mode A Timing Diagram ............................................................................. 701
Figure 6.14-33 PCM Mode B Timing Diagram ............................................................................. 701
ISD94100 SERIES TECHNICAL REFERENCE MANUAL
Figure 6.14-34 FIFO Contents for Various I2S Modes ................................................................. 704
Figure 6.14-35 SPI Timing in Master Mode ................................................................................. 704
Figure 6.14-36 SPI Timing in Master Mode (Alternate Phase of SPIx_CLK) .............................. 705
Figure 6.14-37 SPI Timing in Slave Mode ................................................................................... 705
Figure 6.14-38 SPI Timing in Slave Mode (Alternate Phase of SPIx_CLK) ................................ 705
Figure 6.15-1 CRC Generator Block Diagram ............................................................................. 747
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ISD94100 Series Technical Reference Manual
Figure 6.15-2 CHECKSUM Bit Order Reverse Functional Block ................................................. 748
Figure 6.15-3 Write Data Bit Order Reverse Functional Block .................................................... 748
Figure 6.16-1 ADC Converter Block Diagram .............................................................................. 756
Figure 6.16-2 Sample Module 0~3 Block Diagram ...................................................................... 758
Figure 6.16-3 Sample Module 4~12 Block Diagram ................................................................... 759
Figure 6.16-4 EADC Clock Control .............................................................................................. 760
Figure 6.16-5 Example ADC Conversion Timing Diagram, n=0~12 ............................................ 760
Figure 6.16-6 Sample module Conversion Priority Arbitrator Diagram........................................ 761
Figure 6.16-7 Specific Sample Module ADC EOC Signal for ADINT0~3 Interrupt ...................... 763
Figure 6.16-8 PWM-triggered ADC Start Conversion .................................................................. 764
Figure 6.16-9 External triggered ADC Start Conversion .............................................................. 764
Figure 6.16-10 Conversion Start Delay Timing Diagram ............................................................. 765
Figure 6.16-11 EADC0_ST De-bounce Timing Diagram ............................................................. 766
Figure 6.16-12 ADC Extend Sampling Timing Diagram .............................................................. 767
Figure 6.16-13 ADC Conversion Result Monitor Logics Diagram ............................................... 767
Figure 6.16-14 ADC Controller Interrupts .................................................................................... 768
Figure 6.16-15 ADC start up sequence with calibration............................................................... 769
ISD94100 SERIES TECHNICAL REFERENCE MANUAL
Figure 6.16-16 Model of the sampling network ............................................................................ 770
Figure 6.17-1 I2S Controller Block Diagram ................................................................................. 802
Figure 6.17-2 I2S Clock Control Diagram ..................................................................................... 803
Figure 6.17-3 Master mode Interface Block Diagram .................................................................. 803
Figure 6.17-4 Slave mode Interface Block Diagram .................................................................... 804
Figure 6.17-5 I2S Channel Width and Data Width (CHWIDTH≦DATWIDTH) .............................. 804
Figure 6.17-6 I2S Channel Width and Data Width (CHWIDTH > DATWIDTH) ............................ 804
Figure 6.17-7 I2S Data Format Timing Diagram (FORMAT = 0x0 ; CHWIDTH≦DATWIDTH) .... 805
Figure 6.17-8 MSB Justified Data Format (FORMAT = 0x1 ; CHWIDTH > DATWIDTH) ............ 805
Figure 6.17-9 LSB Justified Data Format (FORMAT = 0x2 ; CHWIDTH > DATWIDTH) ............. 805
Figure 6.17-10 Standar d PCM Audio T iming Diagram (FORMAT = 0x4 ; CHW IDTH≦DATWIDTH)
.............................................................................................................................................. 806
Figure 6.17-11 PCM with MSB Justified Data F or mat (FORMAT = 0x5 ; CHWIDTH > DATW IDTH)
.............................................................................................................................................. 806
Figure 6.17-12 PCM with L SB Justifie d Data For mat (FOR MAT = 0x6 ; CHW IDTH > DATW IDTH)
.............................................................................................................................................. 806
Figure 6.17-13 TDM 6-channel audio format with 24-bit data in 32-bit channel block (PCM standard
data format; FORMAT=0x4) ................................................................................................. 807
Figure 6.17-14 TDM 6-channel audio format with 24-bit data in 32-bit channel block (PCM with MSB
justified; FORMAT=0x5)........................................................................................................ 807
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ISD94100 Series Technical Reference Manual
Figure 6.17-15 TDM 6-channel audio format with 24-bit data in 32-bit channel block (PCM wi th LSB
justified; FORMAT=0x6)........................................................................................................ 807
Figure 6.17-16 I2S Interrupts ........................................................................................................ 809
Figure 6.17-17 FIFO Contents for Various 2-channel Audio Modes ............................................ 810
Figure 6.17-18 FIFO Contents for Various 4-channel Audio Modes ............................................ 811
Figure 6.17-19 FIFO Contents for Various 6-channel Audio Modes (Part-1) .............................. 812
Figure 6.17-20 FIFO Contents for Various 6-channel Audio Modes (Part-2) .............................. 813
Figure 6.18-1 USB Block Diagram ............................................................................................... 834
Figure 6.18-2 NEVWK Interrupt Operation Flow .......................................................................... 836
Figure 6.18-3 Endpoint SRAM Struc tur e ..................................................................................... 837
Figure 6.18-4 Setup Transaction Followed by Data IN Transaction ............................................ 837
Figure 6.18-5 Data Out Transfer .................................................................................................. 838
Figure 6.19-1 DMIC Block Diagram ............................................................................................. 866
Figure 6.19-2 DMIC Clock Control Diagram ................................................................................ 867
Figure 6.19-3 Typical connection to two digital microphones sharing a common data line......... 869
Figure 6.19-4 Digital Microphone Interface Timing Diagram ....................................................... 869
Figure 6.19-5 DMIC FIFO Contents for Various Settings ............................................................ 870
Figure 6.20-1 VAD Block Diagram ............................................................................................... 879
Figure 6.20-2 VAD Clock Control Diagram .................................................................................. 880
Figure 6.20-3 VAD Data Diagram ................................................................................................ 881
Figure 6.20-4 VAD Decision Tree ................................................................................................ 882
Figure 6.21-1 DPWM Block Diagram ........................................................................................... 897
Figure 6.21-2 DPWM Clock Control Diagram .............................................................................. 899
Figure 6.21-3 Splitter Frequency Response and Channel Distribution ........................................ 902
Figure 6.21-4 Audio DPWM FIFO Contents for Various Data Width ........................................... 903
ISD94100 SERIES TECHNICAL REFERENCE MANUAL
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ISD94100 Series Technical Reference Manual
List of Tables
Table 3.1-1 List of Abbreviations .................................................................................................... 27
Table 4.1-1 Devices Features and Peripheral Counts ................................................................... 28
Table 4.2-1 Devices Features Summary ....................................................................................... 30
Table 4.4-1 Pin Descript ion ............................................................................................................ 42
Table 4.5-1 GPIO Alternate Function Summary ............................................................................ 44
Table 6.2.2-1 Reset Value of Register s ......................................................................................... 51
Table 6.2.2-2 Reset Flag Table ...................................................................................................... 53
Table 6.2.5-1 Power Mode T able ................................................................................................... 56
Table 6.2.5-2 Power Mode Difference Table ................................................................................. 57
Table 6.2.5-3 Power Mode Difference Table ................................................................................. 57
Table 6.2.5-4 Clocks in Power Modes ........................................................................................... 58
Table 6.2.5-5 Re-Enter i ng Po wer-down Mode Condition .............................................................. 60
Table 6.2.6-1 Brown-out Detector and Low Voltage Reset Controller Effect Table ...................... 61
Table 6.2.7-1 Address Space Assignments for On-Chip Controllers ............................................. 63
Table 6.2.13-1 Exception Model .................................................................................................. 103
ISD94100 SERIES TECHNICAL REFERENCE MANUAL
Table 6.2.13-2 Interrupt Number Table ........................................................................................ 104
Table 6.2.14-1 Priority Grouping .................................................................................................. 135
Table 6.3.9-1 The symbol definition of PLL Output Frequency formula ...................................... 167
Table 6.4.4-1 Flash Memory Address Map .................................................................................. 195
Table 6.4.4-2 Boot Configuration ................................................................................................. 196
Table 6.4.4-3 ISP Command List ................................................................................................. 201
Table 6.4.4-4 FMC control registers for Flash Read/Write .......................................................... 202
Table 6.4.4-5 Flash Access Optimized Cycle under auto-tuning function ................................... 212
Table 6.4.4-6 The lock effect table with two protections .............................................................. 214
Table 6.5.5-1 De-Bounce Function Setting Table ........................................................................ 245
Table 6.6.5-1 Channel Priority Table ........................................................................................... 266
Table 6.7.6-1 PWM Pulse Gener at ion E vent Priority in Up Count Type...................................... 356
Table 6.7.6-2 PWM Pulse Gener at ion E vent Pr iority in Down Count Type ................................. 357
Table 6.7.6-3 PWM Pulse Gener at ion E vent Pr iority in Up-Down Count Type ........................... 357
Table 6.8.3-1 PWM System Clock Source Control Registers Setting Table ............................... 405
Table 6.8.5-1 PWM Pulse Generation Event Priority for Up-Counter .......................................... 419
Table 6.8.5-2 PWM Pulse Generation Event Priority for Down-Counter ..................................... 420
Table 6.8.5-3 PWM Pulse Generation Event Priority for Up-Down-Counter ............................... 420
Table 6.9.5-1 Watchdog Timer Time-out Interval Period Selection ............................................. 527
Table 6.10.5-1 WWDT Prescaler Value Selection ....................................................................... 535
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ISD94100 Series Technical Reference Manual
Table 6.10.5-2 CMPDAT Setting Limitation ................................................................................. 537
Table 6.11.5-1 RTC Read/Write Enable ...................................................................................... 546
Table 6.11.5-2 12/24 hour T im e Scale Selectio n ......................................................................... 547
Table 6.11.5-3 Registers value after power-on ............................................................................ 548
Table 6.12.2-1 UART Feature ...................................................................................................... 567
Table 6.12.3-1 UART Interrupt ..................................................................................................... 570
Table 6.12.4-1 UART Interface Controller Pin ............................................................................. 571
Table 6.12.5-1 UART controller Baud Rate Equation Table ........................................................ 571
Table 6.12.5-2 UART controller Baud Rate Parameter Setting Example Table .......................... 572
Table 6.12.5-3 UART controller Baud Rate Register Setting Example Table ............................. 572
Table 6.12.5-4 Baud Rate Compensation Example Table 1 ....................................................... 573
Table 6.12.5-5 Baud Rate Compensation Example Table 2 ....................................................... 573
Table 6.12.5-6 UART controller Interrupt Source and Flag List ................................................... 580
Table 6.12.5-7 UART Line Control of Word and Stop Length Setting ......................................... 581
Table 6.12.5-8 UART Line Control of Parity Bit Setting ............................................................... 581
Table 6.13.5-1 Reserved S MBus Address ................................................................................... 637
Table 6.13.5-2 Relationship between I2C Baud Rate and PCLK ................................................. 642
Table 6.13.5-3 I2C Status Code Description ................................................................................ 645
Table 6.14.2-1 SPI feature difference (SPI0~SPI2) ..................................................................... 675
Table 6.16.5-1 The relation between resolution and conversion cycles ...................................... 762
Table 6.16.5-2 EADC Power Saving Mode .................................................................................. 769
Table 6.16.5-3 EADC minimum sampling time ............................................................................ 770
Table 6.19.5-1 Example for DMIC bus clock and OSR configuring ............................................. 868
Table 6.20.5-1 Short Term Power Attack Time Selection ............................................................ 883
Table 6.20.5-2 Long Term Power Attack Time Selection ............................................................ 883
Table 6.20.5-3 Power Threshold Reference ................................................................................ 884
ISD94100 SERIES TECHNICAL REFERENCE MANUAL
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ISD94100 Series Technical Reference Manual

1 GENERAL DESCRIPTION

The ISD94100 s er ies 3 2-bit microcontrollers are an em bedd ed A RM® Cortex®-M4F core wit h D SP extensions and a Floating Point Unit which run up to 200 MHz. It pro vides up to 512 KB of flash memory and up to 192 KB of SRAM. It is ideal for consumer product applications which need communication interfaces and high computing power.
The ISD94100 is also equipped with a variety of peripheral devices, such as Multi-Function Timers, Watchdog Tim ers, RTC, PD MA, UART, SPI, I voltage reset and Brown-o ut Detector. In add ition, it supports plenty of audio peripherals such as
2
S, DMIC and audio DPWM modulator.
I
The ISD94100 series is suitable for a wide range of applications such as:
Audio Processing Platform  Consumer Products  Industrial Automation  Home Automation  Security Alarm System  System Supervisors
ISD94100 SERIES TECHNICAL REFERENCE MANUAL
2
C, PWM, GPIO, 12-bit AD C, USB1.1 De vice, Low
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ISD94100 Series Technical Reference Manual

2 FEATURES

2.1 ISD94100 Series Features

Core
– ARM – Supports DSP extension with hardw are di vider – Supports IEEE 754 compliant Floating-point Unit (FPU) – Supports Memory Protection Unit (MPU) – One 24-bit system timer – Supports Low Power Sleepmode by WFI and WFE instructions – Single-c ycle 32-bit hardware multiplier – Supports programmable 16 level priorities of Nested Vectored Interrupt Controller
– Supports programmable mask-able interrupts – Supports Embedded Trace Macrocell
Built-in LDO for wide operating voltage range Flash Memory
– Up to 512KB on-chip Application ROM (APROM) – Configurable program code/data allocation – 4 KB Flash for loader (LDROM) – Supports 2-wire ICP update through SWD/ICE interface – Supports In-system program (ISP), In application program (IAP) update – Supports 4 KB page erase for all embedded flash – Supports 4 KB two-way cache to reduce power consumption and improve
– Enhanced performance up to 3.4 Core Mark/MHz when running code in Flash with
– Supports 2-wire ICP flash updating through SWD interface – Supports 32-bit/64-bit and multi-word flash programming function. – Supports fast flash programming verification by CRC function.
SRAM
®
Cortex®-M4F core running up to 200 MHz
(NVIC)
performance.
cache
ISD94100 SERIES TECHNICAL REFERENCE MANUAL
– Up to 192 KB embedded SRAM – 32 KB SRAM in bank 0 that supports hardware parity check and retention mode – Supports byte-, half-word- and word-access – Supports exception (NMI) generated once a parity check error occurs – Supports PDMA mode
Clock Control
– Built-in 48.0 MHz or 49.152 MHz selectable internal high speed RC oscillator (HIRC) for
system operation
– Built-in 10 k Hz internal low speed RC oscillator (LIR C) for W atchdog Tim er and wake-
up operation
– 4~24.576 MHz external high speed crystal oscillator (HXT) for precise timing operation – 32.768 kHz ex ternal lo w sp eed c rystal osci llator (LXT ) f or RT C f unction and low-power
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ISD94100 Series Technical Reference Manual
system operation
– Supports one PLL up to 500 MHz for high performance system operation, sourced from
HIRC or HXT
– Supports clock failure detection for high/low speed external crystal oscillator – Supports exception (NMI) generation once a clock failure detected – Supports clock output
GPIO
– Supports four I/O modes:
Quasi bi-direction  Push-Pull output  Open-Drain output  Input only with high impendence
– TTL/Schmitt trigger input selectable – I/O pin configured as interrupt source with edge/level trigger setting – Supports high slew driver and high sink current I/O (up to 20mA at 3.3V) – Supports software selectable slew rate control – Supports 5V tolerance function on subset of GPIO except analog I/O
PDMA (Peripheral DMA)
– Supports 16 independent configurable channels for automatic data transfer between
memories and per ipher a ls
– Supports stride function.
ISD94100 SERIES TECHNICAL REFERENCE MANUAL
– Channel 0, 1 supports time-out function for each channel. – Supports Basic and Scatter-Gather Transfer modes – Each channel supports circular buffer management using Scatter-Gather Transfer mode – Supports two types of priorities modes: Fixed-priority and Round-robin modes – Supports byte-, half-word- and word-access – Supports single and burst transfer type – Supports source and destination address can be increment or fixed. – DMA transfer count up to 65536.
Multi-Function Timer (MFT, Timer + PWM)
– TIMER mode
Supports 4 sets of 32-bit timers with 24-bit up-timer and 8-bit prescale counter,
24-bit up counter value is readable.
Independent clock source for each timer  Provides One-shot, Periodic, Toggle and Continuous Counting operation modes  Supports event counting function to count the event from external pin  Supports input capture function to capture or reset counter value  Supports external capture pin event for interval measurement.  Supports external capture pin event to reset 24-bit up counter.  Supports chip wake-up from Idle/Power-down mode if a timer interrupt signal is
generated
Support Timer0 ~ Timer3 time-out interrupt signal or capture interrupt signal to
trigger PWM, EADC and DMA.
Supports Inter-Timer trigger mode
– PWM mode
Supports four 16-bit PW M counters with 10-bit dead time generator  Supports 12-bit pre-scale for PWM.
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PWM
– Supports up to 6 independent PWM outputs with 16-bit resolution – Supports maximum clock frequency up to 200MHz – Supports 12-bit clock prescale – Supports dead time with maximum divided 12-bit prescale – Supports one-shot or auto-reload counter operation mode – Supports up, down or up-down PWM counter type – Supports synchronous function for phase control – Supports counter synchronous start function – Supports complementary mode for 3 complementary paired PWM output channel – Supports brake function with auto recovery after brake condition removed – Supports mask function and tri-state output for each PWM channel – Supports trigger EADC to start conversion – Supports up to 6 independent input captur e channels with 16-bit resolution counter
Watchdog Timer
ISD94100 Series Technical Reference Manual
Supports independent mode for PWM output channel  Supports 8 channel PWM outputs in complementary mode  Supports mask function and tri-state enable for each PWM pin  Supports interrupt on the following events:
PWM counter match zero, period value or compared value
Supports trigger EADC on the following events:
PWM counter match zero, period value or compared value
ISD94100 SERIES TECHNICAL REFERENCE MANUAL
– 18-bit free running up counter for WDT time-out interval – Supports multiple clock sources from LIRC (default selection), HC L K/2 048 an d LX T – 8 selectable time-out period from 1.6ms ~ 26.0sec (depending on clock source) – Able to wake up from Power-down or Idle mode – Interrupt or reset selectable on watchdog time-out – Supports selectable WDT reset delay period, including 1026、130、18 or 3 WDT_CLK
reset delay period
– Configurable to force WDT enable after chip power-on or reset. – Supports WDT time-out wake-up function only if WDT clock source is selected as LIRC
or LXT
Window Watchdog Timer
– Supports multiple clock sources from HCLK/2048 (default selection) and LIRC – Window set by 6-bit counter with 11-bit prescale – WWDT counter suspends in Idle/Power-down mode
RTC
– Supports software compensation by setting frequency compensate register
(FCR),compensated clock accuracy reaches ±5ppm within 5 seconds
– Supports RTC counter (second, minute, hour) and calendar counter (day, month, year) – Supports Alarm registers (second, minute, hour, day, month, year) – Selectable 12-hour or 24-hour mode – Automatic leap year recognition – Supports Day of the Week counter
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ISD94100 Series Technical Reference Manual
– Supports periodic time tick interrupt with 8 period options 1/128, 1/64, 1/32, 1/16, 1/8,
1/4, 1/2 and 1 second
– Supports 1 Hz, clock output – Supports wake-up from idle mode, Power-down mode and Standby Power-do wn mode – Supports 32 kHz Oscillator gain control – Supports RTC Time Tick and Alarm Match interrupt – Support Time stamp
UART
– Supports low power UART (LPUART): baud rate clock from LXT(32.768 kHz) with
9600bps in Power-down mode even system clock is stopped
– Support baud rate up to 12.5 MHz – Supports 16-byte FIFOs with programmable level trigger – Supports auto flow control ( CTS and RTS) – Supports RS-485 9-bit mode and direction control – Programmable baud-rate generator up to 1/16 system clock – Programmable receiver FIFO trigger level
– Supports wake-up function
– Supports 8-bit receiver FIFO time-out detection function – Supports Auto-Baud Rate measurement and baud rate compensation function – Supports break error, frame error, parity error and receive/transmit FIFO overflow
ISD94100 SERIES TECHNICAL REFERENCE MANUAL
I
detection function
– Supports nCTS, incoming data, RX FIFO reached threshold and RS-485 Address
Match (AAD mode) wake-up function in idle mode.
– Supports hardware or software enables to program nRTS pin to control RS-485
transmission direction
– Supports PDMA mode
2
C
– Supports up to two sets of I – Supports Master/Slave mode – Bidirectional data transfer between masters and slaves – Multi-master bus (no central master) – Supports 10 bits mode – Support High speed mode 3.4Mbps – Supports Standard mode (100 kbps), Fast mode (400 kbps) and Fast mode plus (1
Mbps)
– Arbitration between simultaneously transmitting masters without corruption of serial
data on the bus
– Serial clock synchronization allows devices with different bit rates to communicate via
one serial bus
– Serial clock synchronization can be used as a handshake mechanism to suspend and
resume serial transfer
– Programmable clocks allow versatile rate control – Supports multiple address recognition (four slave address with mask option) – Supports SMBus and PMBus
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2
C devices
Page 23
ISD94100 Series Technical Reference Manual
– Supports multi-address Power-down wake-up function
2
S
I
– Supports one I – Interface with external audio CODEC – Supports Master and Slave mode – Capable of handling 8-, 16-, 24- and 32-bit word sizes – Mono and stereo audio data
2
S protocols: Philips standard, MSB-justified, and LSB-justified data format
– I – PCM protocols: PCM standard, MSB-justified, and LSB-justified data format – PCM protocol supports TDM multi-channel transmission in one audio sample, the number of
data channels can be set as 2, 4, 6, or 8
– Two 16-level FIFO data buffers, one for transmitting and the other for receiving – Generates interrupt requests when buffer levels cross a programmable boundary – Supports two DMA requests, one for transmitting and the other for receiving
SPI0
– SPI Quad controller – SPI0 – Supports Master or Slave mode operation – Supports 2-bit Transfer mode – Supports Dual and Quad I/O Transfer mode – Supports one/two data channel half-duplex transfer – Support receive-only mode – Configurable bit length of a transfer word from 8 to 32-bit – Provides separate 8-level depth transmit and receive FIFO buffers – Supports MSB first or LSB first transfer sequence – Supports the byte reorder function – Supports Byte or Word Suspend mode – Supports 3-wired, no slave select signal, bi-direction interface – Master up to 25 MHz, and Slave up to 25 MHz (when chip operating at V
– Supports PDMA mode
2
SPI / I
S
2
S interface
= 2.7~3.6V)
DD
ISD94100 SERIES TECHNICAL REFERENCE MANUAL
– Supports two sets of SPI/ I2S controllers – SPI 1/ SPI2 – Supports Master or Slave mode operation – Supports two PDMA requests, one for transmitting and the other for receiving – SPI supports configurable bit length of a transfer word from 8 to 32-bit – SPI Provides separate 4-level of 32-bit (or 8-level of 16-bit) transmit and receive FIFO
buffers which depended on SPI setting of data width
– SPI supports MSB first or LSB first transfer sequence – SPI supports the byte reorder function – SPI supports Byte or Word Suspend mode – SPI supports one data channel half-duplex transfer – SPI supports receive-only m ode – I2S interface with externa l aud io CODEC
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ISD94100 Series Technical Reference Manual
– I2S supports Master and Slave mode – I2S supports 8-, 16-, 24- and 32-bit audio data sizes – I2S supports mono and stereo audio data – I2S supports PCM mode A, PCM mode B, I2S and MSB justified data format – I2S Interface with external audio CODEC – I2S provides two 4-level FIFO data buffers, one for transmitting and the other for
receiving
– Generates interrupt requests when buffer levels cross a programmable boundary
EADC
– Analog input voltage range: 0~ AV – Supports single 12-bit SAR EADC conversion – 12-bit resolution and 10-bit accuracy is guaranteed – Up to 13 external single-ended analog input channels – Up to 2 MSPS conversion rate – Supports three power saving modes:
Deep Power-down mode.  Power-down mode.  Standby mode.
– Supports single EADC interrupt – Supports calibration and load calibration words capability.
ISD94100 SERIES TECHNICAL REFERENCE MANUAL
– An A/D conversion can be triggered by Software enable, External pin, Timer 0~3
overflow pulse trigger and PW M trigger.
– 12-bit, 10-bit, 8-bit, 6-bit configurable resolution. – Maximum EADC clock frequency is 60 MHz. – Configurable EADC int erna l sampling time. – Up to 13 sample modules
Each of sample module 0~12 which is configurable for EADC converter channel
EADC_CH0~12 and trigger source.
Double buffer for sample module 0~3  Configurable sampling time for each sample module.  Conversion results are held in 13 data registers with valid and overrun
indicators.
– Supports PDMA transfer
USB 1.1 Device Controller
DD
– Compliant with USB 2.0 Full-Speed specification – Provides 1 interrupt vector with 4 different interrupt events (NEVWK, VBUSDET, USB
and BUS)
– Supports Control/Bulk/Interrupt/Isochronous transfer type – Supports suspend function when no bus activity existing for 3 ms – Supports 12 endpoints for configurable Control/Bulk/Interrupt/Isochronous transfer
types and maximum 1k bytes buffer size
– Provides remote wake-up capability Programmable initial value
Digital Microphone Inputs
– Provides one 32-level FIFO data buffers for receiving. – Generates interrupt requests when buffer levels cross a programmable boundary.
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ISD94100 Series Technical Reference Manual
– Supports PDMA transfer. – Supports up to four channel digital microphones. – Both digital PDM microphone inputs can be used simultaneously.
Voice Active Detection
– Configuration detect levels. – Supports idle mode wake-up function. – Supports auto switch DMIC path when CPU wake-up by VAD. – Generates interrupt requests when voice detected.
Audio DPWM Modulator
– Differential Audio PWM Output (DPWM) – Supports left channel, right channels and sub-woofer channel. – Supports sample rate from 16~96 kHz – Programmable biquad filter with 10 band. – PDMA data channel for streaming of PCM audio data. – Supports the single precision floating point for input data and BIQ coefficient. – Provides one 32-level FIFO data buffers for transmitting.
Cyclic Redundancy Calculation Unit
– Supports four common polynomials CRC-CCITT, CRC-8, CRC-16, and CRC-32 – Programmable initial value – Supports programmable order reverse setting for input data and CRC checksum – Supports programmable 1’s complement setting for input data and CRC checksum. – Supports 8-/16-/32-bit of data width
– Programmable seed value – 8-bit write mode: 1-AHB clock cycle operation – 16-bit write mode: 2-AHB clock cycle operation – 32-bit write mode: 4-AHB clock cycle operation – Supports using DMA to write data to perform CRC operation
Brown-out Detector
– With 8 levels: 3.0V/2.8V/2.6V/2.4V/2.2V/2.0V/1.8V/1.6V – Supports Brown-out Interrupt and Reset option
Low Voltage Reset
– Threshold voltage levels: 1.5V
Operating Temperature: -40℃~85℃ Packages
– All Green package (RoHS)
– QFN 48-pin (6x6 mm)
LQFP 64-pin (7x7 mm)
– –
LQFP 64-pin (10x10 mm)
ISD94100 SERIES TECHNICAL REFERENCE MANUAL
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ISD94100 Series Technical Reference Manual

3 ABBREVIATIONS

3.1 Abbreviations

Acronym
ACMP
ADC Analog-to-Digital Converter AES Advanced Encryption Standard APB Advanced Peripheral Bus AHB Advanced High-Performance Bus BOD Brown-out Detection CAN Controller Area Network DAP Debug Access Port DES Data Encryption Standard DMIC Digital Microphone Inputs DPWM Audio DPWM Modulator EBI External Bus Interface EPWM Enhanced Pulse Width Modulation
ISD94100 SERIES TECHNICAL REFERENCE MANUAL
FIFO First In, First Out FMC Flash Memory Controller
Description
Analog Comparator Controller
FPU Floating-point Unit GPIO General-Purpose Input/Output HCLK The Clock of Advanced High-Performance Bus HIRC High Speed RC Oscillator HXT External High Speed Crystal Oscillator IAP In Application Programming ICP In Circuit Programming ISP In System Programming LDO Low Dropout Regulator LIN Local Interconnect Network LIRC 10 kHz internal low speed RC oscillator (LIRC) MPU Memory Protection Unit NVIC Nested Vectored Interrupt Cont rol ler PCLK The Clock of Advanced Peripheral Bus PDMA Peripheral Direct Memory Access PLL Phase-Locked Loop
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ISD94100 Series Technical Reference Manual
PWM Pulse Width Modulation QEI Quadrature Encoder Interface SD Secure Digital SPI Serial Peripheral Interface SPS Samples per Second TDES Triple Data Encryption Standard TMR Timer Control l er UART Universal Asynchronous Receiver/Transmitter UCID Unique Customer ID USB Universal Seri al Bus VAD Voice Active Detection WDT Watchdog Timer WWDT Window Watchdog Timer
Table 3.1-1 List of Abbreviations
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ISD94100 Series Technical Reference Manual
24
ARI
24
BRI
24
ADI
24
CDI
24
DDI
24
PDI
24
EDI
13
ADI
24
BYI
23
BYI
13
BYI
Max. CPU frequency
(MHz)
Acoustic Echo
Cancellation
Noise
Reduction
Voice
Recognition
LQFP 64
(10x10 mm)
LQFP 64
(7x7 mm)
QFN 48
(6x6 mm)

4 PARTS INFORMATION LIST AND PIN CONFI GURATION

4.1 Parts Information

PART NUMBER
ISD941
100 200
Flash (KB)
SRAM (KB)
ISP Loader ROM (KB)
I/O
32-bit Timer
RTC
UART
SPI
SPI/I2S
Connectivity
ISD94100 SERIES TECHNICAL REFERENCE MANUAL
I2S
I2C
PWM
58 57 41
512 256 512 256 192 128 192 128
4
4
√ 1 1 2 1 2
6 5
USB 1.1 FS Device
12-bit ADC
Audio DPWM
Audio
Function
Beamforming
Input
Processing
Package
VAD
DMIC
- √ 13 12
2.1 -- 2.1 ­√ - √ ­4 - 4 -
- √ -
- √ -
- √ -
- √ - √ -
Table 4.1-1 Devices Features and Peripheral Counts
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Page 29
ISD Audio Product Family
Package Type
Y: QFN48
(6x6 mm)
D: LQFP64
(7x7 mm)
R: LQFP64 (10x10 mm)
Family ID
1: Family Series ID
Temperature
I: -40℃ ~ +85℃
Product Series
4: Cortex-M4F
Flash ROM
Feature
A: Standard B: Basic, no Audio C: Standard + Voice Recognition D: Standard + Beamforming + Noise Reduction P: Standard + Beamforming + Noise Reduction + Voice Recognition
SRAM Size
1: 256KB 2: 512KB
3: 128KB 4: 192KB
I9 4 X X X X XX

4.2 Ordering I nf ormation

ISD94100 Series Technical Reference Manual
Figure 4.2-1 Ordering Information Scheme
ISD94100 SERIES TECHNICAL REFERENCE MANUAL
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ISD94100 Series Technical Reference Manual
PART NUMBER RAM FLASH FEATURE PACKAGE
ISD94124BYI ISD94123BYI ISD94113BYI ISD94124ADI ISD94124CDI ISD94124DDI ISD94124PDI ISD94113ADI ISD94124ARI ISD94124BRI
Note:
1. VR = Voice Recognition / BF = Beamforming / NR = Noise Reduction / AEC = Acoustic Echo Cancellation
192 KB 512 KB Basic feature QFN48 (6x6 mm) 128 KB 512 KB Basic feature QFN48 (6x6 mm) 128 KB 256 KB Basic feature QFN48 (6x6 mm) 192 KB 512 KB Standard feature LQFP64 (7x7 mm) 192 KB 512 KB Standard feature + VR LQFP64 (7x7 mm) 192 KB 512 KB Standard feature + BF + NR LQFP64 (7x7 mm) 192 KB 512 KB Standard feature + BF + NR + VR LQFP64 (7x7 mm) 128 KB 256 KB Standard feature LQFP64 (7x7 mm) 192 KB 512 KB Standard feature LQFP64 (10x10 mm) 192 KB 512 KB Basic feature LQFP64 (10x10 mm)
Table 4.2-1 Devices Features Summary
ISD94100 SERIES TECHNICAL REFERENCE MANUAL
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ISD94100 Series Technical Reference Manual
VSS
Top transparent view
PB.0
PB.1
PB.2
PB.3
PB.4
nRESET
PB.5
PB.6
LDO_CAP
VSS
AVSS
VDD
24 23 22 21 20 19 18 17 16 15 14 13
PD.1 PD.0 PB.13 PB.14 PB.15 USB_VDD33 PC.4 PC.3 PC.2 PC.1 PC.0 AVDD
36
35
34
33
32
31
30
29
28
27
26
25
PA.3
PA.2
PA.1
PA.0
PD.15
PD.14
PD.9
PD.8
PD.5
PD.4
PD.3
PD.2
37 38 39 40 41 42 43 44 45 46 47 48
PA.4 PA.5 PA.6 PA.7 PA.8
PA.9 PA.10 PA.11 PA.12 PA.13 PA.14 PA.15
1
2
3
4
5
6
7
8
9
10
11
12
QFN48

4.3 Pin Configuration

4.3.1 QFN48 (6x6 mm) Pin Diagram

Figure 4.3-1 QFN48 (6x6 mm) Pin Diagram
ISD94100 SERIES TECHNICAL REFERENCE MANUAL
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ISD94100 Series Technical Reference Manual
PB.3
nRESET
PB.5
PB.7
LDO_CAP
PB.1
PB.8
VSS
LQFP64
(7x7 mm)
PA.1
PA.0
PC.13
PC.10
PC.4
PB.13
PB.4
USB_VDD33
PC.12
PC.14
PB.9
PC.11
PC.9 PC.8 PC.7
PD.3
PD.8
PD.4
PD.2
PA.2
PA.4
PD.15
PA.8
PD.1
PD.0
PA.3
PA.7
PA.6
PA.9
PD.14
PB.6
PA.5
1
2
3
4
5
6
7
8
9
10
11
12
48
47
46
45
44
43
42
41
40
39
38
37
17
18
19
20
21
22
23
24
25
26
27
28
64
63
62
61
60
59
58
57
56
55
54
53
PD.13
PD.7
PD.6
PB.0
PB.2
PA.15
PA.11
PC.6 PC.5
VDD
AVDD
13
14
15
16
AVSS
PC.3
29
30
31
32
PC.2 PC.1 PC.0
PB.14
PB.15
36
35
34
33
PA.12
PA.10
52
51
50
49
PA.13 PA.14
PD.9
PD.5

4.3.2 LQFP64 (7x7 mm) Pin Diagram

ISD94100 SERIES TECHNICAL REFERENCE MANUAL
Figure 4.3-2 LQFP64 (7x 7 m m ) Pin Diagram
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ISD94100 Series Technical Reference Manual
PB.3
nRESET
PB.5
PB.7
LDO_CAP
PB.1
PB.8
VSS
LQFP64
(10x10 mm)
PA.1
PA.0
PC.13
PC.10
PC.4
PD.2
PB.4
PC.15
PC.12
PC.14
PB.9
PC.11
PC.9 PC.8 PC.7
PD.6
PD.11
PD.7
PD.5
PA.2
PA.4
PD.15
PA.8
PD.4
PD.3
PA.3
PA.7
PA.6
PA.9
PD.14
PB.6
PA.5
1
2
3
4
5
6
7
8
9
10
11
12
48
47
46
45
44
43
42
41
40
39
38
37
17
18
19
20
21
22
23
24
25
26
27
28
64
63
62
61
60
59
58
57
56
55
54
53
PD.13
PD.10
PD.9
PB.0
PB.2
PA.15
PA.11
PC.6 PC.5
VDD
AVDD
13
14
15
16
AVSS
PC.3
29
30
31
32
PC.2 PC.1 PC.0
PD.1
PD.0
36
35
34
33
PA.12
PA.10
52
51
50
49
PA.13 PA.14
PD.12
PD.8

4.3.3 LQFP64 (10x10 mm) Pin Diagram

Figure 4.3-3 LQFP64 (10x10 mm) Pin Diagram
ISD94100 SERIES TECHNICAL REFERENCE MANUAL
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ISD94100 Series Technical Reference Manual
PB.0
I/O
MFP0
General purpose digital I/O pin.
PWM0_SYNC_IN
I/O
MFP1
PWM0 counter synchronous trigger input pin.
I2C0_SCL
I/O
MFP2
I2C0 clock pin.
PWM0_CH0
I/O
MFP3
PWM0 channel0 output/capture input.
PB.1
I/O
MFP0
General purpose digital I/O pin.
PWM0_SYNC_OUT
I/O
MFP1
PWM0 counter synchronous trigger output pin.
I2C0_SDA
I/O
MFP2
I2C0 data input/output pin.
PWM0_CH1
I/O
MFP3
PWM0 channel1 output/capture input.
PB.2
I/O
MFP0
General purpose digital I/O pin.
PWM0_CH0
I/O
MFP1
PWM0 channel0 output/capture input.
TM2
I/O
MFP2
Timer2 event counter input / toggle output.
PWM0_CH2
I/O
MFP3
PWM0 channel2 output/capture input.
PB.3
I/O
MFP0
General purpose digital I/O pin.
PWM0_CH1
I/O
MFP1
PWM0 channel1 output/capture input.
TM2_EXT
I/O
MFP2
Timer2 external capture input.
DMIC_DAT1
I
MFP3
Digital microphone channel 1 data input pin.
UART0_RXD
I
MFP4
UART0 Data receiver input pin.
PWM0_CH3
I/O
MFP5
PWM0 channel3 output/capture input.
PB.4
I/O
MFP0
General purpose digital I/O pin.
UART0_nCTS
I
MFP1
Clear to Send input pin for UART0.
PWM0_CH0
I/O
MFP2
PWM0 channel0 output/capture input.
DMIC_CLK1
O
MFP3
Digital microphone channel 1 clock output pin.
UART0_TXD
O
MFP4
UART0 data transmitter output pin.
PWM0_CH4
I/O
MFP5
PWM0 channel4 output/capture input.
RESETN
I
MFP0
External reset input: active LOW, with an internal pull­up. Set this pin low reset to initial state.
PB.5
I/O
MFP0
General purpose digital I/O pin.
XT1_OUT
I
MFP1
External 4~24.576 MHz (high speed) crystal output pin.
PWM0_CH1
I/O
MFP2
PWM0 channel1 output/capture input.
I2C0_SDA
I/O
MFP3
I2C0 data input/output pin.
I2C1_SDA
I/O
MFP4
I2C1 data input/output pin.

4.4 Pin Description

MFP = Multi-funct i on pi n.
Note: Pin Type I=Digital Input, O = Digital Output; A = Analog Pin; P = Power Pin;
Pins
QFN48
(6x6)
1 1 1
2 2 2
3 3 3
LQFP64
(7x7)
LQFP64
(10x10)
Pin Name Type MFP Description
ISD94100 SERIES TECHNICAL REFERENCE MANUAL
4 4 4
5 5 5
6 6 6
7 7 7
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DMIC_DAT0
I
MFP5
Digital microphone channel 0 data input pin.
PB.6
I/O
MFP0
General purpose digital I/O pin.
XT1_IN
I
MFP1
External 4~24.576 MHz (high speed) crystal input pin.
PWM0_CH2
I/O
MFP2
PWM0 channel2 output/capture input.
I2C0_SCL
I/O
MFP4
I2C0 serial clock pin.
I2C1_SCL
I/O
MFP5
I2C1 serial clock pin.
DMIC_CLK0
O
MFP6
Digital microphone channel 0 clock output pin.
PB.7
I/O
MFP0
General purpose digital I/O pin.
UART0_nRTS
O
MFP1
Request to Send output pin for UART0.
PWM0_CH3
I/O
MFP2
PWM0 channel3 output/capture input.
PB.8
I/O
MFP0
General purpose digital I/O pin.
UART0_TXD
O
MFP1
UART0 Data transmitter output pin.
PWM0_CH4
I/O
MFP2
PWM0 channel4 output/capture input.
PB.9
I/O
MFP0
General purpose digital I/O pin.
UART0_RXD
I
MFP1
UART0 Data receiver input pin.
PWM0_CH5
I/O
MFP2
PWM0 channel5 output/capture input.
LDO_CAP
P
MFP0
LDO output pin.
connected with a 1uF
capacitor.
10
13
13
VSS P MFP0
Ground pin for digital circuit.
11
14
14
AVSS
P
MFP0
Ground pin for analog circuit.
VDD P MFP0
Power supply for I/O ports and LDO source for internal PLL and digital circuit.
13
16
16
AVDD
P
MFP0
Power supply for internal analog circuit.
PC.0
I/O
MFP0
General purpose digital I/O pin.
I2C1_SCL
I/O
MPF1
I2C1 clock pin.
X32_OUT
O
MFP2
External 32.768 kHz (low-speed) crystal output pin.
SPI1_MOSI
I/O
MFP3
SPI1 MOSI (Master Out, Slave In) pin; or I2S1 data output pin.
PC.1
I/O
MFP0
General purpose digital I/O pin.
I2C1_SDA
I/O
MFP1
I2C1 data input/output pin.
X32_IN
I
MFP2
External 32.768 kHz (low-speed) crystal input pin.
SPI1_MISO
I/O
MFP3
SPI1 MISO (Master In, Slave Out) pin; or I2S1 data input pin.
PC.2
I/O
MFP0
General purpose digital I/O pin.
I2C1_SMBSUS
O
MFP1
I2C1 SMBus SMBSUS# pin (PMBus CONTROL pin)
TM3
I/O
MFP2
Timer3 event counter input / toggle output.
Pins
QFN48
(6x6)
8 8 8
LQFP64
(7x7)
9 9
10 10
11 11
LQFP64
(10x10)
Pin Name Type MFP Description
ISD94100 SERIES TECHNICAL REFERENCE MANUAL
9 12 12
12 15 15
14 17 17
15 18 18
16 19 19
Note: This pin needs to be
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ISD94100 Series Technical Reference Manual
SPI1_CLK
I/O
MFP3
SPI1 Serial Clock pin; or I2S1 bit clock pin.
PC.3
I/O
MFP0
General purpose digital I/O pin.
I2C1_SMBAL
O
MFP1
I2C1 SMBus SMBALERT# pin
TM3_EXT
I/O
MFP2
Timer3 external capture input.
SPI1_SS
I/O
MFP3
SPI1 slave select pin; or I2S1 le ft right c hannel c lock pin.
PC.4
I/O
MFP0
General purpose digital I/O pin.
PWM0_CH2
I/O
MFP1
PWM0 channel2 output/capture input.
CLKO
O
MFP2
Clock Output pin.
SPI1_I2SMCLK
O
MFP3
SPI1 I2S master clock output pin.
PC.5
I/O
MFP0
General purpose digital I/O pin.
INT1 I MFP1
External interrupt1 input pin.
SPI2_MOSI
I/O
MFP2
SPI2 MOSI (Master Out, Slave In) pin.
PC.6
I/O
MFP0
General purpose digital I/O pin.
INT2 I MFP1
External interrupt2 input pin.
SPI2_MISO
I/O
MFP2
SPI2 MISO (Master In, Slave Out) pin.
PC.7
I/O
MFP0
General purpose digital I/O pin.
SPI0_SS0
I/O
MFP1
1st SPI0 Slave Select pin
SPI2_CLK
I/O
MFP2
SPI2 serial clock pin.
PC.8
I/O
MFP0
General purpose digital I/O pin.
SPI0_MOSI1
I/O
MFP1
2nd SPI0 MOSI (Master Out, Slave In) pin.
SPI2_SS
I/O
MFP2
SPI2 Slave Select pin.
PC.9
I/O
MFP0
General purpose digital I/O pin.
SPI0_MISO1
I/O
MFP1
2nd SPI0 MISO (Master In, Slave Out) pin.
SPI2_I2SMCLK
O
MFP2
SPI2 I2S master clock output pin
PC.10
I/O
MFP0
General purpose digital I/O pin.
SPI0_MOSI0
I/O
MFP1
1st SPI0 MOSI (Master Out, Slave In) pin.
PWM0_BRAKE0
I
MFP2
Brake input pin 0 of PWM0.
DPWM_RN
O
MFP3
Audio DPWM right channel negative output pin.
PC.11
I/O
MFP0
General purpose digital I/O pin.
SPI0_MISO0
I/O
MFP1
1st SPI0 MISO (Master In, Slave Out) pin.
PWM0_BRAKE1
I
MFP2
Brake input pin 1 of PWM0.
DPWM_RP
O
MFP3
Audio DPWM right channel positive output pin.
PC.12
I/O
MFP0
General purpose digital I/O pin.
SPI0_CLK
I/O
MFP1
SPI0 serial clock pin.
Pins
QFN48
(6x6)
17 20 20
18 21 21
LQFP64
(7x7)
22 22
23 23
LQFP64
(10x10)
Pin Name Type MFP Description
ISD94100 SERIES TECHNICAL REFERENCE MANUAL
24 24
25 25
26 26
27 27
28 28
29 29
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ISD94100 Series Technical Reference Manual
DPWM_LN
O
MFP3
Audio DPWM left channel negative output pin.
PC.13
I/O
MFP0
General purpose digital I/O pin.
PWM0_CH3
I/O
MFP1
PWM0 channel3 output/capture input.
I2C0_SCL
I/O
MFP2
I2C0 clock pin.
DPWM_LP
O
MFP3
Audio DPWM left channel positive output pin.
PC.14
I/O
MFP0
General purpose digital I/O pin.
PWM0_CH4
I/O
MFP1
PWM0 channel4 output/capture input.
I2C0_SDA
I/O
MFP2
I2C0 data input/output pin.
DPWM_SN
O
MFP3
Audio DPWM sub-woofer channel negative output pin.
PC.15
I/O
MFP0
General purpose digital I/O pin.
SPI0_SS1
O
MFP1
2nd SPI0 Slave Select pin
DPWM_SP
O
MFP3
Audio DPWM sub-woofer channel positive output pin.
19
32
USB_VDD33
P
MFP0
Power supply for USB, DC 3.3V.
PB.15
I/O
MFP0
General purpose digital I/O pin.
USB_VBUS
P
MFP1
Power supply from USB or HUB.
I2S0_MCLK
O
MFP2
I2S0 master clock output pin.
PB.14
I/O
MFP0
General purpose digital I/O pin.
USB_D-
A
MFP1
USB differential signal D-.
I2S0_DO
O
MFP2
I2S0 data output pin.
PB.13
I/O
MFP0
General purpose digital I/O pin.
USB_D+
A
MFP1
USB differential signal D+.
I2S0_DI
I
MFP2
I2S0 data input pin.
PD.0
I/O
MFP0
General purpose digital I/O pin.
INT3 I MFP1
External interrupt3 input pin.
I2C1_SCL
I/O
MFP2
I2C1 clock pin.
I2C0_SCL
I/O
MFP3
I2C0 clock pin.
I2S0_BCLK
I/O
MFP4
I2S0 bit clock pin.
DPWM_LN
O
MFP5
Audio DPWM left channel negative output pin.
PD.1
I/O
MFP0
General purpose digital I/O pin.
INT4 I MFP1
External interrupt4 input pin.
I2C1_SDA
I/O
MFP2
I2C1 data p input/output in.
I2C0_SDA
I/O
MFP3
I2C0 data input/output pin.
I2S0_LRCK
I/O
MFP4
I2S0 left right channel clock pin.
DPWM_LP
O
MFP5
Audio DPWM left channel positive output pin.
PD.2
I/O
MFP0
General purpose digital I/O pin.
Pins
QFN48
(6x6)
20 33
LQFP64
(7x7)
30 30
31 31
32
LQFP64
(10x10)
Pin Name Type MFP Description
ISD94100 SERIES TECHNICAL REFERENCE MANUAL
21 34
22 35
23 36 33
24 37 34
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ISD94100 Series Technical Reference Manual
TRACE_CLK
O
MFP1
TPIU for ETM Tx trace clock output pin.
SPI1_MOSI
I/O
MFP2
SPI1 MOSI (Master Out, Slave In) pin.
I2S0_MCLK
O
MFP3
I2S0 master clock output pin.
I2C1_SCL
I/O
MFP4
I2C1 clock pin.
TM0
I/O
MFP5
Timer0 event counter input / toggle output.
PD.3
I/O
MFP0
General purpose digital I/O pin.
TRACE_DATA0
O
MFP1
TPIU for ETM Tx trace data output bit0.
SPI1_MISO
I/O
MFP2
SPI1 MISO (Master In, Slave Out) pin.
I2S0_LRCK
I/O
MFP3
I2S0 left right channel clock pin.
DMIC_CLK1
O
MFP4
Digital microphone channel 1 clock output pin.
TM2
I/O
MFP5
Timer2 event counter input / toggle output.
PD.4
I/O
MFP0
General purpose digital I/O pin.
TRACE_DATA1
O
MFP1
TPIU for ETM Tx trace data output bit1.
SPI1_CLK
I/O
MFP2
SPI1 serial clock pin.
I2S0_DI
I
MFP3
I2S0 data input pin.
DMIC_DAT1
I
MFP4
Digital microphone channel 1 data input pin.
TM1
I/O
MFP5
Timer1 event counter input / toggle output.
PD.5
I/O
MFP0
General purpose digital I/O pin.
TRACE_DATA2
O
MFP1
TPIU for ETM Tx trace data output bit2.
SPI1_SS
I/O
MFP2
SPI1 Slave Select pin.
I2S0_DO
O
MFP3
I2S0 data output pin.
DMIC_CLK0
O
MFP4
Digital microphone channel 0 clock output pin.
DPWM_RN
O
MFP5
Audio DPWM right channel negative output pin.
PD.6
I/O
MFP0
General purpose digital I/O pin.
TRACE_DATA3
O
MFP1
TPIU for ETM Tx trace data output bit3.
SPI1_I2SMCLK
O
MFP2
SPI1 I2S master clock output pin
I2S0_BCLK
I/O
MFP3
I2S0 Bit Clock pin.
DMIC_DAT0
I
MFP4
Digital microphone channel 0 data input pin.
DPWM_RP
O
MFP5
Audio DPWM right channel positive output pin.
PD.7
I/O
MFP0
General purpose digital I/O pin.
PWM0_CH5
I/O
MFP1
PWM0 channel5 output/capture input.
INT1 I MFP2
External interrupt1 input pin.
PD.8
I/O
MFP0
General purpose digital I/O pin.
ICE_CLK
I
MFP1
Serial wired debugger clock pin
Pins
QFN48
(6x6)
25 38 35
26 39 36
27 40 37
LQFP64
(7x7)
LQFP64
(10x10)
Pin Name Type MFP Description
ISD94100 SERIES TECHNICAL REFERENCE MANUAL
28 41 38
42 39
43 40
29 44 41
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ISD94100 Series Technical Reference Manual
TM0
I/O
MFP2
Timer0 event counter input / toggle output.
I2C1_SCL
I/O
MFP3
I2C1 clock pin.
I2C0_SCL
I/O
MFP4
I2C0 clock pin.
DPWM_SN
O
MFP5
Audio DPWM sub-woofer channel negative output pin.
PD.9
I/O
MFP0
General purpose digital I/O pin.
ICE_DAT
I/O
MFP1
Serial wired debugger data pin
TM0_EXT
I/O
MFP2
Timer0 external capture input.
I2C1_SDA
I/O
MFP3
I2C1 data input/output pin.
I2C0_SDA
I/O
MFP4
I2C0 data input/output pin.
DPWM_SP
O
MFP5
Audio DPWM sub-woofer channel positive output pin.
PD.10
I/O
MFP0
General purpose digital I/O pin.
INT5 I MFP1
External interrupt5 input pin.
EADC0_ST
I
MFP2
EADC0 external trigger input.
PD.11
I/O
MFP0
General purpose digital I/O pin.
UART0_TXD
O
MFP1
UART0 Data transmitter output pin.
INT2 I MFP2
External interrupt2 input pin.
PD.12
I/O
MFP0
General purpose digital I/O pin.
UART0_RXD
I
MFP1
UART0 Data receiver input pin.
INT3 I MFP2
External interrupt3 input pin.
PWM0_CH3
I/O
MFP3
PWM0 channel3 output/capture input.
INT0 I MFP4
External interrupt0 input pin.
PD.13
I/O
MFP0
General purpose digital I/O pin.
SPI0_SS1
O
MFP1
2nd SPI0 Slave Select pin
EADC0_CH10
A
MFP2
EADC0 channel10 analog input.
PD.14
I/O
MFP0
General purpose digital I/O pin.
UART0_nCTS
I
MFP1
Clear to Send input pin for UART0.
EADC0_CH11
A
MFP2
EADC0 channel11 analog input.
I2C0_SCL
I/O
MFP3
I2C0 clock pin.
UART0_TXD
O
MFP4
UART0 data transmitter output pin.
I2C1_SCL
I/O
MFP5
I2C1 clock pin.
PD.15
I/O
MFP0
General purpose digital I/O pin.
UART0_nRTS
O
MFP1
Request to Send output pin for UART0.
EADC0_CH12
A
MFP2
EADC0 channel12 analog input.
I2C0_SDA
I/O
MFP3
I2C0 data input/output pin.
Pins
QFN48
(6x6)
30 45 42
LQFP64
(7x7)
43
44
LQFP64
(10x10)
Pin Name Type MFP Description
ISD94100 SERIES TECHNICAL REFERENCE MANUAL
45
46 46
31 47 47
32 48 48
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UART0_RXD
I
MFP4
UART0 data receiver input pin.
I2C1_SDA
I/O
MFP5
I2C1 data input/output pin.
PA.0
I/O
MFP0
General purpose digital I/O pin.
SPI0_SS1
O
MFP1
2nd SPI0 Slave Select pin
EADC0_CH0
A
MFP2
EADC0 channel0 analog input.
DMIC_DAT0
I
MFP3
Digital microphone channel 0 data input pin.
PA.1
I/O
MFP0
General purpose digital I/O pin.
SPI0_MOSI1
I/O
MFP1
2nd SPI0 MOSI (Master Out, Slave In) pin.
EADC0_CH1
A
MFP2
EADC0 channel1 analog input.
DMIC_CLK0
O
MFP3
Digital microphone channel 0 clock output pin.
PA2
I/O
MFP0
General purpose digital I/O pin.
SPI0_MISO1
I/O
MFP1
2nd SPI0 MISO (Master In, Slave Out) pin.
EADC0_CH2
A
MFP2
EADC0 channel2 analog input.
DMIC_DAT1
I
MFP3
Digital microphone channel 1 data input pin.
PA.3
I/O
MFP0
General purpose digital I/O pin.
SPI0_MOSI0
I/O
MFP1
1st SPI0 MOSI (Master Out, Slave In) pin.
EADC0_CH3
A
MFP2
EADC0 channel3 analog input.
DMIC_CLK1
O
MFP3
Digital microphone channel 1 clock output pin.
PA.4
I/O
MFP0
General purpose digital I/O pin.
SPI0_MISO0
I/O
MFP1
1st SPI0 MISO (Master In, Slave Out) pin.
EADC0_CH4
A
MFP2
EADC0 channel4 analog input.
DPWM_LN
O
MFP3
Audio DPWM left channel negative output pin.
PA.5
I/O
MFP0
General purpose digital I/O pin.
SPI0_CLK
I/O
MFP1
SPI0 serial clock pin.
EADC0_CH5
A
MFP2
EADC0 channel5 analog input.
DPWM_LP
O
MFP3
Audio DPWM left channel positive output pin.
PA.6
I/O
MFP0
General purpose digital I/O pin.
SPI0_SS0
I/O
MFP1
1st SPI0 Slave Select pin
EADC0_CH6
A
MFP2
EADC0 channel6 analog input.
PA.7
I/O
MFP0
General purpose digital I/O pin.
UART0_TXD
O
MFP1
UART0 data transmitter output pin.
EADC0_CH7
A
MFP2
EADC0 channel7 analog input.
SPI2_MISO
I/O
MFP4
SPI2 MISO (Master In, Slave Out) pin; or I2S2 data input pin.
PA.8
I/O
MFP0
General purpose digital I/O pin.
Pins
QFN48
(6x6)
33 49 49
34 50 50
35 51 51
LQFP64
(7x7)
LQFP64
(10x10)
Pin Name Type MFP Description
ISD94100 SERIES TECHNICAL REFERENCE MANUAL
36 52 52
37 53 53
38 54 54
39 55 55
40 56 56
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UART0_RXD
I
MFP1
UART0 data receiver input pin..
EADC0_CH8
A
MFP2
EADC0 channel8 analog input.
SPI2_MOSI
I/O
MFP4
SPI2 MOSI (Master Out, Slave In) pin; or I2S2 data output pin.
PA.9
I/O
MFP0
General purpose digital I/O pin.
I2C0_SCL
I/O
MFP1
I2C0 Serial Clock pin
EADC0_CH9
A
MFP2
EADC0 channel9 analog input.
SPI2_SS
I/O
MFP4
SPI2 slave select pin; or I2S2 left right channel clock pin.
PA.10
I/O
MFP0
General purpose digital I/O pin.
I2C0_SDA
I/O
MFP1
I2C0 data input/output pin.
EADC0_ST
I
MFP2
EADC0 external trigger input.
DPWM_RN
O
MFP3
Audio DPWM right channel negative output pin.
SPI2_CLK
I/O
MFP4
SPI2 clock pin; or I2S2 bit clock pin.
PA.11
I/O
MFP0
General purpose digital I/O pin.
I2C0_SMBSUS
O
MFP1
I2C0 SMBus SMBSUS# pin (PMBus CONTROL pin)
TM0
I/O
MFP2
Timer0 event counter input / toggle output.
DPWM_RP
O
MFP3
Audio DPWM right channel positive output pin.
PA.12
I/O
MFP0
General purpose digital I/O pin.
I2C0_SMBAL
O
MFP1
I2C0 SMBus SMBALERT# pin
TM0_EXT
I/O
MFP2
Timer0 external capture input.
SPI2_I2SMCLK
O
MFP4
SPI2 I2S master clock output pin.
PA.13
I/O
MFP0
General purpose digital I/O pin.
CLKO
O
MFP1
Clock Output pin.
INT0 I MFP2
External interrupt0 input pin.
DPWM_SN
O
MFP3
Audio DPWM sub-woofer channel negative output pin.
I2C1_SCL
I/O
MFP4
I2C1 clock pin.
PA.14
I/O
MFP0
General purpose digital I/O pin.
SPI0_SS0
I/O
MFP1
1st SPI0 Slave Select pin
TM1
I/O
MFP2
Timer1 event counter input / toggle output.
DPWM_SP
O
MFP3
Audio DPWM sub-woofer channel positive output pin.
I2C1_SDA
I/O
MFP4
I2C1 data input/output pin.
PA.15
I/O
MFP0
General purpose digital I/O pin.
INT0 I MFP1
External interrupt0 input pin.
TM1_EXT
I/O
MFP2
Timer1 external capture input.
Pins
QFN48
(6x6)
41 57 57
42 58 58
43 59 59
44 60 60
LQFP64
(7x7)
LQFP64
(10x10)
Pin Name Type MFP Description
ISD94100 SERIES TECHNICAL REFERENCE MANUAL
45 61 61
46 62 62
47 63 63
48 64 64
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ISD94100 Series Technical Reference Manual
Note:
1. Part number ISD941XXBYI and ISD941XXBRI do not provide DPWM and DMIC functionality.
Table 4.4-1 Pin Descript ion
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EADC0_CH0
EADC0_CH1
EADC0_CH2
EADC0_CH3
EADC0_CH4
EADC0_CH5
EADC0_CH6
EADC0_CH7
EADC0_CH8
EADC0_CH9
EADC0_ST
TM0
TM0_EXT
INT0
TM1
TM1_EXT
I2C0_SCL
I2C0_SDA
TM2
TM2_EXT
PWM0_CH0
PWM0_CH1
PWM0_CH2
PWM0_CH3
PWM0_CH4
PWM0_CH5
I2S0_D
I2S0_DO
I2S0_MCLK
X32_OUT
X32_IN

4.5 GPIO Alternate Function Summary

MFP* = Multi -f unct i on pi n. (Reference secti on ) Pin function is defined in SYS_GPx_MFPx registers. For example PA0~7 pin functions are defined in SYS_GPA_MFPL register,
and PA8~15 pin functions are defined in SYS_GPA_MFPH register.
MFP0 MFP1 MFP2 MFP3 MFP4 MFP5
PA.0 SPI0_SS1 PA.1 SPI0_MOSI1 PA.2 SPI0_MISO1 PA.3 SPI0_MOSI0 PA.4 SPI0_MISO0 PA.5 SPI0_CLK PA.6 SPI0_SS0 PA.7 UART0_TXD PA.8 UART0_RXD PA.9 I2C0_SCL PA.10 I2C0_SDA PA.11 I2C0_SMBSUS PA.12 I2C0_SMBAL PA.13 CLKO PA.14 SPI0_SS0 PA.15 INT0
DMIC_DAT0 DMIC_CLK0 DMIC_DAT1 DMIC_CLK1 DPWM_LN DPWM_LP
SPI2_MISO SPI2_MOSI SPI2_SS
DPWM_RN SPI2_CLK
DPWM_RP
SPI2_I2SMCLK
DPWM_SN I2C1_SCL
DPWM_SP I2C1_SDA
ISD94100 SERIES TECHNICAL REFERENCE MANUAL
PB.0 PWM0_SYNC_IN PB.1 PWM0_SYNC_OUT PB.2 PWM0_CH0 PB.3 PWM0_CH1 PB.4 UART0_nCTS PB.5 XT1_OUT PB.6 XT1_IN PB.7 UART0_nRTS PB.8 UART0_TXD PB.9 UART0_RXD PB.13 USB_D+ PB.14 USB_D­PB.15 USB_VBUS PC.0 I2C1_SCL PC.1 I2C1_SDA
PWM0_CH0
PWM0_CH1
PWM0_CH2
DMIC_DAT1 UART0_RXD PWM0_CH3
DMIC_CLK1 UART0_TXD PWM0_CH4 I2C0_SDA I2C1_SDA DMIC_DAT0 I2C0_SCL I2C1_SCL DMIC_CLK0
I
SPI1_MOSI
SPI1_MISO
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ISD94100 Series Technical Reference Manual
TM3
TM3_EXT
CLKO
SPI2_MOSI
SPI2_MISO
SPI2_CLK
SPI2_SS
SPI2_I2SMCLK
PWM0_BRAKE0
PWM0_BRAKE1
I2C0_SCL
I2C0_SDA
I2C1_SCL
I2C1_SDA
SPI1_MOSI
SPI1_MISO
SPI1_CLK
SPI1_SS
SPI1_I2SMCLK
INT1
TM0
TM0_EXT
EADC0_ST
INT2
INT3
EADC0_CH10
EADC0_CH11
EADC0_CH12
MFP0 MFP1 MFP2 MFP3 MFP4 MFP5
PC.2 I2C1_SMBSUS PC.3 I2C1_SMBAL PC.4 PWM0_CH2 PC.5 INT1 PC.6 INT2 PC.7 SPI0_SS0 PC.8 SPI0_MOSI1 PC.9 SPI0_MISO1 PC.10 SPI0_MOSI0 PC.11 SPI0_MISO0 PC.12 SPI0_CLK PC.13 PWM0_CH3 PC.14 PWM0_CH4 PC.15 SPI0_SS1 PD.0 INT3
ISD94100 SERIES TECHNICAL REFERENCE MANUAL
PD.1 INT4 PD.2 TRACE_CLK
SPI1_CLK
SPI1_SS
SPI1_I2SMCLK
DPWM_RN DPWM_RP
DPWM_LN
DPWM_LP
DPWM_SN
DPWM_SP
I2C0_SCL I2S0_BCLK DPWM_LN
I2C0_SDA I2S0_LRCK DPWM_LP
I2S0_MCLK I2C1_SCL TM0 PD.3 TRACE_DATA0 PD.4 TRACE_DATA1 PD.5 TRACE_DATA2 PD.6 TRACE_DATA3 PD.7 PWM0_CH5 PD.8 ICE_CLK PD.9 ICE_DAT PD.10 INT5 PD.11 UART0_TXD PD.12 UART0_RXD PD.13 SPI0_SS1 PD.14 UART0_nCTS PD.15 UART0_nRTS
Note:
1. Part number ISD941XXBYI does not provide DPWM and DMIC functionality.
I2S0_LRCK DMIC_CLK1 TM2
I2S0_DI DMIC_DAT1 TM1
I2S0_DO DMIC_CLK0 DPWM_RN
I2S0_BCLK DMIC_DAT0 DPWM_RP
I2C1_SCL I2C0_SCL DPWM_SN
I2C1_SDA I2C0_SDA DPWM_SP
PWM0_CH3 INT0
I2C0_SCL UART0_TXD I2C1_SCL I2C0_SDA UART0_RXD I2C1_SDA
Table 4.5-1 GPIO Alternate Function Summary
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ISD94100 Series Technical Reference Manual
ARM
Cortex
TM
-M4
(DSP/FPU/ETM)
200MHz
APROM
512KB
SRAM 192KB
LDROM 4KB
Data Flash share
with APROM
POR / LVR / BOD
CPU core LDO
1.2V
Memory
Power control Timer / PWM
Timer x4
WDT x1/WWDT x1
PWM x6
RTC
Analog Interface
12-bit ADC 13-ch
HS Osc.
48.0/49.152MHz LS Osc. 10KHz
PLL 100~500MHz
HS Ext. Crystal
4~24.576MHz
Clock control
LS Ext. Crystal
32.768KHz
PDMA
16-ch
GPIO
External interrupt
General Purpose
IO
Connectivity
UART0 x1
I2C x2
(SPI/I2S) x2
SPI (Quad) x1
AHB Bus
Bridge
Security
CRC
APB Bus
USB 1.1 Device
I2S
DMIC
DPWM

5 BLOCK DIAGRAM

5.1 ISD94100 Series Block Diagram

Figure 5.1-1 ISD94100 Series Block Diagram
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ISD94100 Series Technical Reference Manual

6 FUNCTIONAL DESCRIPTION

6.1 ARM® Cortex®-M4 Core

The Cortex®-M4 processor, a co nfigurable, multistage, 32-bit RI SC processor, has three AMBA AHB-Lite interfaces for best parallel performance and includes an NVIC component. The processor with optional hard ware deb ug functi onality c an execut e Thum b code and is c ompatible with oth er
®
Cortex Handler mode is entered a s a result of an exception. An ex ception return can onl y be issued in Handler mode. Thr ead m ode is enter ed o n Res et, an d can be e ntere d as a res ult of an exception return. The Cortex includes floating point arithmetic functionality. The ISD94100 series contains an embedded Cortex M4 and Cortex processor.
-M profile processo rs. The profile sup ports two m odes -Thread mode an d Handler mode.
®
-M4F is a processor with the same capability as the Cortex®-M4 processor and
®
-M4F processor. Thr oughout this docum ent, the nam e Cortex®-M4 refers to both Cort ex®-
®
-M4F processors. The following figure shows the functional controller of the
ISD94100 SERIES TECHNICAL REFERENCE MANUAL
Figure 6.1-1 Cortex®-M4 Block Diagram
®
Cortex
-M4 processor features:
A low gate count processor core, with low latency interrupt processing that has:
A subset of the Thumb instruction set, defined in the ARMv7-M Architecture
Reference Manual
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ISD94100 Series Technical Reference Manual
Banked Stack Pointer (SP)  Hardware integer divide instructions , SDI V and UDIV  Handler and Thread modes  Thumb and Debug states  Support for interruptible-co ntinued instructions LDM, ST M, PUSH, and POP for
low interrupt latency
Automatic processor state saving and restoration for low latency Interrupt Service
Routine (ISR) entry and exit
Support for ARMv6 big-en d ian byte-invariant or little-endian accesses  Support for ARMv6 unaligned accesses
®
Floating Point Unit (FPU) in the Cortex
32-bit instructions for single-precision (C float) data-processing operations  Combined Multipl y and Accumulate instructions f or increased precision (Fuse d
MAC)
Hardware support for conversion, addition, subtraction, multiplication with optional
accumulate, division, and square-root
-M4F processor providing:
Hardware support for denormals and all IEEE rounding modes  32 dedicated 32-bit single precision registers, also addressable as 16 double-word
registers
Decoupled three stage pipeline
Nested Vectored Interrupt Contr o ll er ( NVIC) clos ely integrated with the proces s or core
to achieve low latency interrupt processing. Features include: External interrupts. Conf igurable from 1 to 240 (the ISD94100 series configur ed
with 97 interrupts)
Bits of priority, configurable from 3 to 8  Dynamic reprioritization of interrupts  Priority grouping which en ables s elect ion of pr eem pting int errupt levels a nd non-
preempting interrupt levels
Support for tail-chaining and late arrival of interrupts, which enables back-to-back
interrupt processing without the overhead of state saving and restoration between interrupts.
Processor state autom atically sa ved on inter rupt e ntry, and restore d on inter rupt
exit with on instruction overhead
Support for Wake-up Interrupt Controller (WIC) with Ultra-low Power Sleep mode
Memory Protection Unit (MPU). An optional MPU for memory protection, includin g:
ISD94100 SERIES TECHNICAL REFERENCE MANUAL
Eight memory regions  Sub Region Disable (SRD), enabling efficient use of memory regions  The ability to enable a background region that im plements the default memor y
map attributes
Low-cost debug solution that features:
Debug access to all memory and registers in the system, including access to
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ISD94100 Series Technical Reference Manual
memory mapped devices, access to internal core registers when the core is halted, and access to debug control registers even while SYSRESETn is asserted.
Serial Wire Debug Port(SW-DP) debug access  Optional Flash Patch and Breakpoint (FPB) unit for implementing breakpoints and
code patches
Optional Data Watc hpoint and Trace (DWT) unit for im plementing watchpoints,
data tracing, and system profiling
Optional Instrumentation Trace Macrocell (ITM) for support of printf() style
debugging
Optional Trace Port Interf ace Unit (TPIU) for bridgin g to a Trace Port Analyzer
(TPA), including Single Wire Output (SWO) mode
Bus interfaces:
Three Advanced High-performance Bus-Lite (AHB-Lite) interfaces: ICode, Dcode,
and System bus interfaces
Private Peripheral Bus (PPB) based on Advanced Peripheral Bus (APB) interface  Bit-band support that includes atomic bit-band write and read operations.  Memory access alignment  Write buffer for buffering of write data  Exclusive access transfers for multiprocessor systems
ISD94100 SERIES TECHNICAL REFERENCE MANUAL
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ISD94100 Series Technical Reference Manual
Low Voltage
Reset
Power-on
Reset
Brown-out
Reset
Reset Pulse Width
~3.2ms
WDT/WWDT
Reset
System Reset
~50k ohm
@3.3v
Reset Pulse Width
2 system clocks
nRESET
V
DD
CHIP Reset
CHIPRST(SYS_IPRST0[0])
CPU Reset
CPURST(SYS_IPRST0[1])
CPU Lockup
Reset
MCU Reset
SYSRSTREQ(AIRCR[2])
LVREN(SYS_BODCTL[7])
BODRSTEN(SYS_BODCTL[3])
POROFF(SYS_PORCTL[15:0])
Reset Pulse Width
64 WDT clocks
Reset Pulse Width
2 system clocks
Glitch Filter
66 us
Software Reset

6.2 System Manager

6.2.1 Overview

System management includes the following sections:
System Reset  System Power Distribution  SRAM Memory Organization  System Timer (SysTick)  Nested Vectored Interrupt Controller (NVIC)  System Control register

6.2.2 System Reset

A system reset sets all registers to their rese t values except s ome of the registers listed in Table
6.2.2-1, whic h wil l maintain their or ig in a l va lu es after reset. A system reset can be trigger ed b y one of the nine so urces listed belo w. The reset source can be identified by checking the reset flag bits in the System Reset Status Register (SYS_RSTSTS).
Hardware Reset Sources
- Power-on Reset
- Low level on the nRESET pin
- Watchdog Time-out Reset and Window Watchdog Reset (WDT/WWDT Reset)
- Low Voltage Reset (LVR)
- Brown-out Detector Reset (BOD Reset)
- CPU Lockup Reset
Software Reset Sources
- CHIP Reset: writing 1 to CHIPRST (SYS_IPRST0[0]) will reset whole chip.
- MCU Reset: writing 1 to SYSRESETREQ (AIRCR[2]) will reboot the device,
according to the boot selection defined in configuration byte CONFIG0.
- CPU Reset: writ ing 1 to CPUR ST (SYS_IPRST 0[1]) will reset Cortex Only.
®
-M4 core
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Bit 0 = 1
Bit 2 = 1
Bit 7 =
0x0
-
Reload from CONFIG0
Reload from CONFIG0
Reload from CONFIG0
Reload from CONFIG0
0x0
-
0x1
0x1
Reload from CONFIG0
Reload from CONFIG0
0x3
-
0x0
-
0x0
-
0x0
-
0x1
-
0x0
-
Reload from CONFIG0
Reload from CONFIG0
Figure 6.2-1 System Reset Sources
There are a total of 9 res et s ourc es in the ISD94100 series . In g ener a l, C PU r ese t is us ed to res et
®
Cortex are small differences between each reset source and they are listed in Table 6.2.2-1.
Reset Sources Register
-M4 only; the other reset sources will reset Cortex®-M4 and all peripherals. However, there
POR NRESET WDT LVR BOD Lockup CHIP MCU CPU
SYS_RSTSTS
CHIPRST (SYS_IPRST0[0])
BODEN (SYS_BODCTL[0])
BODVL (SYS_BODCTL[18:16])
BODRSTEN (SYS_BODCTL[3])
HXTEN (CLK_PWRCTL[0])
ISD94100 SERIES TECHNICAL REFERENCE MANUAL
LXTEN (CLK_PWRCTL[1])
WDTCKEN (CLK_APBCLK0[0])
HCLKSEL (CLK_CLKSEL0[2:0])
WDTSEL (CLK_CLKSEL1[1:0])
B it 1 = 1
-
Reload from CONFIG0
Reload from CONFIG0
-
-
Reload from CONFIG0
0x3
Bit 3 = 1 Bit 4 = 1 Bit 8 = 1 Bit 0 = 1 Bit 5 = 1
- - - - - -
Reload from CONFIG0
Reload from CONFIG0
- - - - - -
- - - 0x1 - -
Reload from CONFIG0
- - - - - -
- Reload
Reload from CONFIG0
Reload from CONFIG0
from CONFIG0
Reload from CONFIG0
Reload from CONFIG0
Reload from CONFIG0
Reload from CONFIG0
Reload from CONFIG0
Reload from CONFIG0
Reload from CONFIG0
Reload from CONFIG0
1
-
-
HXTSTB (CLK_STATUS[0])
LXTSTB (CLK_STATUS[1])
PLLSTB (CLK_STATUS[2])
HIRCSTB (CLK_STATUS[4])
CLKSFAIL (CLK_STATUS[7])
RSTEN (WDT_CTL[1])
WDTEN (WDT_CTL[7])
-
-
-
-
0x0
Reload from CONFIG0
- - - - - -
- - - - - -
- - - - - -
- - - - - -
- - - - - -
Reload from CONFIG0
Reload from CONFIG0
- Reload from CONFIG0
- -
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ISD94100 Series Technical Reference Manual
0x0700
0x0700 0x0000
0x0000
0x0000
0x0000
0x3F0800
0x3F0800
0x0000
0x0000
0x3F
0x3F
Reload from CONFIG0
Reload from CONFIG0
Reload from CONFIG1
Reload from CONFIG1
Reload from CONFIG0
Reload from CONFIG0
Reload based on CONFIG0
Reload based on CONFIG0
Reset Value Reset Value
nRESET
0.3 V
DD
0.7 V
DD
nRESET Reset
66 us
66 us
WDT_CTL except bit 1 and bit 7
WDT_ALTCTL WWDT_RLDCNT WWDT_CTL WWDT_STATUS WWDT_CNT BS
(FMC_ISPCTL[1])
FMC_DFBA
CBS (FMC_ISPSTS[2:1))
VECMAP (FMC_ISPSTS[23:9])
Other Peripheral Registers
FMC Registers
0x0700
0x0000 0x0000
0x3F0800
0x0000
0x3F
Reload from CONFIG0
Reload from CONFIG1
Reload from CONFIG0
Reload based on CONFIG0
-
0x0700 0x0700 - 0x0700 - -
0x0000 0x0000 - 0x0000 - ­ 0x0000 0x0000 - 0x0000 - -
0x3F0800 0x3F0800 - 0x3F0800 - -
0x0000 0x0000 - 0x0000 - -
0x3F 0x3F - 0x3F - -
Reload from CONFIG0
Reload from CONFIG1
Reload from CONFIG0
Reload based on CONFIG0
Reload from CONFIG0
Reload from CONFIG1
Reload from CONFIG0
Reload based on CONFIG0
- Reload from CONFIG0
- Reload from CONFIG1
- Reload from CONFIG0
- Reload based on CONFIG0
- -
- -
- -
- -
ISD94100 SERIES TECHNICAL REFERENCE MANUAL
Note: ‘-‘ means that the value of register keeps original setting.
Table 6.2.2-1 Reset Value of Registers
6.2.2.1 nRESET Reset
nRESET is t riggered by pul ling nRESET pin low. nRESET pin is an asynchr onous reset input pin so that it can be used to reset the system any time. Pull nRESET pin to < 0.3 * V voltage (> 0.7* V
) presented on nRESET pin f or >66us can exit the reset state. See nR ESET
DD
reset waveform in Figure 6.2-2. After an nRES ET reset, the PINRF bit (SYS_RSTST S[1]) wi ll b e set , indicating the previous res et source is an nRESET reset. Writing 1 to PINRF clears the bit.
f or > 66us will reset the chip. Once entered reset state, only high
DD
Figure 6.2-2 nRESET Reset Waveform
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ISD94100 Series Technical Reference Manual
V
DD
V
BODL
BODOUT
BODRSTEN
Brown-out
Reset
T
1
(< BODDGSEL)
T
2
(= BODDGSEL
)
T
3
(= BODDGSEL)
Hysteresis
V
BODH
6.2.2.2 Power-on Reset (POR)
System power-on gen erate s the Po wer-on r eset (POR). When po wer is app lie d, the POR m odule detects the rising voltage and generates reset signal. The reset signal stays active until the voltage is ready for MCU operation . PORF bit (SYS_RST STS[0]) wil l be set to 1 to indicate a POR reset event. The PORF bit (SYS_RSTSTS[0]) can be cleared by writing 1 to it.
6.2.2.3 Low Voltage Reset (LVR)
Writing 1 to LVREN bit (SYS_BODCTL[7]) enables the Low Voltage Reset (LVR) function. If enabled, the LVR function module keeps monitoring V
voltage has been lo wer than V
If V
DD
LVR
Once triggered, the LVR reset keeps the chip in reset state until the V been above V
LVR
.
By default, Low Voltage Reset is enabled without De-glitch function.
6.2.2.4 Brown-out Detector Reset (BOD Reset)
Writing 1 to Brown-out Detector Enable Bit BODEN (SYS_BODCTL[0]) enables the Brown-out Detector (BOD) func ti on. In addition, wr iti ng 1 t o t he B O DRSTEN (SYS_BODCT L[3]) ena bl es th e BOD reset function. When enabled, the BOD module monitors V voltage is lower than V time (defined by BODDGSEL bits in SYS_BODCTL[10:8]), a BOD reset will be triggered. The BOD reset keeps the chip in res et state until a condition is met that V
for more than De-glitch time (defined b y BODDGSEL).
V
BOD
Initial values of BODEN, BODVL and BODRSTEN (SYS_BODCTL[3]) are defined in flash configuration byte CONFIG0. Figure 6.2-3 shows the Brown-out Detector waveform.
ISD94100 SERIES TECHNICAL REFERENCE MANUAL
(defined by BODVL bits in SYS_BODCTL[18:16]) for more than De-glitch
BOD
during system operation.
DD
, a LVR reset will be triggered and the chip wil l be reset.
voltage rises back and has
DD
during system operation, if VDD
DD
voltage has been higher than
DD
Figure 6.2-3 Brown-out Detector (BOD) Waveform
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ISD94100 Series Technical Reference Manual
Normal /
6.2.2.5 Watchdog Timer Reset ( WDT)
A Watchdog reset can be identified by checking WDTRF bit (SYS_RSTSTS[2]).
6.2.2.6 CPU Lockup Reset
CPU enters lockup state after CPU produces hardfault at hardfault handler. This is the result of the CPU being locked because of an unrecoverable exception, following the activation of the processor’s built in system state protection hardware. When chip is in debug mode, the CPU lockup reset will be ignored.
6.2.2.7 CPU Reset , CHIP Reset and MCU Reset
A CPU Rese t only resets the Cortex®-M4 cor e, while all other peripherals k eep the state as is. Writing 1 to CPURST bit(SYS_IPRST0[1]) triggers a CPU reset.
CHIP Reset acts the same as Power-on Reset. The CPU and all peripherals are reset and BS(FMC_ISPCTL[1]) bit is automatically reloaded from CONFIG0. Writing 1 to CHIPRST bit (SYS_IPRST0[1]) triggers a CHIP Reset.
MCU Reset is s imilar to C HIP Reset as the only differenc e is that MCU Reset does not reloa d BS(FMC_ISPCTL[1]) from CONFIG0; so where device will boot from (APROM or LDROM) still depends on the old value in BS(FMC_ISPCTL[1]). Writing 1 to SYSRESETREQ bit (AIRCR[2]) triggers a MCU Reset.
6.2.2.8 Reset Flag
After wake-up or reset from each power modes, reset flag in SYS_RSTSTS register will take effect when system return Normal mode. Table 6.2.2-2 shows the LVRF (SYS_RSTSTS[3]), PINRF (SYS_RSTSTS[1]) and PORF (SYS_RSTSTS[0]) effect when wake-up or reset from different power modes. Note that LVR function cannot be used in DPD mode.
ISD94100 SERIES TECHNICAL REFERENCE MANUAL
Conditions Flag
Power Mode
Idle
SPD0/1
DPD
Power-on Reset
V - - - V V V
- V - - V - -
- - V - - V ­V - - - V V V
- V - - V V V
- - V - - V V
- - - V - V V V - - - V V V
- - V - - V V
- - - V V V V
Low Voltage Reset
nRESET Reset
Wakeup
LVRF SYS_RSTSTS[3]
Table 6.2.2-2 Reset Flag Table

6.2.3 System Power Distribution

ISD94100 series de vice power distribution is d iv id e d in t o:
Analog power from AV
and AVSS: provides the power for analog components
DD
operation.
PINRF SYS_RSTSTS[1]
PORF SYS_RSTSTS[0]
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ISD94100 Series Technical Reference Manual
AV
DD
AV
SS
V
DD
SRAM
V
DD
to 1
.2V
LDO
POR33
PLL
Flash
Power On
Control
PB
.5
PB
.6
GPIOs except PB
.13~PB
.
15
1
.2V
LDO
_CAP
1
uF
I94100 Series Power Distribution
PC
.0
PC.1
V
SS
POR12
IO Cell
10 KHz
LIRC
Oscillator
48.0/49.152 MHz HIRC
Oscillator
32.768
kHz
crystal
oscillator
Digital
Logic
4~
24.
576
MHz crystal
oscillator
Low Voltage Reset Brown
-out Detector
12
-
bit ADC
PB.13
~PB.
15
USB_V
DD33
USB_V
SS
IO Cell
USB 1
.
1
PHY
Digital power from VDD and VSS: supplies the power to the internal regulator which
provides a regulated 1.2 V power for digital operation.
USB transceiver power from USB_V
transceiver.
Analog power (AV
) should be at the same voltage level as digital power (VDD).
DD
Both power supplies should have decoupling capacitors placed as close as possible to pins preferably with no via. The outputs of interna l voltage regulator, LDO_CAP, requires an external c apacitor which shoul d be located close t o LDO_CAP pin and returne d direc tly t o V distribution of the ISD94100 series.
offers the power for operating the USB
DD33
. The Figure 6.2-4 shows the power
SS
ISD94100 SERIES TECHNICAL REFERENCE MANUAL
Figure 6.2-4 ISD94100 Series Power Distribution Diagram

6.2.4 Power Modes

The ISD94100 series p ower m ode include Norm al mode, I dle mode and Power-d own m ode. The system starts up in Normal mode. In Idle mode, only CPU clock is disabled while other peripherals work normally. If system is waiting for an interrupt only, the user can set system in Idl e mode to save power and wake-up q uickly. The user can set system into Power-down m ode when s ystem does not need to work for a long tim e. ISD94100 series provides sever al po wer-down modes with different power consumption level.
The ISD94100 series includes the following power modes:
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Normal mode
The system starts up in Normal mode. All clock sources and peripheral can be enabled or disabled by user in register CL K_PWRCTL (System Power-down Contr ol Register), CLK_AHBCLK (AH B Devices Clock Enable Control Register), CLK_APBCLK0 (APB Devices Clock Enable Control Register 0) and CLK _APBCLK1 (APB Devices Clock Enabl e Control Register 1). The user can disable unused clock or peripheral to save power.
Idle mode
If system is waiting f or an interrupt only. The user can set s ystem in idle m ode. In idle m ode, only CPU clock is disabled, other peripherals work normally. System waits interrupt to wake-up, returns to Normal mode and program execution continues. All interrupts can wak e-up system from Idle mode.
Power-down mode (PD)
In Power-down mode (PD), CPU clock is disabled and LDO enters low power mode. All clock source will be disabled except LXT and LIRC, LXT and LIRC can be controlled by CLK_PWRCTL register. If they are enabled and pe ripheral clock sourc e are selected as LXT or LIRC , the peripheral can keep working in Power-down mode. System waits wake-up source occurred to wake-up, returns to Normal mode and progr am ex ecution c onti nues. In system wake-up phase, system waits f or LDO recovery, and clock sources are enabled aga in and stabl e.
Low Leakage Power-down mode (LLPD)
In Lo w Leakage Power-do wn mode (LLPD), CPU c lock is disabled, LDO enters low power m ode and LDO voltage drops down from current working voltage to 0.9 V to save power. All clock source will be disabled except LXT and LIRC, LXT and LIRC can be controlled by CLK_PWRCTL register. If they are enabled and pe ripheral clock sourc e are selected as LXT or LIR C, the peripheral can keep working in Low Leakage Power-down mode. System waits wake-up source occurred to wake­up, returns to Nor mal mode and progr am execution contin ues . In system wake-up phase, besides waiting for LDO recovery and clock sour ces are enabled and s tab le, system also needs t o wait f or LDO voltage rising to th e original work ing voltage. The Lo w Leakage Po wer-down m ode wak e-up sources are the same as Power-down mode.
Standby Power-down mode 0 (SPD0)
In Standby Power-down m ode 0 (SPD0), all po wer supply is disab led except SPD0 contro l logic, LXT and LIRC. The SPD0 control logic controls Standby Power-down mode wake-up functions and system SRAM bank 0 to retain data. After wake-up f rom Standby Power-down m ode 0 (SPD0), system resets and execut e s code fr om the beginn ing again. All peripheral config uratio ns ret urn t o default value and all SRAM data will be lost except system SRAM bank0 data can be retained. After system wake-up from Standby Power-down mode 0 (SPD0), GPIO will keep their states before entering Standby Power-do wn mode 0. They cannot b e cont ro ll ed b y GPIO or peripherals register after system wake-up, for example: U ART cannot print m ess age and ICE c annot download c ode. To control GPIO, the user have to write 1 to register CLK_IO PDCTL (GPIO Standb y Power-down Control Register) after system wake-up to release GPIO hold state function.
Standby Power-down mode 1 (SPD1)
In St andby Power-down mode 1 ( SPD1), all power su pply is disabled ex cept SPD1 contro l logic, LXT and LIRC. The SPD1 control logic controls Standby Po wer-down mode wake-up func tions. After wake-up from Standb y Power -dow n m ode 1 (SPD1) , system r esets and ex ecutes c ode fr om the beginning again. All peripheral co nf igur at ions r et urn t o d ef ault va lue and al l SRAM data will be lost. After system wake-up from Standby Power-down mode 1 (SPD1), GPIO will keep their states before entering Standby Power-do wn mode 1. They cannot b e contr o ll ed b y GPIO or peripherals register after system wake-up, for example: U ART cannot print m ess age and ICE c annot download c ode. To control GPIO, the user have to write 1 t o regis ter C LK_IOPDCT L (GPIO Standb y Power-down Control Register) after system wake-up to release GPIO hold state function.
ISD94100 SERIES TECHNICAL REFERENCE MANUAL
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LXT, and
if their clock sources are selected as
down
LXT, and
if their clock sources are selected as
1
CPU Run WFI I
Deep Power-down mode (DPD)
In Deep Power-down mode (DPD), all power supply is disabled except DPD control logic. The DPD control logic controls Deep Power-down mode wake-up functions. After wake-up from Deep Power­down mode (DPD), system resets and executes code from the beginning again. All peri pheral configurations return t o def ault va lue and all SRAM data will be lost. T he Deep P o wer-down mode (DPD) wake-up sources include Wake-up Timer and Wake-up Pin (PA.15).

6.2.5 Power Modes Settings and Wake-up Sources

ISD94100 series is equ ipped with power m anagement unit to support different po wer modes for saving power. Table 6.2.5-1 lists all power mode at ISD94100 series.
Power Mode CPU operating maximum
speed
(MHz)
LDO_CAP
(V)
Clock Disable
Normal mode
Turbo mode Idle mode Power-down mode
(PD)
ISD94100 SERIES TECHNICAL REFERENCE MANUAL
Low leakage Power­mode
(LLPD)
Standby Power-down mode 0 (SPD0)
Standby Power-down mode (SPD1)
Deep Power-down mode (DPD)
CPU enter Sleep mode 1.20 Only CPU clock is disabled.
CPU enters Deep Sleep mode 1.20
CPU enters Deep Sleep mode 0.9
160 1.20 All clocks are disabled by control register.
200 1.26 All clocks are disabled by control register.
Most clocks are disabled except LIRC/ only RTC/WDT/Timer/UART peripheral clocks still enable LIRC/LXT.
Most clocks are disabled except LIRC/ only RTC/WDT/Timer/UART peripheral clocks still enable LIRC/LXT.
Power off Floating Only LIRC still enable for wake-up timer usage
Power off Floating Only LIRC still enable for wake-up timer usage
Power off Floating Only LIRC still enable for wake-up timer usage
Table 6.2.5-1 Power Mode Table
There are different po wer mode entry set tings. Each po wer mode has different entr y setting and leaving condition. Table 6.2.5-2 shows the enry setting for each power mode. When chip power-on, chip is running at normal mode. User can enter each mode by configuring SLEEPDEEP (SCR[2]), PDEN (CLK_PWRCT[7]) and PDMSEL (CLK_PMUCTL[2:0]) bits and then execute WFI instruction.
Register/Instruction Mode
SLEEPDEEP (SCR[2])
PDEN (CLK_PWRCTL[7])
PDMSEL (CLK_PMUCTL[2:0])
nstruction
Normal mode Idle mode Power-down mode Low leakage Power-down mode Standby Power-down mode 0
Sep 9, 2019 Page 56 of 928 Rev1.09
0 0 0 NO 0 0 0 YES 1 1 0 YES 1 1 1 YES 1 1 4 YES
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ISD94100 Series Technical Reference Manual
Normal Mode
CPU Clock ON
Power-down Mode
CPU Clock OFF
HXT, HIRC, PCLK OFF
Flash Halt
System reset released
CPU executes WFI Interrupts occur
Idle Mode
CPU Clock OFF
Flash Halt
1. SLEEPDEEP(SCR[2]) = 1
2. PDEN(CLK_PWRCTL[7]) = 1
3. CPU executes WFI
Wake-up events
occur
LXT, LIRC ON
HXT, HIRC, PCLK ON
LXT, LIRC ON
HXT, HIRC, LXT, LIRC, HCLK, PCLK ON
Flash ON
Standby Power-down mode 1 Deep Power-down mode
1 1 5 YES 1 1 6 YES
Table 6.2.5-2 Power Mode Differ ence Table
Note:
1. User must turn on LIRC before entering PD, LLPD and SPD0/1 mode.
There are several wake-up sources in Idle m ode and Power-down m ode. Table 6.2.5-3 l ists the available clocks for each power mode.
Power Mode Normal Mode Idle Mode Power-Down Mode Definition
Entry Condition
Wake-up Sources
Available Clocks After Wake-up
CPU is in active state CPU is in sleep state CPU is in sleep state and all
Chip is in normal mode after system reset released
N/A All interrupts RTC, WDT, I²C, Timer, UART,
All All except CPU clock LXT and LIRC N/A CPU back to normal mode CPU back to normal mode
CPU executes WFI instruction. CPU sets sleep mode enable
clocks stop except LXT and LIRC. SRAM content retained.
and power down enable and executes WFI instruction.
BOD, GPIO, EINT, USBD.
Table 6.2.5-3 Power Mode Differ ence Table
ISD94100 SERIES TECHNICAL REFERENCE MANUAL
Figure 6.2-5 ISD94100 Series Power Mode State Machine
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ISD94100 Series Technical Reference Manual
Normal Mode Idle Mode PD, LLPD SPD0, SPD1 DPD
HXT ON ON Halt Halt Halt
HIRC ON ON Halt Halt Halt
LXT ON ON ON/OFF1 ON/OFF1 Halt
LIRC ON ON ON ON ON/OFF2
PLL ON ON Halt Halt Halt
HCLK/PCLK ON ON Halt Halt Halt
CPU ON Halt Halt Halt Halt
SRAM retention ON ON ON Halt Halt
FLASH ON ON Halt Halt Halt
TIMER ON ON ON/OFF3 Halt Halt
WDT ON ON ON/OFF4 Halt Halt
RTC ON ON ON/OFF5 ON/OFF5 Halt
UART ON ON ON/OFF6 Halt Halt
Others ON ON Halt Halt Halt
Table 6.2.5-4 Clocks in Power Modes
ISD94100 SERIES TECHNICAL REFERENCE MANUAL
Note:
1. LXT ON or OFF depends on S/W setting in normal mode.
2. LIRC ON or OFF depends on S/W setting in normal mode.
3. If TIMER clock source is selected as LIRC/LXT and LIRC/LXT is on.
4. If WDT clock source is selected as LIRC and LIRC is on.
5. If RTC clock source is selected as LXT and LXT is on.
6. If UART clock source is selected as LXT and LXT is on.
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ISD94100 Series Technical Reference Manual
Condition that SPD0/1
After software writes 1 to clear BODIF (SYS_BODCTL[4]).
BODWK(CLK_PMUSTS[4]) is cleared when SPD mode is entered.
After software writes 1 to clear LVRF(SYS_RSTSTS[3])
PORWK(CLK_PMUSTS[0]) is cleared when DPD mode is entered.
After software writes 1 to clear PORF(SYS_RSTSTS[0])
After software write 1 to clear the
After software write 1 to clear the
rising or falling edge
GPxWK(CLK_PMUSTS[11:8]) is cleared when SPD mode is entered.
rising or falling edge
PINWK(CLK_PMUSTS[1]) is cleared when DPD mode is entered.
After software writes 1 to clear TWKF (
up
D (CLK_PMUSTS[6]) is cleared when SPD or DPD mode is entered.
After software writes 1 to clear WKF
[5]) (Wri te
Protected).
After software writes 1 to clear
After software writes 1 to clear
RTCWK(CLK_PMUSTS[5]) is cleared when SPD mode is entered.
Wakeup by RTC tick
RTCWK(CLK_PMUSTS[5]) is cleared when SPD mode is entered.
A
CTSWKF
(
After software writes 1 to clear DATWKF (
A
Wake-up sources in Power-down mode:
Table 6.2.5-5 lis ts all wak e-up sources that c an wake chip up f rom power down m ode to normal mode, wake-up condition and conditions on how to re-enter the power down mode again.
User needs to wait this condition before setting PDEN(CLK_PWRCTL[7]) and execute WFI to enter Power-down mode.
Note that before enter ing each power down mode, user needs to enable wake-up s ource NVIC interrupt and make sure that other peripherals’ interrupt are disabled. In addition, if BOD function is enabled, BOD NVIC interrupt must be enabled before entering power down mode.
Power down mode
Wake-Up
Source
Wake-Up Condition
PD/ LLPD
DPD
System Re-enter Power-Down Mode *
BOD
BOD
LVR LVR Reset Y Y N
POR POR Reset N N Y
POR POR Reset Y Y N
INT External Interrupt Y N N
GPIO GPIO Interrupt Y N N
GPIO(PA~PD)
Wake-up pin
GPIO(PA.15)
Wake-up pin
TIMER
Wakeup timer
WDT
Brown-Out Det ector
Interrupt
Brown-Out Det ector
Interrupt
event, 58-pin
event , 1-pin
Timer Interrupt Y N N
Wakeup by wake-
timer time-out
WDT Interrupt Y N N
Y N N
N Y N
N Y N
N N Y
N Y Y
Px_INTSRC[n] bit. Px_INTSRC[n] bit.
TIMERx_INTSTS[1]) and TIF (TIMERx_INTSTS[0]).
PD_TMRWK (CLK_PMUSTS[2]) or SPD_TMRWK
(WDT_CTL
ISD94100 SERIES TECHNICAL REFERENCE MANUAL
RTC Alarm Interrupt Y N N
Time Tick Interrupt Y N N
Wakeup by RTC
RTC
UART
Sep 9, 2019 Page 59 of 928 Rev1.09
alarm
time
nCTS wake-up Y N N
RX Data wake-up Y N N
Received FIFO
N Y N
N Y N
Y N N
ALMIF (RTC_INTSTS[0]). TICKIF (RTC_INTSTS[1]).
fter software writes 1 to clear
UARTx_WKSTS[0]).
UARTx_WKSTS[1]).
fter software writes 1 to clear RFRTWKF
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ISD94100 Series Technical Reference Manual
Threshold Wake-up
(UARTx_WKSTS[2]).
A (
A (
A
WKAKDONE (I2C_WKSTS[1]). Then WKIF(I2C_WKSTS[0]).
After software writes 1 to clear (
I2C
USBD
RS-485 AAD Mode
Wake-up
Received FIFO
Threshold Time-out
Wake-up
Address match
wake-up
Remote Wake-up Y N N
Y N N
Y N N
Y N N
fter software writes 1 to clear RS485WKF
UARTx_WKSTS[3]).
fter software writes 1 to clear TOUTWKF
UARTx_WKSTS[4]).
fter software writes 1 to clear
software writes 1 to clear
BUSIF
USBD_INTSTS[0]).
Table 6.2.5-5 Re-Entering Power-do wn Mode Condition
ISD94100 SERIES TECHNICAL REFERENCE MANUAL
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ISD94100 Series Technical Reference Manual

6.2.6 Brown-out Detector and Low Voltage Reset Cont roller Configuration

ISD94100 series is equipped with brown-out detector and low voltage reset controller function. Low voltage reset controller is enabled by setting LVREN(SYS_BODCTL[7]) to 1. Brown-out detector is enabled by setting both LVREN(SYS_BODCTL[7]) and BODEN(SYS_BODCTL[0]) to 1. Both brown-ou t detector and l ow voltage res et controller also integrates low po wer mode functi on, the low power mode is enabled by setting BODLPM(SYS_BODCTL[5]). When enable low power mode, brown-out detector and low voltage reset controller will consume less power, but the detection speed will becom e slow (The response time is about 13m s). W hen using bro wn-out detect or and low vol tag e reset controller, the LIRC must be turned on. In addition, the brown-out detector cannot operate independently without enabled low voltage reset controller.
Power Mode LVREN
(SYS_BODCTL[7])
Normal / Idle / PD 0 X X Disabled Disabled
1 0 X Normal Disabled 1 1 0 Normal Normal 1 1 1 Low power Low power
BODEN
(SYS_BODCTL[0])
BODLPM
(SYS_BODCTL[5])
LVR / BOD Operation Mode
LVR BOD
LLPD / SPD0 /
SPD1
DPD X X X Disabled Disabled
0 X X Disabled Disabled 1 0 X Low power Disabled 1 1 0 Normal Normal 1 1 1 Low power Low power
Table 6.2.6-1 Brown-out Detector and Low Voltage Reset Controller Effect Table
Note: X means don’t care, write 1 or 0 to correspond register bit will not affect functionality.
ISD94100 SERIES TECHNICAL REFERENCE MANUAL
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ISD94100 Series Technical Reference Manual

6.2.7 System Memory Map

The ISD94100 series provides 4G-byte addr essing space. The memory addresses assigned to each on-chip controllers are shown in Table 6.2.7-1. The detailed register definition, memory space, and programming will be described in the following sections for each on-chip peripheral. The ISD94100 series only supports little-endian data format.
Address Space
Flash and SRAM Memory Space
0x0000_0000 – 0x0007_FFFF FLASH_BA FLASH Memory Space (512 Kbytes) 0x2000_0000 – 0x2000_7FFF SRAM0_BA SRAM Memory Space (32 Kbytes) 0x2000_8000 – 0x2002_FFFF SRAM1_BA SRA M Memory Space (160 Kbytes) Peripheral Controllers Space (0x4000_0000 – 0x400F_FFFF) 0x4000_0000 – 0x4000_01FF SYS_BA System Control Registers 0x4000_0200 – 0x4000_02FF CLK_BA Clock Control Registers 0x4000_0300 – 0x4000_03FF NMI_BA NMI Control Registers 0x4000_4000 – 0x4000_4FFF GPIO_BA GPIO Control Registers
Token Controllers
0x4000_8000 – 0x4000_8FFF PDMA_BA Peri pheral DMA Control Registers 0x4000_C000 – 0x4000_CFFF FMC_BA Flash Memory Cont rol Registers
ISD94100 SERIES TECHNICAL REFERENCE MANUAL
0x4003_1000 – 0x4003_1FFF CRC_BA CRC Generator Registers APB Controllers Space (0x4000_0000 ~ 0x400F_FFFF) 0x4004_0000 – 0x4004_0FFF WDT_BA Watchdog Timer Control Registers 0x4004_1000 – 0x4004_1FFF RTC_BA Real Time Clock (RTC) Control Register 0x4004_3000 – 0x4004_3FFF EADC_BA Enhanced Analog-Digital-Converter (EADC) Control Registers 0x4004_8000 – 0x4004_8FFF I2S0_BA I2S0 Interface Control Registers 0x4005_0000 – 0x4005_0FFF TMR01_BA Timer0/Timer1 Control Registers 0x4005_1000 – 0x4005_1FFF TMR23_BA Timer2/Timer3 Control Registers 0x4005_8000 – 0x4005_8FFF PWM0_BA PWM0 Control Registers 0x4006_0000 – 0x4006_0FFF SPI0_BA SPI0 Control Registers 0x4006_1000 – 0x4006_1FFF SPI1_BA SPI1 Control Registers 0x4006_2000 – 0x4006_2FFF SPI2_BA SPI2 Control Registers 0x4006_3000 – 0x4006_30FF DMIC_BA DMIC Control Registers 0x4006_3100 – 0x4006_3FFF VAD_BA VAD Control Registers 0x4006_4000 – 0x4006_4FFF DPWM_BA DPWM Control Registers 0x4007_0000 – 0x4007_0FFF UART0_BA UART0 Control Registers 0x4008_0000 – 0x4008_0FFF I2C0_BA I2C0 Control Registers 0x4008_1000 – 0x4008_1FFF I2C1_BA I2C1 Control Registers 0x400C_0000 – 0x400C_0FFF USBD_BA USB Device Control Register
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SRAM bank1
SRAM decoder
AHB interface
controller
SRAM bank
0
SRAM decoder
AHB interface
controller
System Controllers Space (0xE000_E000 ~ 0xE000_EFFF) 0xE000_E010 – 0xE000_E0FF SCS_BA System Timer Control Registers 0xE000_E100 – 0xE000_ECFF SCS_BA External Interrupt Controller Control Registers 0xE000_ED00 – 0xE000_ED8F SCS_BA System Control Registers
Table 6.2.7-1 Address Space Assignments for On-Chip Controllers

6.2.8 SRAM Memory Organization

The ISD94100 series supports up to 192 KB of em bedded SRAM and t he SRAM org anization is separated to two banks : SRAM bank0 and SRAM ba nk1. The SRAM bank0 suppor ts parity error check to make sure chip operating more stable.
Supports up to 192 KB of SRAM  Supports byte / half word / word write  Supports parity error check function for SRAM bank0  Supports oversize response error
Figure 6.2-6 SRAM Block Diagram
ISD94100 SERIES TECHNICAL REFERENCE MANUAL
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ISD94100 Series Technical Reference Manual
512MB
32 KB
SRAM
0x
2000_0000
Reserved
0
x
3
FFF
_
FFFF
0
x
2000_
7FFF
0x2000
_
8000
160
KB
SRAM
0x2003_0000 0
x
2002
_
FFFF
ISD94100 SERIES TECHNICAL REFERENCE MANUAL
Figure 6.2-7 SRAM Mem ory Organ i zat ion
SRAM address from 0x 2000_0000 to 0x2000_7FFF has byte parit y error check function. When CPU is accessing SRAM address from 0x2000_0000 to 0x2000_7FF F the parity error checking mechanism is operating dynamically. If parity error occurrs, the PERRIF (SYS_SRAM_STA TUS[0]) will be asserted to 1 and t he SYS_SRAM_ERR ADDR register will record the address with parity error. Chip will enter interrupt when SRAM parity error occurs if PERRIEN (SYS_SRAM_INTCTL[0]) is set to 1. W hen SRAM parit y error occurs, chip wil l stop detecting SR AM parity errors until user writes 1 to clear the PERRIF(SYS_SRAM_STATUS[0]) bit.

6.2.9 HIRC Auto Trim

This chip supports auto-trim func tion: the HIRC trim , according to the acc urate LXT (32.768 k Hz crystal oscillator) or USB SOF (Start -Of-Frame), automatically gets accurate HIRC output frequency ,
0.25 % deviation within all temperature ranges. For instance, the system needs an ac curate 49.152 MHz or 48 MHz clock. In such case, if neith er using PLL as the system clock s ource nor s older ing 3 2.76 8 kH z cr ystal in system , user has t o set REFCKSEL (SYS_IRCTCTL[10] reference clock selection) to “1”, set FREQSEL (SYS_IRCTCTL[1:0] trim frequency selection) to “10” or “11”, and the auto-trim function will be enabled. Interrupt status bit FREQLOCK (SYS_IRCTISTS[8] HIRC frequency lock status) “1” indicates the HIRC output frequency is accurate within 0.25% deviation.
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R/W
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R/W
R/W
R/W
R/W
R/W

6.2.10 Register Map

R: read only, W: write only, R/W: both read and write
Register
SYS Base Address: SYS_BA = 0x4000_0000
SYS_PDID
SYS_RSTSTS
SYS_IPRST0
SYS_IPRST1
SYS_IPRST2
SYS_BODCTL
SYS_PORCTL
SYS_USBPHY
SYS_GPA_MFPL
SYS_GPA_MFPH
ISD94100 SERIES TECHNICAL REFERENCE MANUAL
SYS_GPB_MFPL
SYS_GPB_MFPH
Offset
SYS_BA+0x00
SYS_BA+0x04
SYS_BA+0x08
SYS_BA+0x0C
SYS_BA+0x10
SYS_BA+0x18
SYS_BA+0x24
SYS_BA+0x2C
SYS_BA+0x30
SYS_BA+0x34
SYS_BA+0x38
SYS_BA+0x3C
Description Reset Value
Part Device Identification Number Register 0x1DXX_05XX
System Reset Status Register 0x0000_0043
Peripheral Reset Control Register 0 0x0000_0000
Peripheral Reset Control Register 1 0x0000_0000
Peripheral Reset Control Register 2 0x0000_0000
Brown-Out Detector Control Register 0x000X_038X
Power-On-Reset Cont rol l er Register 0x0000_0000
USB PHY Control Register 0x0000_0000
GPI OA Low Byte Multiple Function Control Register 0x0000_0000
GPI OA High Byte Multiple Function Control Register 0x0000_0000
GPI OB Low Byte Multiple Function Control Register 0x0110_0000
GPI OB High Byte Multiple Function Control Regi st er 0x0000_0000
[1]
SYS_GPC_MFPL
SYS_GPC_MFPH
SYS_GPD_MFPL
SYS_GPD_MFPH
SYS_SRAM_INTCTL
SYS_SRAM_STATUS
SYS_SRAM_ERRADDR
SYS_IRCTCTL
SYS_IRCTIEN
SYS_IRCTISTS
SYS_REGLCTL
SYS_RCADJ
Note:
1. Any register not listed here is reserved and must not be written. The result of a read operation on these bits is undefined.
2. The reserved register fields that listed in register description must be written to their reset value. Writing reserved fields with other than reset values may produce undefined results.
SYS_BA+0x40
SYS_BA+0x44
SYS_BA+0x48
SYS_BA+0x4C
SYS_BA+0xC0
SYS_BA+0xC4
SYS_BA+0xC8
SYS_BA+0xF0
SYS_BA+0xF4
SYS_BA+0xF8
SYS_BA+0x100
SYS_BA+0x110
GPI OC Low Byte Multiple Function Control Regi st er 0x0000_0000
GPIOC High Byte Multiple Function Control Register 0x0000_0000
GPI OD Low Byte Multiple Function Control Regi st er 0x0000_0000
GPI OD High Byte Multipl e Function Control Regi st er 0x0000_0011
System SRAM Interrupt Enable Control Register 0x0000_0000
System SRAM Parity Error Status Register 0x0000_0000
System SRAM Parity Check Error Address Register 0x0000_0000
HIRC Trim Control Register 0x0000_0000
HIRC Trim Interrupt Enable Register 0x0000_0000
HIRC Trim Interrupt Status Register 0x0000_0000
Regist er Lock Control Register 0x0000_0000
HIRC Trim Value Register 0x0000_0XXX
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ISD94100 Series Technical Reference Manual
R/W
R
This register reflects device part number code. Software can read this register to i dentify

6.2.11 Register Description

Part Device Identification Number Register (SYS_PDID)
Register
SYS_PDID
[1] Every part number has a unique default reset value.
31 30 29 28 27 26 25 24
23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8
7 6 5 4 3 2 1 0
Offset
SYS_BA+0x00
Description Reset Value
Part Device Identificati on Number Register 0x1DXX_05XX
PDID
PDID
PDID
PDID
Bits
[31:0]
Description
Part Device Identification Number (Read Only)
PDID
which device is used.
[1]
ISD94100 SERIES TECHNICAL REFERENCE MANUAL
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ISD94100 Series Technical Reference Manual
R/W
R/W
writing to this field always write with
The CPU reset flag is set by hardware if software writes CPURST (SYS_IPRST0[1]) 1 to
M4 Core to indicate the
reset signal to reset the system by writing 1 to the bit
SYSRESETREQ(AIRCR[2], Application Interrupt and Reset Control Register, address =
System Reset Status Register (SYS_RSTSTS)
This register provides specific information for software to identify this chip’s reset source from last operation.
Register
Offset
Description Reset Value
SYS_RSTSTS
SYS_BA+0x04
System Reset Status Register 0x0000_0043
31 30 29 28 27 26 25 24
Reserved
23 22 21 20 19 18 17 16
Reserved
15 14 13 12 11 10 9 8
Reserved CPULKRF
7 6 5 4 3 2 1 0
CPURF PMURF SYSRF BODRF LVRF WDTRF PINRF PORF
Bits
ISD94100 SERIES TECHNICAL REFERENCE MANUAL
[31:9]
[8]
Description
Reserved
CPULKRF
Reserved. Any values read should be ignored. When reset value.
CPU Lockup Reset Flag
0 = No reset from CPU lockup occurred. 1 = The Cortex-M4 lockup occurred and chip is reset.
Note: Write 1 to clear this bit to 0. Note: when ICE is connected, CPU lockup event sets this flag to 1 but will not reset chip.
CPU Reset Flag
[7]
[6]
[5]
Sep 9, 2019 Page 68 of 928 Rev1.09
CPURF
PMURF
SYSRF
reset Cortex®-M4 Core and Flash Memory Controller (FMC). 0 = No reset from CPU.
®
1 = The Cortex
Note: Write 1 t o clear this bit to 0. PMU Reset Flag
0 = No reset from POR, PINR, WDTR, LVR, BODR, SYSR and CPULKR. 1 = When POR, PINR, WDTR, LVR, BODR, SYSR and CPULKR occurred.
Note: Write 1 to clear this bit to 0. System Reset Flag
The system reset flag is set by the “Reset Signal” from the Cortex®­previous reset source.
0 = No reset from Cortex®-M4. 1 = The Cortex®-M4 had issued the
0xE000ED0C) in system control registers of Cortex®-M4 core. Note: Write 1 to clear this bit to 0.
-M4 Core and FMC are reset by software setting CPURST to 1.
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ISD94100 Series Technical Reference Manual
Out Detector to indicate the
from the Low Voltage Reset Controller to
from the Watchdog Timer or Wi ndow
= The watchdog timer or window watchdog timer issued the reset signal to reset the
Watchdog Timer register RSTF( WDT_CTL[2]) bit is set if the system has been reset
out reset. Window Watchdog Timer register WWDTRF(WWDT_STATUS[1])
from the nRESET Pin to indicate the
on Reset (POR) Controller
Bits
[4]
[3]
[2]
[1]
Description
BODRF
LVRF
WDTRF
PINRF
BOD Reset Flag
The BOD reset flag is set by the “Reset Signal” from the Brown­previous reset source.
0 = No reset from BOD. 1 = The BOD had issued the reset signal to reset the system.
Note: Write 1 to clear this bit to 0.
LVR Reset Flag
The LVR reset flag is set by the “Reset Signal” indicate the previous reset source.
0 = No reset from LVR. 1 = LVR controller issued the reset signal to reset the system.
Note: Write 1 to clear this bit to 0.
WDT Reset Flag
The WDT reset flag is set by the “Reset Signal” Watchdog Timer to indicate the previous reset source.
0 = No reset from watchdog timer or window watchdog timer. 1
system.
Note1: Write 1 to clear this bit to 0. Note2:
by W DT t ime ­bit is set if the system has been reset by WWDT time-out reset.
NRESET Pin Reset Flag
The nRESET pin reset flag is set by the “Reset Signal” previous reset source.
0 = No reset from nRESET pin. 1 = Pin nRESET issued the reset signal to reset the system. Note: Write 1 to clear this bit to 0.
ISD94100 SERIES TECHNICAL REFERENCE MANUAL
POR Reset Flag
The POR reset flag is set by the “Reset Signal” from the Power-
[0]
Sep 9, 2019 Page 69 of 928 Rev1.09
PORF
or bit CHIPRST (SYS_IPRST0[0]) to indicate the previous reset source. 0 = No reset from POR or CHIPRST. 1 = Power-on Reset (POR) or CHIPRST issued the reset signal to reset the system. Note: Write 1 to clear this bit to 0.
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ISD94100 Series Technical Reference Manual
R/W
R/W
always wri te wit h
Set this bit to 1 will generate a reset signal to the CRC calculation controller. User needs to
. Any values read should be ignored. When writing to this fiel d always write with
About the difference between CHIPRST and SYSRESETREQ(AIRCR[2]), please refer to
Peripheral Reset Control Register 0 (SYS_IPRST0)
Register
SYS_IPRST0
Offset
SYS_BA+0x08
Description Reset Value
P eri pheral Res et Cont rol Register 0 0x0000_0000
31 30 29 28 27 26 25 24
Reserved
23 22 21 20 19 18 17 16
Reserved
15 14 13 12 11 10 9 8
Reserved
7 6 5 4 3 2 1 0
CRCRST
Reserved
PDMARST CPURST CHIPRST
Bits
[31: 8]
ISD94100 SERIES TECHNICAL REFERENCE MANUAL
Description
Reserved
Reserved. Any values read should be ignored. When writing to this fi eld reset value.
CRC Calculation Controller Reset (Write Protected)
[7]
[6:3]
[2]
[1]
[0]
CRCRST
Reserved
PDMARST
CPURST
CHIPRST
set this bit to 0 to release from the reset state. 0 = CRC calculation controller normal operation. 1 = CRC calculation controller reset. Note: This bit is write protected. Refer to the SYS_REGLCTL register.
Reserved reset value.
PDMA Controller Reset (Write Protected)
Setting this bit to 1 will generate a reset signal to the PDMA. User needs to set this bit to 0 to release from reset state.
0 = PDMA controller normal operation. 1 = PDMA controller reset.
Note: This bit is write protected. Refer to the SYS_REGLCTL register. Processor Core One-shot Reset (Write Protected)
Setting this bit will only reset the processor core and Flash Memory Controller(FMC); this bit will automatically return to 0 after the 2 clock cycles.
0 = Processor core normal operation. 1 = Processor core one-shot r eset.
Note: This bit is write protected. Refer to the SYS_REGLCTL register. Chip One-shot Reset (Write Protected)
Setting this bit will reset the whole chip, including Processor core and all peripherals; this bit will automatically return to 0 after the 2 clock cycles.
The CHIPRST is same as the POR reset, all the chip controllers are reset and the chip settings from flash configuration are also reloaded.
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section 6.2.2
0 = Chip normal operation. 1 = Chip one-shot reset. Note: This bit is write protected. Refer to the SYS_REGLCTL register.
ISD94100 SERIES TECHNICAL REFERENCE MANUAL
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ISD94100 Series Technical Reference Manual
R/W
R/W
When writing to this field always write with
values read should be ignored. When writing to this field always write with
Peripheral Reset Control Register 1 (SYS_IPRST1)
Setting these bits 1 will generate as ynchronous reset s ignals to the corr esponding module c ontroller. Users need to set these bits to 0 to release corresponding module controller from reset state.
Register
Offset
Description Reset Value
SYS_IPRST1
SYS_BA+0x0C
P eri pheral Res et Cont rol Register 1 0x0000_0000
31 30 29 28 27 26 25 24
Reserved HIRCCKF I2S0RST EADCRST
23 22 21 20 19 18 17 16
Reserved UART0RST
15 14 13 12 11 10 9 8
DMICRST SPI2RST SPI1RST
7 6 5 4 3 2 1 0
Reserved TMR3RST TMR2RST TMR1RST TMR0RST GPIORST Reserved
SPI0RST
USBDRST Reserved
Reserved
I2C1RST I2C0RST
Bits Description
ISD94100 SERIES TECHNICAL REFERENCE MANUAL
[31]
[30]
[29]
Reserved
HIRCCKF
I2S0RST
Reserved. Any values read should be ignored. reset value.
HIRC Clock Filter Enable Bit
0 = HIRC clock filter Enabled. 1 = HIRC clock filter Disabled.
2
I
S0 Controller Reset
2
S0 controller normal operation.
0 = I
2
S0 controller reset.
1 = I
EADC Controller Reset
[28]
[27]
[26:17]
[16]
[15]
[14]
EADCRST
USBDRST
Reserved
UART0RST
DMICRST
SPI2RST SPI2 Contr oll er Reset
0 = EADC controller normal operation. 1 = EADC controller reset.
USBD Controller Reset
0 = USBD controller normal operation. 1 = USBD controller reset.
Reserved. Any reset value.
UART0 Controller Reset
0 = UART0 controller normal operation. 1 = UART0 controller reset.
DMIC Controller Reset 0 = DMIC controller normal operation. 1 = DMIC controller reset.
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Page 73
0 = SPI2 controller normal operation.
. Any values read should be ignored. When writing to this fiel d always write with
with
. Any values read should be ignored. When writing to this fiel d always write with
[13]
[12]
ISD94100 Series Technical Reference Manual
1 = SPI2 controller reset.
SPI1 Controller Reset
SPI1RST
SPI0RST
0 = SPI1 controller normal operation. 1 = SPI1 controller reset.
SPI0 Controller Reset
0 = SPI0 controller normal operation. 1 = SPI0 controller reset.
[11:10]
[9]
[8]
[7:6]
[5]
[4]
[3]
[2]
Reserved
I2C1RST
I2C0RST
Reserved
TMR3RST
TMR2RST
TMR1RST
TMR0RST
Reserved reset value.
I2C1 Controller Reset
0 = I2C1 controller normal operation. 1 = I2C1 controller reset.
I2C0 Controller Reset
0 = I2C0 controller normal operation. 1 = I2C0 controller reset.
Reserved. Any values read should be ignored. When writing to this fi eld always write reset value.
Timer3 Controller Reset
0 = Timer3 controller normal operation. 1 = Timer3 controller reset.
Timer2 Controller Reset
0 = Timer2 controller normal operation. 1 = Timer2 controller reset.
Timer1 Controller Reset
0 = Timer1 controller normal operation. 1 = Timer1 controller reset.
Timer0 Controller Reset
0 = Timer0 controller normal operation. 1 = Timer0 controller reset.
ISD94100 SERIES TECHNICAL REFERENCE MANUAL
[1]
[0]
Sep 9, 2019 Page 73 of 928 Rev1.09
GPIORST
Reserved
GPIO Controller Reset
0 = GPIO controller normal operation. 1 = GPIO controller reset.
Reserved reset value.
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ISD94100 Series Technical Reference Manual
R/W
R/W
values read should be ignored. When writing to this field always write with
writing to this field always write with
always wri te wit h
Peripheral Reset Control Register 2 (SYS_IPRST2)
Setting these bits to 1 will generate asynchronous reset signals to the corresponding module controller. Users need to set these bits to 0 to release corresponding module controller from reset state.
Register
Offset
Description Reset Value
SYS_IPRST2
SYS_BA+0x10
P eri pheral Res et Cont rol Register 2 0x0000_0000
31 30 29 28 27 26 25 24
Reserved
23 22 21 20 19 18 17 16
Reserved PWM0RST
15 14 13 12 11 10 9 8
Reserved
7 6 5 4 3 2 1 0
Reserved DPWMRST Reserved
Bits Description
ISD94100 SERIES TECHNICAL REFERENCE MANUAL
[31:17]
[16]
Reserved
PWM0RST
Reserved. Any reset value.
PWM0 Controller Reset
0 = PWM0 controller normal operation. 1 = PWM0 controller reset.
[15:7]
[6]
[5:0]
Reserved
DPWMRST
Reserved
Reserved. Any values read should be ignored. When reset value.
DPWM Controller Reset
0 = Audio DPWM controller normal operation. 1 = Audio DPWM controller reset.
Reserved. Any values read should be ignored. When writing to this fi eld reset value.
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ISD94100 Series Technical Reference Manual
R/W
R/W
. Any values read should be ignored. When writing to this field always write with
set by flash controller user configuration register CBOV (CONFIG0
. Any values read should be ignored. When writing to this field always write with
Brown-out Detector Control Register (SYS_BODCTL)
Part of the SYS_BODCTL control registers values are initialized by flash configuration and writeable bits are write-protected.
Register Offset
Description Reset Value
SYS_BODCTL
SYS_BA+0x18
Brown-Out Det ec tor Control Register 0x000X_038X
31 30 29 28 27 26 25 24
Reserved
23 22 21 20 19 18 17 16
Reserved BODVL
15 14 13 12 11 10 9 8
Reserved BODDGSEL
7 6 5 4 3 2 1 0
LVREN BODOUT BODLPM BODIF BODRSTEN Reserved BODEN
Bits Description
[31:19]
[18:16]
Reserved
BODVL
Reserved reset value.
Brown-out Detector Threshold Voltage Selection (Write Protected)
The default value is [23:21]).
000 = Brown-Out Detector threshold voltage is 1.6V. 001 = Brown-Out Detector threshold voltage is 1.8V. 010 = Brown-Out Detector threshold voltage is 2.0V. 011 = Brown-Out Detector threshold voltage is 2.2V. 100 = Brown-Out Detector threshold voltage is 2.4V. 101 = Brown-Out Detector threshold voltage is 2.6V. 110 = Brown-Out Detector threshold voltage is 2.8V. 111 = Brown-Out Detector threshold voltage is 3.0V. Note: These bits are write protected. Refer to the SYS_REGLCTL register.
ISD94100 SERIES TECHNICAL REFERENCE MANUAL
[15:11]
[10:8]
Reserved
BODDGSEL
Reserved reset value.
Brown-out Detector Output De-glitch Time Select (Write Protected)
000 = Without de-glitch function. 001 = 3 system clock (HCLK). 010 = 7 system clock (HCLK). 011 = 15 system clock (HCLK). 100 = 31 system clock (HCLK). 101 = 63 system clock (HCLK). 110 = 127 system clock (HCLK). 111 = 255 sys t em clock (HCLK). Note: These bits are write protected. Refer to the SYS_REGLCTL register.
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ISD94100 Series Technical Reference Manual
The LVR function resets the chip when the input power voltage is lower than LVR circuit
The low power mode can reduce the current to about 1/10 but slow the BOD
down through or up through
either direction,
controller user configuration register
out Detector function is enabled (BODEN high) and BOD reset function is
BODRSTEN high), BOD will assert a signal to reset chip when the detected voltage
While the BOD function is enabled (BODEN high) and BOD interrupt function is
interrupt if BODOUT is high. BOD interrupt
will latch until BODEN is set to 0. BOD interrupt can be blocked by disabling the NVIC BOD
. Any values read should be ignored. When writing to this field always write with
Bits Description
Low Voltage Reset Enable Bit (Write Protected)
[7]
[6]
[5]
ISD94100 SERIES TECHNICAL REFERENCE MANUAL
[4]
LVREN
BODOUT
BODLPM
BODIF
setting. LVR function is enabled by default. 0 = Low Voltage Reset function Disabled. 1 = Low Voltage Reset function Enabled.
Note: This bit is write protected. Refer to the SYS_REGLCTL register. Brown-out Detector Output Status
0 = Brown-out Detector output status is 0. The detected voltage is higher than BODVL setting or BODEN is 0. 1 = Brown-out Detector output status is 1. The detected voltage is lower than BODVL setting. If the BODEN is 0, BOD function is disabled and this bit will be 0.
Brown-out Detector Low Power Mode (Write Protected)
0 = BOD operate in normal mode (default). 1 = BOD Low Power mode Enabled.
Note 1:
response.
Note 2: This bit is write protected. Refer to the SYS_REGLCTL register. Brown-out Detector Interrupt Flag
0 = Brown-out Detector has not detected a BOD event on VDD the voltage of BODVL setting.
1 = When Brown-out Detector detects that VDD cro sses BOD L VL settin g from this bit is set to 1 and the brown-out interrupt is requested if brown-out interrupt is enabled.
Note: Write 1 to clear this bit to 0. Brown-out Reset Enable Bit (Write Protected)
The default value is set by flash CBORST(CONFIG0[20]) bit .
0 = Brown-out “INTERRUPT” function Enabled. 1 = Brown-out “RESET” function Enabled.
Note 1:
[3]
[2:1]
Sep 9, 2019 Page 76 of 928 Rev1.09
BODRSTEN
Reserved
While the Brown­enabled ( is lower than the threshold (BODOUT high).
enabled (BODRSTEN low), BOD will assert an interrupt or disabling BOD function (set BODEN low).
Note 2: The reset value of SYS_BODCTL[3] is determined by user flash configuration. Note 3: This bit is write protected. Refer to the SYS_REGLCTL register.
Reserved reset value.
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ISD94100 Series Technical Reference Manual
The default value is set by flash controller user configuration register CBODEN (CONFIG0
out detector can only work when both BODEN(SYS_BODCTL[0]) and
are set to 1,
Bits Description
[0]
BODEN
Brown-out Detector Enable Bit (Write Protected)
[19]). 0 = Brown-out Detector function Disabled. 1 = Brown-out Detector function Enabled.
Note 1: The reset value of SYS_BODCTL[0] is determined by user flash configuration. Note 2: Brown-
LVREN(SYS_BODCTL[7]) are set to 1. Note 3: When both BODEN(SYS_BODCTL[0]) and LVREN(SYS_BODCTL[7])
NVIC BOD interrupt must be enabled before entering power down mode. Note 4: This bit is write protected. Refer to the SYS_REGLCTL register.
ISD94100 SERIES TECHNICAL REFERENCE MANUAL
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R/W
R/W
When writing to this field always write with
When power is applied to device, the POR circuit generates a reset signal to re set the entire
the POR to become active again. User can
disable internal POR circuit to avoid unpredictable noise to cause chip reset by writing
The POR function will be active again when this field is set to another value or chip is reset
chip reset
Power-on Reset Controller Register (SYS_PORCTL)
Register
SYS_PORCTL
Offset
SYS_BA+0x24
Description Reset Value
Power-On-Reset Controller Register 0x0000_0000
31 30 29 28 27 26 25 24
Reserved
23 22 21 20 19 18 17 16
Reserved
15 14 13 12 11 10 9 8
POROFF
7 6 5 4 3 2 1 0
POROFF
Bits
[31:16]
ISD94100 SERIES TECHNICAL REFERENCE MANUAL
Description
Reserved
Reserved. Any values read should be ignored. reset value.
Power-on Reset Enable Bit (Write Protected)
chip function. Noise on the power may cause
[15:0]
POROFF
0x5AA5 to this field.
by other reset source, including: nRESET , Watchdog, LVR reset, BOD reset, ICE reset command and the software-
function. Note: This bit is write protected. Refer to the SYS_REGLCTL register.
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R/W
R/W
. Any values read should be ignored. When writing to this field always write with
. Any values read should be ignored. When writing to this field always write with
USB PHY Control Register (SYS_USBPHY)
Register
SYS_USBPHY
Offset
SYS_BA+0x2C
Description Reset Value
US B PHY Control Register 0x0000_0000
31
23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8
7 6 5 4 3 2 1 0
30 29 28 27 26 25 24
Reserved
Reserved
Reserved
Reserved
Bits
[31:9]
[8]
Description
Reserved
USB_PHY_EN
Reserved reset value.
USB PHY Enable (Write Protect)
This bit is used to enable/disable USB PHY function. 0 = USB PHY function Disabled (default). 1 = USB PHY function Enabled.
USB_PHY_EN
ISD94100 SERIES TECHNICAL REFERENCE MANUAL
[7:0]
Reserved
Reserved reset value.
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R/W
GPIOA Low Byte Multiple Function Control Register (SYS_GPA_MFPL)
Register Offset
SYS_GPA_MFPL
SYS_BA+0x30
Description Reset Value
GP IOA Low Byte Multiple Function Control Register 0x0000_0000
31 30 29 28 27 26 25 24
PA7MFP PA6MFP
23 22 21 20 19 18 17 16
PA5MFP PA4MFP
15 14 13 12 11 10 9 8
PA3MFP PA2MFP
7 6 5 4 3 2 1 0
PA1MFP PA0MFP
Bits Description
[31:28] [27:24]
ISD94100 SERIES TECHNICAL REFERENCE MANUAL
[23:20]
PA7MFP PA.7 Multi-function Pin Se le ction PA6MFP PA.6 Multi-function Pin Se le ction PA5MFP PA.5 Multi-function Pin Se le ction
[19:16] [15:12] [11:8] [7:4] [3:0]
PA4MFP PA.4 Multi-function Pin Se le ction PA3MFP PA.3 Multi-function Pin Selection PA2MFP PA.2 Multi-function Pin Se le ction PA1MFP PA.1 Multi-function Pin Se le ction PA0MFP PA.0 Multi-function Pin Se le ction
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R/W
R/W
GPIOA High Byte Multiple Function Control Re g ister (SYS_GPA_MFPH)
Register Offset
SYS_GPA_MFPH
SYS_BA+0x34
Description Reset Value
GP IOA High Byte Multiple Function Control Register 0x0000_0000
31 30 29 28 27 26 25 24
PA15MFP PA14MFP
23 22 21 20 19 18 17 16
PA13MFP PA12MFP
15 14 13 12 11 10 9 8
PA11MFP PA10MFP
7 6 5 4 3 2 1 0
PA9MFP PA8MFP
Bits Description
[31:28] [27:24] [23:20]
PA15MFP PA.15 Multi-function Pin Selection PA14MFP PA.14 Multi-function Pin Selection PA13MFP PA.13 Multi-function Pin Selection
ISD94100 SERIES TECHNICAL REFERENCE MANUAL
[19:16] [15:12] [11:8] [7:4] [3:0]
PA12MFP PA.12 Multi-function Pin Selection PA11MFP PA.11 Multi-function Pin Selection PA10MFP PA.10 Multi-function Pin Selection PA9MFP PA.9 Multi-function Pin Se le ction PA8MFP PA.8 Multi-function Pin Se le ction
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R/W
GPIOB Low Byte Multiple Function Control Register (SYS_GPB_MFPL)
Register Offset
SYS_GPB_MFPL
SYS_BA+0x38
Description Reset Value
GP IOB Low Byte Multiple Function Control Register 0x0110_0000
31 30 29 28 27 26 25 24
PB7MFP PB6MFP
23 22 21 20 19 18 17 16
PB5MFP PB4MFP
15 14 13 12 11 10 9 8
PB3MFP PB2MFP
7 6 5 4 3 2 1 0
PB1MFP PB0MFP
Bits Description
[31:28] [27:24]
ISD94100 SERIES TECHNICAL REFERENCE MANUAL
[23:20]
PB7MFP PB.7 Multi-funct ion Pin Selection PB6MFP PB.6 Multi-funct ion Pin Selection PB5MFP PB.5 Multi-funct ion Pin Selection
[19:16] [15:12] [11:8] [7:4] [3:0]
PB4MFP PB.4 Multi-function Pin Selection PB3MFP PB.3 Multi-funct ion Pin Selection PB2MFP PB.2 Multi-funct ion Pin Selection PB1MFP PB.1 Multi-funct ion Pin Selection PB0MFP PB.0 Multi-funct ion Pin Selection
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. Any values read should be ignored. When writing to this field always write with
GPIOB High Byte Multiple Function Control Register (SYS_GPB_MFPH)
Register Offset R/W Description Reset Value
SYS_GPB_MFPH
SYS_BA+0x3C R/W G P IOB High Byte Multiple Function Control Register 0x0000_0000
31 30 29 28 27 26 25 24
PB15MFP PB14MFP
23 22 21 20 19 18 17 16
PB13MFP Reserved
15 14 13 12 11 10 9 8
Reserved
7 6 5 4 3 2 1 0
PB9MFP PB8MFP
Bits Description
[31:28] [27:24] [23:20]
[19:8]
PB15MFP PB.15 Multi-function Pin Selection PB14MFP PB.14 Multi-function Pin Selection PB13MFP PB.13 Multi-function Pin Selection
Reserved
Reserved reset value.
ISD94100 SERIES TECHNICAL REFERENCE MANUAL
[7:4] [3:0]
PB9MFP PB.9 Multi-funct ion Pin Selection PB8MFP PB.8 Multi-funct ion Pin Selection
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R/W
R/W
GPIOC Low Byte Multiple Function Control Register (SYS_GPC_MFPL)
Register Offset
SYS_GPC_MFPL
SYS_BA+0x40
Description Reset Value
GP IOC Low Byte Multiple Function Control Register 0x0000_0000
31 30 29 28 27 26 25 24
PC7MFP PC6MFP
23 22 21 20 19 18 17 16
PC5MFP PC4MFP
15 14 13 12 11 10 9 8
PC3MFP PC2MFP
7 6 5 4 3 2 1 0
PC1MFP PC0MFP
Bits Description
[31:28] [27:24]
ISD94100 SERIES TECHNICAL REFERENCE MANUAL
[23:20]
PC7MFP PC.7 Multi-funct ion Pin Selection PC6MFP PC.6 Multi-funct ion Pin Selection PC5MFP PC.5 Multi-funct ion Pin Selection
[19:16] [15:12] [11:8] [7:4] [3:0]
PC4MFP PC.4 Multi-function Pin Selection PC3MFP PC.3 Multi-funct ion Pin Selection PC2MFP PC.2 Multi-funct ion Pin Selection PC1MFP PC.1 Multi-funct ion Pin Selection PC0MFP PC.0 Multi-funct ion Pin Selection
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R/W
R/W
GPIOC High Byte Multiple Function Control Register (SYS_GPC_MFPH)
Register Offset
SYS_GPC_MFPH
SYS_BA+0x44
Description Reset Value
GP IOC High Byte Multiple Function Control Register 0x0000_0000
31 30 29 28 27 26 25 24
PC15MFP PC14MFP
23 22 21 20 19 18 17 16
PC13MFP PC12MFP
15 14 13 12 11 10 9 8
PC11MFP PC10MFP
7 6 5 4 3 2 1 0
PC9MFP PC8MFP
Bits Description
[31:28] [27:24] [23:20]
PC15MFP PC.15 Multi-function Pin Selection PC14MFP PC.14 Multi-function Pin Selection PC13MFP PC.13 Multi-function Pin Selection
ISD94100 SERIES TECHNICAL REFERENCE MANUAL
[19:16] [15:12] [11:8] [7:4] [3:0]
PC12MFP PC.12 Multi-function Pin Selection PC11MFP PC.11 Multi-function Pin Selection PC10MFP PC.10 Multi-function Pin Selection PC9MFP PC.9 Multi-funct ion Pin Selection PC8MFP PC.8 Multi-funct ion Pin Selection
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R/W
GPIOD Low Byte Multiple Function Control Register (SYS_GPD_MFPL)
Register Offset
SYS_GPD_MFPL
SYS_BA+0x48
Description Reset Value
GP IOD Low Byte Multiple Function Control Register 0x0000_0000
31 30 29 28 27 26 25 24
PD7MFP PD6MFP
23 22 21 20 19 18 17 16
PD5MFP PD4MFP
15 14 13 12 11 10 9 8
PD3MFP PD2MFP
7 6 5 4 3 2 1 0
PD1MFP PD0MFP
Bits Description
[31:28] [27:24]
ISD94100 SERIES TECHNICAL REFERENCE MANUAL
[23:20]
PD7MFP PD.7 Multi-funct ion Pin Selection PD6MFP PD.6 Multi-funct ion Pin Selection PD5MFP PD.5 Multi-funct ion Pin Selection
[19:16] [15:12] [11:8] [7:4] [3:0]
PD4MFP PD.4 Multi-funct ion Pin Selection PD3MFP PD.3 Multi-funct ion Pin Selection PD2MFP PD.2 Multi-funct ion Pin Selection PD1MFP PD.1 Multi-funct ion Pin Selection PD0MFP PD.0 Multi-funct ion Pin Selection
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R/W
R/W
GPIOD High Byte Multiple Function Control Register (SYS_GPD_MFPH)
Register Offset
SYS_GPD_MFPH
SYS_BA+0x4C
Description Reset Value
GP IOD High Byte Multiple Function Control Register 0x0000_0011
31 30 29 28 27 26 25 24
PD15MFP PD14MFP
23 22 21 20 19 18 17 16
PD13MFP PD12MFP
15 14 13 12 11 10 9 8
PD11MFP PD10MFP
7 6 5 4 3 2 1 0
PD9MFP PD8MFP
Bits Description
[31:28] [27:24] [23:20]
PD15MFP PD.15 Multi-function Pin Selection PD14MFP PD.14 Multi-function Pin Selection PD13MFP PD.13 Multi-function Pin Selection
ISD94100 SERIES TECHNICAL REFERENCE MANUAL
[19:16] [15:12] [11:8] [7:4] [3:0]
PD12MFP PD.12 Multi-function Pin Selection PD11MFP PD.11 Multi-function Pin Selection PD10MFP PD.10 Multi-function Pin Selection PD9MFP PD.9 Multi-funct ion Pin Selection PD8MFP PD.8 Multi-function Pin Selection
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R/W
R/W
. Any values read should be ignored. When writing to this fiel d always write with
System SRAM Parity Error Interrupt Ena b le Control Register (SYS_SRAM_INTCTL)
Register
SYS_SRAM_INTCTL
Offset
SYS_BA+0xC0
Description Reset Value
System SRAM Interrupt Enable Control Register 0x0000_0000
31 30 29 28 27 26 25 24
Reserved
23 22 21 20 19 18 17 16
Reserved
15 14 13 12 11 10 9 8
Reserved
7 6 5 4 3 2 1 0
Reserved PERRIEN
Bits
[31:1]
ISD94100 SERIES TECHNICAL REFERENCE MANUAL
[0]
Description
Reserved
PERRIEN
Reserved reset value.
SRAM Parity Check Error Interrupt Enable Bit
0 = SRAM parity check error interrupt Disabled. 1 = SRAM parity check error interrupt Enabled.
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R/W
R/W
. Any values read should be ignored. When writing to this fiel d always write with
System SRAM Parity Check Status Register (SYS_SRAM_STATUS)
Register
SYS_SRAM_STATUS
Offset
SYS_BA+0xC4
Description Reset Value
System SRAM Parity Error Status Register 0x0000_0000
31 30 29 28 27 26 25 24
Reserved
23 22 21 20 19 18 17 16
Reserved
15 14 13 12 11 10 9 8
Reserved
7 6 5 4 3 2 1 0
Reserved PERRIF
Bits
[31:1]
[0]
Description
Reserved
PERRIF
Reserved reset value.
SRAM Parity Check Error Flag
This bit indicates the System SRAM parity error occurred. Write 1 to clear this bit to 0. 0 = No System SRAM parity error. 1 = System SRAM parity error occur.
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R
System SRAM Parity Error Address
This register shows system SRAM parity error
System SRAM Parity Error Address Register (SYS_SRAM_ERRADDR)
Register
SYS_SRAM_ERRADDR
Offset
SYS_BA+0xC8
Description Reset Value
System SRAM Parity Check Error Address Register 0x0000_0000
31 30 29 28 27 26 25 24
ERRADDR
23 22 21 20 19 18 17 16
ERRADDR
15 14 13 12 11 10 9 8
ERRADDR
7 6 5 4 3 2 1 0
ERRADDR
Bits
[31:0]
ISD94100 SERIES TECHNICAL REFERENCE MANUAL
Description
ERRADDR
byte address.
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ISD94100 Series Technical Reference Manual
R/W
R/W
. Any values read should be ignored. When writing to this fiel d always write with
many times the auto trim circuit will try to update t he HIRC trim
uency of HIRC still
Note: For example, if LOOPSEL is set as 00, auto trim circuit will calculate trim value based
HIRC Trim Control Register (SYS_IRCTCTL)
Register
SYS_IRCTCTL
Offset
SYS_BA+0xF0
Description Reset Value
HI RC Trim Cont rol Register 0x0000_0000
31 30 29 28 27 26 25 24
Reserved
23 22 21 20 19 18 17 16
Reserved
15 14 13 12 11 10 9 8
Reserved REFCKSEL Reserved CESTOPEN
7 6 5 4 3 2 1 0
RETRYCNT LOOPSEL Reserved FREQSEL
Bits
[31:11]
[10]
Description
Reserved
REFCKSEL
Reserved reset value.
Reference Clock Selection
0 = HIRC trim reference clock is from LXT (32.768 kHz). 1 = HIRC trim reference clock is from USB SOF (Start-Of-Frame) packet.
ISD94100 SERIES TECHNICAL REFERENCE MANUAL
[9]
[8]
[7:6]
[5:4]
Reserved
CESTOPEN
RETRYCNT
LOOPSEL
Reserved. Any values read should be ignored. When writing to this fi eld always write with reset value.
Clock Error Stop Enable Bit
0 = The trim operation is keep going if clock is inaccuracy. 1 = The trim operation is stopped if clock is inaccuracy.
Trim Value Update Limitation Count
This field defines that how value before the frequency of HIRC locked.
Once the HIRC locked, the internal trim value update counter will be reset. If the trim value update counter reached this limitation value and f req
doesn’t lock, the auto trim operation will be disabled and FREQSEL will be cleared to 00. 00 = Trim retry count limitation is 64 loops. 01 = Trim retry count limitation is 128 loops. 10 = Trim retry count limitation is 256 loops. 11 = Trim retry count limitation is 512 loops.
Trim Calculation Loop Selection
This field defines that trim value calculation is based on how many reference clocks. 00 = Trim value calculation is based on average difference in 4 clocks of reference clock. 01 = Trim value calculation is based on average difference in 8 clocks of reference clock. 10 = Trim value calculation is based on average difference in 16 clocks of reference clock. 11 = Trim value calculation is based on average difference in 32 clocks of reference clock.
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ISD94100 Series Technical Reference Manual
on the average frequency difference in 4 clocks of reference clock.
When writing to this field always write with
internal high speed RC
ror detected with CESTOPEN is set to 1 or trim retry
[3:2]
[1:0]
Reserved
FREQSEL
Reserved. Any values read should be ignored. reset value.
Trim Frequency Selection
This field indicates the target frequency of 48 MHz and 49.152 MHz oscillator (HIRC) auto trim.
During auto trim operation, if clock er limitation count reached, this field will be cleared to 00 automatically.
01 = Enable HIRC auto trim function and trim HIRC to 48 MHz. 11 = Enable HIRC auto trim function and trim HIRC to 49.152 MHz. Others = Disable HIRC auto trim function.
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R/W
R/W
. Any values read should be ignored. When writing to this fiel d always write with
This bit controls if CPU would get an interrupt while cl ock is inaccuracy during auto trim
If this bit is set to1, and CLKERRIF(SYS_IRCTISTS[2]) is set during auto trim operation, an
This bit controls if an interrupt will be triggered while HIRC trim value update limitation count reached and HIRC frequency still not locked on target frequency set by
during auto trim operation, an
. Any values read should be ignored. When writing to this fiel d always write with
HIRC Trim Interrupt Enable Register (SYS_IRCTIEN)
Register
SYS_IRCTIEN
Offset
SYS_BA+0xF4
Description Reset Value
HI RC Trim I nterrupt E nabl e Register 0x0000_0000
31 30 29 28 27 26 25 24
Reserved
23 22 21 20 19 18 17 16
Reserved
15 14 13 12 11 10 9 8
Reserved
7 6 5 4 3 2 1 0
Reserved CLKEIEN TFAILIEN Reserved
Bits
[31:3]
Description
Reserved
Reserved reset value.
Clock Error Interrupt Enable Bit
ISD94100 SERIES TECHNICAL REFERENCE MANUAL
operation.
[2]
[1]
[0]
CLKEIEN
TFAILIEN
Reserved
interrupt will be triggered to notify the clock frequency is inaccuracy. 0 = Disable CLKERRIF(SYS_IRCTISTS[2]) status to trigger an interrupt to CPU. 1 = Enable CLKERRIF(SYS_IRCTISTS[2]) status to trigger an interrupt to CPU.
Trim Failure Interrupt Enable Bit
FREQSEL(SYS_IRCTCTL[1:0]). If this bit is high and TFAILIF(SYS_IRCTISTS[1]) is set
interrupt will be triggered to notify that HIRC trim value update limitation count was reached. 0 = Disable TFAILIF(SYS_IRCTISTS[1]) status to trigger an interrupt to CPU. 1 = Enable TFAILIF(SYS_IRCTISTS[1]) status to trigger an interrupt to CPU.
Reserved reset value.
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ISD94100 Series Technical Reference Manual
R/W
R/W
. Any values read should be ignored. When writing to this fiel d always write with
When the frequency of 32.768 kHz external low speed crystal oscillat or (LXT) or internal
oscillator (HIRC) is shift larger to unreasonable value, this bit will be set and
Once this bit is set to 1, the auto trim operation stopped and FREQSEL(SYS_IRCTCL[1:0])
automatically if CESTOPEN(SYS_IRCTCTL[8]) is set to
If this bit is set and CLKEIEN(SYS_IRCTIEN[2]) is high, an interrupt will be triggered to notify
This bit indicates that HIRC trim value update limitation count reached and the HIRC clock
t be locked. Once this bit is set, the auto trim operation stopped and
If this bit is set and TF AILIEN(SYS_IRCTIEN[1]) is high, an interrupt will be triggered to notify
yet.
HIRC Trim Interrupt Status Register (SYS_IRCTISTS)
Register
SYS_IRCTISTS
Offset
SYS_BA+0xF8
Description Reset Value
HI RC Trim I nterrupt Status Register 0x0000_0000
31 30 29 28 27 26 25 24
Reserved
23 22 21 20 19 18 17 16
Reserved
15 14 13 12 11 10 9 8
Reserved
7 6 5 4 3 2 1 0
Reserved CLKERRIF TFAILIF FREQLOCK
Bits
[31:3]
ISD94100 SERIES TECHNICAL REFERENCE MANUAL
Description
Reserved
Reserved reset value.
Clock Error Interrupt Status
high speed RC to be an indicate that clock frequency is inaccuracy
[2]
[1]
[0]
CLKERRIF
TFAILIF
FREQLOCK
will be cleared to 00 by hardware
1.
the clock frequency is inaccuracy. Wri te 1 to clear this to 0. 0 = Clock frequency is accuracy. 1 = Clock frequency is inaccuracy.
Trim Failure Interrupt Status
frequency still doesn’ FREQSEL(SYS_IRCTCTL[1:0]) will be cleared to 00 by hardware automatically.
that HIRC trim value update limitation count was reached. Write 1 to clear this to 0. 0 = Trim value update limitation count does not reach. 1 = Trim value update limitation count reached and HIRC frequency still not locked.
HIRC Frequency Lock Status
This bit indicates the HIRC frequency is locked. This is a status bit and doesn’t trigger any interrupt Write 1 to clear this to 0. This bit will be set automatically, if the frequecy is lock. 0 = The internal high-speed oscillator frequency doesn’t lock at 48 MHz or 49.152 MHz 1 = The internal high-speed oscillator frequency locked at 48 MHz or 49.152 MHz.
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ISD94100 Series Technical Reference Manual
R/W
R/W
. Any values read should be ignored. When writing to this fiel d always write with
To write to these registers, this write
. After
registers
protected registers. Any write to the protected
up
Register Lock Control Register (SYS_REGLCTL)
This register is written to disable/enable register protection and read for the REGLCTL status. Some of the system control register s are protected to avo id inadverte nt write that may disturb the chip operation. These system control registers are protected after power-on reset until the user disables this register protection. For user to program these protected registers, a register protection disable sequence needs to be fol lowe d. The register protectio n dis a ble sequence is wr iting t he d ata “59h”, “16h” “88h” to the register SYS_REG LCTL address at 0x4000_01 00. Any different data value, different sequenc e or any other write to other address during thes e three data writes will abort the whole sequence. After the protection is disabled, user can check the protection disable bit at address 0x4000_0100 bit0, 1 is protection dis able, and 0 is protecti on enable. Then user can up date the tar get protec ted register value. The register protection can be re-enabled by writing any data to the address 0x4000_0100.
Register
Offset
Description Reset Value
SYS_REGLCTL
SYS_BA+0x100
Register Lock Control Register 0x0000_0000
31 30 29 28 27 26 25 24
Reserved
23 22 21 20 19 18 17 16
Reserved
15 14 13 12 11 10 9 8
Reserved
7 6 5 4 3 2 1 0
REGLCTL
Bits
[31:8]
[7:0]
Description
Reserved
REGLCTL
Reserved reset value.
Register Lock Control Code (Write Only)
Some registers have a write-protection function. protection must be by writing t he sequence value “59h”, “16h”, “88h” to this address this sequence is completed, the REGLCTL bit will be set to 1 and write-protected can be write accessed.
Register Lock Control Disable Index (Read Only)
0 = Write-protection Enabled for write registers is ignored.
1 = Write-protection Disabled for write protected registers. The Protected registers are:
SYS_IPRST0: address 0x4000_0008 SYS_BODCTL: address 0x4000_0018 SYS_PORCTL: address 0x4000_0024 SYS_USBPHY: address 0x4000_002C CLK_PWRCTL: address 0x4000_0200 (bit[6] is not protected for power-down wake-
interrupt clear) SYS_RCADJ: address 0x4000_0110
ISD94100 SERIES TECHNICAL REFERENCE MANUAL
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CLK_APBCLK0 [0]: address 0x4000_0208 (bit[0] is watchdog clock enable)
CLK_CLKSEL0: address 0x4000_0210 (for HCLK and CPU STCLK clock source select) CLK_CLKSEL1 [1:0]: address 0x4000_0214 (for watchdog clock source select) CLK_CLKSEL1 [31:30]: address 0x4000_0214 (for window watchdog clock source select) CLK_CLKDSTS: address 0x4000_0274 NMIEN: address 0x4000_0300 FMC_ISPCTL: address 0x4000_C000 (Flash ISP Control register) FMC_ISPTRG: address 0x4000_C010 (ISP Trigger Control register) FMC_ISPSTS: address 0x4000_C040 WDT_CTL: addres s 0x4004_0000 AHBMCTL: address 0x4000_0400 CLK_PLLCTL: address 0x4000_0240 PWM_CTL0: address 0x4005_8000 PWM_DTCTL0_1: address 0x4005_8070 PWM_DTCTL2_3: address 0x4005_8074 PWM_DTCTL4_5: address 0x4005_8078 PWM_BRKCTL0_1: address 0x4005_80C8 PWM_BRKCTL2_3: address 0x4005_80CC PWM_BRKCTL4_5: address 0x4005_80D0 PWM_INTEN1: address 0x4005_80E4 PWM_INTSTS1: address 0x4005_80EC
ISD94100 SERIES TECHNICAL REFERENCE MANUAL
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R/W
R/W
. Any values read should be ignored. When writing to this fiel d always write with
”
000_0100 to disable register protection. Refer to the register SYS_REGLCTL
HIRC Trim Value Register (SYS_RCADJ)
Register
SYS_RCADJ
Offset
SYS_BA+0x110
Description Reset Value
HI RC Trim V al ue Register 0x0000_0XXX
31 30 29 28 27 26 25 24
Reserved
23 22 21 20 19 18 17 16
Reserved
15 14 13 12 11 10 9 8
Reserved RCADJ
7 6 5 4 3 2 1 0
RCADJ
Bits
[31:10]
[9:0]
Reserved
RCADJ
Description
Reserved reset value.
HIRC Trim Value (Write Protect)
This bit is the protected bit, which means programming it needs to write “59h”, “16h”, “88h to address 0x4 at address SYS_BA+0x100.
This field reflects the HIRC trim value. Software can update HIRC trim value by writing this field. Note: This bit is write protected. Refer to the SYS_REGLCTL register.
ISD94100 SERIES TECHNICAL REFERENCE MANUAL
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Offset
R/W
SCS_BA+0x10
R/W
SCS_BA+0x14
R/W
SCS_BA+0x18
R/W

6.2.12 System Timer (SysTi ck)

The Cortex®-M4 integrates a system timer, SysTick, which provides a simple, 24-bit clear-on-write, decrementing, wrap-on-zero counter with a flexi ble control mechanism . The counter can be used as a Real Time Operating System (RTOS) tick timer or as a simple counter. When system tim er is enabled, it will count down from the value in the SysTick Current Value Register (SYST_VAL) to zero, and reload (wrap) to the value in the SysTick Reload Value Register (SYST_LOAD) on the next clock cycle, and then decrement on subsequent clocks. When the counter decrements to zero, the COUNT FLAG status bit is set. A read or write on C urrent Value Register clears the COUNTFLAG bit to 0. The SYST_VAL value is U NKNOWN on reset. Softwar e should write to the regi ster to clear it to zero before enablin g the feature. This ensures the t imer will count from the SYST_LOAD value rather than an arbitrary value when it is enabled. If the SYST_LOAD is zero, the timer will be mainta ined with a current value of zero after it is reloaded with this value. This m echanism can be used to disa ble the feature independen tly from the timer enable bit. For more detailed information, please refer to the “ARM
®
and “ARM
v6-M Architecture Reference Manual”.
6.2.12.1 System Timer Control Register M ap
R: read only, W: write only, R/W: both read and write
Register
Description Reset Value
®
Cortex™-M4 Technical Reference Manual”
SYST Base Address: SCS_BA = 0xE000_E000
ISD94100 SERIES TECHNICAL REFERENCE MANUAL
SYST_CTRL
SYST_LOAD
SYST_VAL
Note:
1. Any register not listed here is reserved and must not be written. The result of a read operation on these bits is undefined.
2. The reserved register fields that listed in register description must be written to their reset value. Writing reserved fields with other than reset values may produce undefined results.
SysT ick Cont rol and Status Register 0x0000_0000
SysT ick Reload Value Regist er 0x0000_0000
SysT ick Current Value Regist er 0x0000_0000
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ISD94100 Series Technical Reference Manual
R/W
R/W
. Any values read should be ignored. When writing to this fiel d always write with
always wri te wit h
SysTick exception to be pended. Software can
1 = Counting down to 0 will cause the SysT ick ex ception to be pended. Clearing the SysT ick
6.2.12.2 System Timer Control Register Description
SysTick Control and Status Register (SYST_CTRL)
Register
SYST_CTRL
Offset
SCS_BA+0x10
Description Reset Value
S ys T ick Cont rol and Stat us Register 0x0000_0000
31 30 29 28 27 26 25 24
Reserved
23 22 21 20 19 18 17 16
Reserved COUNTFLAG
15 14 13 12 11 10 9 8
Reserved
7 6 5 4 3 2 1 0
Reserved CLKSRC TICKINT ENABLE
Bits
[31:17]
[16]
Description
Reserved
COUNTFLAG
Reserved reset value.
System Tick Counter Flag
Returns 1 if timer counted to 0 since last time this register was read. COUNTFLAG is set by a count transition from 1 to 0. COUNTFLAG is cleared on read or by a write to the Current Value register.
ISD94100 SERIES TECHNICAL REFERENCE MANUAL
[15:3]
[2]
[1]
[0]
Sep 9, 2019 Page 99 of 928 Rev1.09
Reserved
CLKSRC
TICKINT
ENABLE
Reserved. Any values read should be ignored. When writing to this fi eld reset value.
System Tick Clock Source Selection
0 = Clock source is the (optional) external reference clock. 1 = Core clock used for SysTick.
System Tick Interrupt Enabled
0 = Counting down to 0 does not cause the use COUNTFLAG to determine if a count to zero has occurred.
current value register by a register write in software will not cause SysTick to be pended.
System Tick Counter Enabled
0 = Counter Disabled. 1 = Counter will operate in a multi-shot manner.
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ISD94100 Series Technical Reference Manual
R/W
R/W
When writing to this field always write with
SysTick Reload Value Register (SYST_LOAD)
Register
SYST_LOAD
31 30 29 28 27 26 25 24
23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8
7 6 5 4 3 2 1 0
Offset
SCS_BA+0x14
Description Reset Value
S ys T ick Rel oad Value Regist er 0x0000_0000
Reserved
RELOAD
RELOAD
RELOAD
Bits
[31:24]
ISD94100 SERIES TECHNICAL REFERENCE MANUAL
[23:0]
Description
Reserved
RELOAD
Reserved. Any values read should be ignored. reset value.
System Tick Reload Value
Value to load into the Current Value register when the counter reaches 0.
Sep 9, 2019 Page 100 of 928 Rev1.09
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