NSC MM80C97N, MM80C96J, MM80C95J, MM70C98N, MM70C98J Datasheet
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TL/F/5907
MM70C95/MM80C95, MM70C97/MM80C97 TRI-STATE Hex Buffers
MM70C96/MM80C96, MM70C98/MM80C98 TRI-STATE Hex Inverters
February 1988
MM70C95/MM80C95, MM70C97/MM80C97
TRI-STATE
É
Hex Buffers
MM70C96/MM80C96, MM70C98/MM80C98
TRI-STATE Hex Inverters
General Description
These gates are monolithic complementary MOS (CMOS)
integrated circuits constructed with N- and P-channel enhancement mode transistors. The MM70C95/MM80C95
and the MM70C97/MM80C97 convert CMOS or TTL outputs to TRI-STATE outputs with no logic inversion, the
MM70C96/MM80C96 and the MM70C98/MM80C98 provide the logical opposite of the input signal. The MM70C95/
MM80C95 and the MM70C96/MM80C96 have common
TRI-STATE controls for all six devices. The MM70C97/
MM80C97 and the MM70C98/MM80C98 have two TRISTATE controls; one for two devices and one for the other
four devices. Inputs are protected from damage due to static discharge by diode clamps to V
CC
and GND.
Features
Y
Wide supply voltage range 3.0V to 15V
Y
Guaranteed noise margin 1.0V
Y
High noise immunity 0.45 VCC(typ.)
Y
TTL compatible Drive 1 TTL Load
Applications
Y
Bus drivers Typical propagation delay
into 150 pF load is 40 ns
Connection Diagrams (Dual-In-Line Packages)
MM70C95/MM80C95
TL/F/5907– 1
Top View
Order Number MM70C95 or MM80C95
MM70C96/MM80C96
TL/F/5907– 2
Top View
Order Number MM70C96 or MM80C96
MM70C97/MM80C97
TL/F/5907– 3
Top View
Order Number MM70C97 or MM80C97
MM70C98/MM80C98
TL/F/5907– 4
Top View
Order Number MM70C98 or MM80C98
TRI-STATEÉis a registered trademark of National Semiconductor Corporation.
C
1995 National Semiconductor Corporation RRD-B30M105/Printed in U. S. A.
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Voltage at Any Pin
b
0.3V to V
CC
a
0.3V
Operating Temperature Range
MM70CXX
b
55§Ctoa125§C
MM80CXX
b
40§Ctoa85§C
Storage Temperature Range
b
65§Ctoa150§C
Power Dissipation (PD)
Dual-In-Line 700 mW
Small Outline 500 mW
Power Supply Voltage (V
CC
) 18V
Lead Temperature
(Soldering, 10 seconds) 260
§
C
DC Electrical Characteristics Min/Max limits apply across temperature range unless otherwise noted
Symbol Parameter Conditions Min Typ Max Units
CMOS TO CMOS
V
IN(1)
Logical ‘‘1’’ Input Voltage V
CC
e
5V 3.5 V
V
CC
e
10V 8.0 V
V
IN(0)
Logical ‘‘0’’ Input Voltage V
CC
e
5V 1.5 V
V
CC
e
10V 2.0 V
V
OUT(1)
Logical ‘‘1’’ Output Voltage V
CC
e
5V 4.5 V
V
CC
e
10V 9.0 V
V
OUT(0)
Logical ‘‘0’’ Output Voltage V
CC
e
5V 0.5 V
V
CC
e
10V 1.0 V
I
IN(1)
Logical ‘‘1’’ Input Current V
CC
e
15V 0.005 1.0 mA
I
IN(0)
Logical ‘‘0’’ Input Current
b
1.0
b
0.005 mA
I
OZ
Output Current in High V
CC
e
15V, V
O
e
15V 0.005 1.0 mA
Impedance State V
CC
e
15V, V
O
e
0V
b
1.0
b
0.005 mA
I
CC
Supply Current V
CC
e
15V 0.01 15 mA
TTL INTERFACE
V
IN(1)
Logical ‘‘1’’ Input Voltage 70C V
CC
e
4.5V V
CC
b
1.5 V
80C V
CC
e
4.75V V
CC
b
1.5 V
V
IN(0)
Logical ‘‘0’’ Input Voltage 70C V
CC
e
4.5V 0.8 V
80C V
CC
e
4.75V 0.8 V
V
OUT(1)
Logical ‘‘1’’ Output Voltage 70C V
CC
e
4.5V, I
O
eb
1.6 mA 2.4 V
80C V
CC
e
4.75V, I
O
eb
1.6 mA 2.4 V
V
OUT(0)
Logical ‘‘0’’ Output Voltage 70C V
CC
e
4.5V, I
O
e
1.6 mA 0.4 V
80C V
CC
e
4.75V, I
O
e
1.6 mA 0.4 V
OUTPUT DRIVE (Short Circuit Current)
I
SOURCE
Output Source Current V
CC
e
5V, V
IN(1)
e
5V
b
4.35 mA
T
A
e
25§C, V
OUT
e
0V
I
SOURCE
Output Source Current V
CC
e
10V, V
IN(1)
e
10V
b
20 mA
T
A
e
25§C, V
OUT
e
0V
I
SINK
Output Sink Current V
CC
e
5V, V
IN(0)
e
0V
4.35 mA
T
A
e
25§C, V
OUT
e
V
CC
I
SINK
Output Sink Current V
CC
e
10V, V
IN(0)
e
0V
20 mA
T
A
e
25§C, V
OUT
e
V
CC
Note 1: ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed. Except for ‘‘Operating Temperature Range’’
they are not meant to imply that the device should be operated at these limits. The table of ‘‘Electrical Characteristics’’ provides conditions for actual device
operation.
Note 2: Capacitance is guaranteed by periodic testing.
Note 3: C
PD
determines the no load AC power consumption of any CMOS device. For complete explanation see 54C/74C Family Characteristics application note
AN-90.
2
AC Electrical Characteristics* T
A
e
25§C, C
L
e
50 pF, unless otherwise noted.
Symbol Parameter Conditions Min Typ Max Units
t
pd0,tpd1
Propagation Delay Time to a Logical ‘‘0’’ or
Logical ‘‘1’’ from Data Input to Output
MM70C95/MM80C95, MM70C97/MM80C97 V
CC
e
5V 60 100 ns
V
CC
e
10V 25 40 ns
MM70C96/MM80C96, MM70C98/MM80C98 V
CC
e
5V 70 150 ns
V
CC
e
10V 35 75 ns
t
pd0,tpd1
Propagation Delay Time to a Logical ‘‘0’’ or
Logical ‘‘1’’ from Data Input to Output
MM70C95/MM80C95, MM70C97/MM80C97 V
CC
e
5V, C
L
e
150 pF 85 160 ns
V
CC
e
10V, C
L
e
150 pF 40 80 ns
MM70C96/MM80C96, MM70C98/MM80C98 V
CC
e
5V, C
L
e
150 pF 95 210 ns
V
CC
e
10V, C
L
e
150 pF 45 110 ns
t1H,t
0H
Delay from Disable Input to High Impedance
R
L
e
10k, C
L
e
5pF
State, (from Logical ‘‘1’’ or Logical ‘‘0’’)
MM70C95/MM80C95 V
CC
e
5V 80 135 ns
V
CC
e
10V 50 90 ns
MM70C96/MM80C96 V
CC
e
5V 100 180 ns
V
CC
e
10V 70 125 ns
MM70C97/MM80C97 V
CC
e
5V 70 125 ns
V
CC
e
10V 50 90 ns
MM70C98/MM80C98 V
CC
e
5V 90 170 ns
V
CC
e
10V 70 125 ns
tH1,t
H0
Delay from Disable Input to Logical ‘‘1’’ Level
R
L
e
10k, C
L
e
50 pF
(from High Impedance State)
MM70C95/MM80C95 V
CC
e
5V 120 200 ns
V
CC
e
10V 50 90 ns
MM70C96/MM80C96 V
CC
e
5V 130 225 ns
V
CC
e
10V 60 110 ns
MM70C97/MM80C97 V
CC
e
5V 95 175 ns
V
CC
e
10V 40 80 ns
MM70C98/MM80C98 V
CC
e
5V 120 200 ns
V
CC
e
10V 50 90 ns
C
IN
Input Capacitance Any Input (Note 2) 5.0 pF
C
OUT
Output Capacitance TRI-STATE Any Output (Note 2) 11 pF
C
PD
Power Dissipation Capacitance (Note 3) 60 pF
*AC Parameters are guaranteed by DC correlated testing.
Truth Tables
MM70C95/MM80C95
Disable Input
Input Output
DIS
1
DIS
2
0000
0011
0 1 X H-z
1 0 X H-z
1 1 X H-z
MM70C96/MM80C96
Disable Input
Input Output
DIS
1
DIS
2
0001
0010
0 1 X H-z
1 0 X H-z
1 1 X H-z
MM70C97/MM80C97
Disable Input
Input Output
DIS
4
DIS
2
0000
0011
X 1 X H-z*
1 X X H-z**
*Output 5– 6 only
**Output 1– 4 only
X
e
Irrelevant
MM70C98/MM80C98
Disable Input
Input Output
DIS
4
DIS
2
0001
0010
X 1 X H-z*
1 X X H-z**
3
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