NSC MM58174AN Datasheet

MM58174A
Microprocessor-Compatible Real-Time Clock

Y

General Description

The MM58174A is a low-threshold metal-gate CMOS circuit
that functions as a real-time clock and calendar in bus-ori­ented microprocessor systems. The device includes an in­terrupt timer which may be programmed to one of three
times. Timekeeping is maintained down to 2.2V to allow low
power standby battery operation. The timebase is generat­ed from a 32768 Hz crystal-controlled oscillator.

Features

Y

Microprocessor compatible

Y

Tenths of seconds, seconds, tens of seconds, minutes,
tens of minutes, day of week, days, tens of days,
months, tens of months, independent registers

Y

Automatic leap year calculation

Y

Internal pull-ups to safeguard data

Y

Protection for read during data changing

Y

Independent interrupt system with open drain output

Block Diagram

TTL compatible

Y

Low power standby operation (2.2V, 10 mA)

Y

Low cost internally biased oscillator

Y

Low cost 16-pin dual-in-line package

Y

Available for commercial and military temperature
ranges

Applications

Y

Point-of-sale terminals

Y

Word processors

Y

Teller terminals

Y

Event recorders

Y

Microprocessor-controlled instrumentation

Y

Microprocessor time clock

Y

TV/VCR reprogramming

Y

Intelligent telephone

MM58174A Microprocessor-Compatible Real-Time Clock

May 1991

FIGURE 1

TL/F/6681– 1

TRI-STATEÉis a registered trademark of National Semiconductor Corporation.

C

1995 National Semiconductor Corporation RRD-B30M105/Printed in U. S. A.

TL/F/6681

Absolute Maximum Ratings

If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.

Voltage at All Inputs and Outputs V

Operating Temperature

MM58174AN

DD

a

0.3 to V

SS

b

40§Ctoa85§C

b

0.3

Storage Temperature

VDD–V

SS

b

65§Ctoa150§C

6.5V

Lead Temperature (Soldering, 10 seconds) 300§C

Electrical Characteristics T

eb

40§Ctoa85§C, V

A

e

0V

SS

Symbol Parameter Conditions Min Typ Max Units

V

DD

Supply Voltage Standby Mode

(no READ or WRITE Instructions)

2.2 5.5 V

Operational Mode 4.5 5.5 V

I

DD

Supply Current V

Input Logic Levels V
for Signals:

e

2.2V (Standby) 10 mA

DD

e

V

5V (Operating) 1 mA

DD

e

5V

DD

AD0–AD3, DB0–DB3, WR, RD, CS

Logic ‘‘1’’ 2 V
Logic ‘‘0’’ 0.8 V

Input Capacitance 10 pF

Input Current Levels V

Current to V
for Signals:

SS

AD0–AD3, DB0–DB3, RD

Internal Resistor to V
for Signals:

DD

WR

e

5V

DD

e

V

V

IN

DD

30 mA

30 100 kX

CS 30 100 kX

Output Logic Levels V
for Signals:

DD

e

5V

DB0–DB3

Logic ‘‘1’’ I
Logic ‘‘0’’ I

INTERRUPT (Open Drain)

Logic ‘‘0’’ For I
Off Leakage V

eb

0.1 mA 2.4 V

OH

e

1.6 mA 0.4 V

OL

e

1.6 mA 0.4 V

DS

e

5V 5 mA

OUT

2

Functional Description

The MM58174 is a microprocessor bus-oriented real-time
clock. The circuit includes addressable real-time counters
for tenths of seconds through months and a write only regis­ter for leap year calculation. The counters are arranged as
bytes of four bits each. When addressed a byte will appear
on the data I/O bus so that each word can be accessed
independently. If any byte does not contain four bits (e.g.,
days of the week uses only 3 bits), the unused bits will be
unrecognized during a write operation and tied to V
a read operation.

The addressable reset latch causes the pre-scaler, tenths of
seconds, seconds, and tens of seconds to be held in a reset
condition. If a register is updated during a read operation the
I/O data is prevented from updating and a subsequent read
will return the illegal b.c.d. code ’1111’. The interrupt timer
may be programmed for intervals of 0.5 second, 5 seconds,
or 60 seconds and may be coded as a single or repeated
operation. The open drain interrupt output is pulled to V
when the timer times out and reading the interrupt register
provides the internal selected information.

SS

during

SS

Circuit Description

The block diagram shown in
the CMOS clock chip. A 16-pin DIL package is used.

CRYSTAL OSCILLATOR

This consists of a CMOS inverter/amplifier with on-chip bias
resistor and capacitors. A single 6 pF – 36 pF trimmer is all
that is required to fine tune the crystal (see
ever, for improved stability, some crystals may require a ca­pacitor of typical value 20 pF to be added between pin 14
and ground. The output of the oscillator is blocked by the
start/stop F/F.

NON-INTEGER DIVIDER

This counter divides the incoming 32,768 Hz frequency by
15/16 down to 30,720 Hz.

FIXED DIVIDER (512)

This is a standard 9-stage binary ripple counter. Output fre­quency is 60 Hz. This counter is reset to zero by start/stop
F/F.

FIXED DIVIDER (6)

This is a 3-stage Johnson counter with a 10 Hz output sig­nal. This counter is reset to zero state by the start/stop F/F.

SYNCHRONIZATION STAGE

Both 10 Hz and 32,768 Hz clocks are fed into this section. It
is used to generate a pulse of 15.25 ms width on the rising
edge of each 10 Hz pulse.

This pulse is used to increment all the seconds, minutes,
hours, days, months, and year counter and also to set the
data changed F/F.

DATA CHANGED F/F

This is set by the rising edge of each 10 Hz pulse to indicate
that the clock value has changed since the last read opera­tion. It is reset by any clock read command.

The flip flop sets all data bus bits to a ‘‘1’’ during RD time
indicating that a register has been updated. This transient
condition may occur at the end of the Read Data strobe.
Hence, invalid data may still be read from the clock, if the
strobe width was less than 3 ms.

Figure 1

shows the structure of

Figure 2

). How-

Connection Diagram

Dual-In-Line Package

TL/F/6681– 2

Top View

Order Number MM58174AN

See NS Package Number N16A

The possibility may be overcome by implementing a further
read of the tenths of seconds register at the end of every
series of reads (starting with a read at the tenths of seconds
register) and checking for unchanged data.

SECONDS COUNTERS

There are three counters for Seconds:

a) tenths of seconds

b) units of seconds

c) tens of seconds

The outputs of all three counters can be separately multi­plexed on to the command 4-bit output bus. Table I shows
the address decoding for each counter. All three counters
are reset to zero by the start/stop F/F.

MINUTES COUNTERS

There are two Minutes counters:

a) units of minutes

b) tens of minutes

Both counters are parallel loaded with data from the 4-bit
input bus when addressed by the microprocessor and a
Write Data Strobe pulse given. Similarly, the output of both
counters can be read separately onto the common 4-bit out­put bus (Table I).

HOURS COUNTERS

There are two Hours counters which will count in a 24-hour
mode:

a) units of hours

b) tens of hours

Both counters have identical parallel load and read multi­plex features to the Minutes counters.

SEVEN DAY COUNTER

There is a 7-state counter which increments every 24 hours.
It will have identical parallel load and read multiplex capabili­ties to the Minutes and Hours counters. The counter counts
cyclically from 1 – 7.

3