NSC MM54C923J-MIL Datasheet
TL/F/6037
MM54C922/MM74C922 16-Key Encoder, MM54C923/MM74C923 20-Key Encoder
July 1993
MM54C922/MM74C922 16-Key Encoder
MM54C923/MM74C923 20-Key Encoder
General Description
These CMOS key encoders provide all the necessary logic
to fully encode an array of SPST switches. The keyboard
scan can be implemented by either an external clock or
external capacitor. These encoders also have on-chip pullup devices which permit switches with up to 50 kX on resistance to be used. No diodes in the switch array are needed
to eliminate ghost switches. The internal debounce circuit
needs only a single external capacitor and can be defeated
by omitting the capacitor. A Data Available output goes to a
high level when a valid keyboard entry has been made. The
Data Available output returns to a low level when the entered key is released, even if another key is depressed. The
Data Available will return high to indicate acceptance of the
new key after a normal debounce period; this two-key rollover is provided between any two switches.
An internal register remembers the last key pressed even
after the key is released. The TRI-STATE
É
outputs provide
for easy expansion and bus operation and are LPTTL compatible.
Features
Y
50 kX maximum switch on resistance
Y
On or off chip clock
Y
On-chip row pull-up devices
Y
2 key roll-over
Y
Keybounce elimination with single capacitor
Y
Last key register at outputs
Y
TRI-STATE outpust LPTTL compatible
Y
Wide supply range 3V to 15V
Y
Low power consumption
Connection Diagrams
Pin Assignment for
Dual-In-Line Package
TL/F/6037– 1
Top View
Order Number MM54C922 or
MM74C922
Pin Assignment
for SOIC
TL/F/6037– 14
Top View
Order Number MM74C922
Pin Assignment for
DIP and SOIC Package
TL/F/6037– 2
Top View
Order Number MM54C923 or
MM74C923
TRI-STATEÉis a registered trademark of National Semiconductor Corporation.
C
1995 National Semiconductor Corporation RRD-B30M105/Printed in U. S. A.
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Voltage at Any Pin V
CC
b
0.3V to V
CC
a
0.3V
Operating Temperature Range
MM54C922, MM54C923
b
55§Ctoa125§C
MM74C922, MM74C923
b
40§Ctoa85§C
Storage Temperature Range
b
65§Ctoa150§C
Power Dissipation (PD)
Dual-In-Line 700 mW
Small Outline 500 mW
Operating V
CC
Range 3V to 15V
V
CC
18V
Lead Temperature
(Soldering, 10 seconds) 260
§
C
DC Electrical Characteristics Min/Max limits apply across temperature range unless otherwise specified
Symbol Parameter Conditions Min Typ Max Units
CMOS TO CMOS
V
T
a
Positive-Going Threshold Voltage V
CC
e
5V, I
IN
t
0.7 mA 3.0 3.6 4.3 V
at Osc and KBM Inputs V
CC
e
10V, I
IN
t
1.4 mA 6.0 6.8 8.6 V
V
CC
e
15V, I
IN
t
2.1 mA 9.0 10 12.9 V
V
T
b
Negative-Going Threshold Voltage V
CC
e
5V, I
IN
t
0.7 mA 0.7 1.4 2.0 V
at Osc and KBM Inputs V
CC
e
10V, I
IN
t
1.4 mA 1.4 3.2 4.0 V
V
CC
e
15V, I
IN
t
2.1 mA 2.1 5 6.0 V
V
IN(1)
Logical ‘‘1’’ Input Voltage, V
CC
e
5V 3.5 4.5 V
Except Osc and KBM Inputs V
CC
e
10V 8.0 9 V
V
CC
e
15V 12.5 13.5 V
V
IN(0)
Logical ‘‘0’’ Input Voltage, V
CC
e
5V 0.5 1.5 V
Except Osc and KBM Inputs V
CC
e
10V 1 2 V
V
CC
e
15V 1.5 2.5 V
I
rp
Row Pull-Up Current at Y1, Y2, V
CC
e
5V, V
IN
e
0.1 V
CC
b
2
b
5 mA
Y3, Y4 and Y5 Inputs V
CC
e
10V
b
10
b
20 mA
V
CC
e
15V
b
22
b
45 mA
V
OUT(1)
Logical ‘‘1’’ Output Voltage V
CC
e
5V, I
O
eb
10 mA 4.5 V
V
CC
e
10V, I
O
eb
10 mA9 V
V
CC
e
15V, I
O
eb
10 mA 13.5 V
V
OUT(0)
Logical ‘‘0’’ Output Voltage V
CC
e
5V, I
O
e
10 mA 0.5 V
V
CC
e
10V, I
O
e
10 mA1V
V
CC
e
15V, I
O
e
10 mA 1.5 V
R
on
Column ‘‘ON’’ Resistance at V
CC
e
5V, V
O
e
0.5V 500 1400 X
X1, X2, X3 and X4 Outputs V
CC
e
10V, V
O
e
1V 300 700 X
V
CC
e
15V, V
O
e
1.5V 200 500 X
I
CC
Supply Current V
CC
e
5V 0.55 1.1 mA
Osc at 0V, (one Y low) V
CC
e
10V 1.1 1.9 mA
V
CC
e
15V 1.7 2.6 mA
I
IN(1)
Logical ‘‘1’’ Input Current V
CC
e
15V, V
IN
e
15V
0.005 1.0 mA
at Output Enable
I
IN(0)
Logical ‘‘0’’ Input Current V
CC
e
15V, V
IN
e
0V
b
1.0
b
0.005 mA
at Output Enable
CMOS/LPTTL INTERFACE
V
IN(1)
Logical ‘‘1’’ Input Voltage, 54C, V
CC
e
4.5V V
CC
b
1.5 V
Except Osc and KBM Inputs 74C, V
CC
e
4.75V V
CC
b
1.5 V
V
IN(0)
Logical ‘‘0’’ Input Voltage, 54C, V
CC
e
4.5V 0.8 V
Except Osc and KBM Inputs 74C, V
CC
e
4.75V 0.8 V
V
OUT(1)
Logical ‘‘1’’ Output Voltage 54C, V
CC
e
4.5V
2.4 V
I
O
eb
360 mA
74C, V
CC
e
4.75V
2.4 V
I
O
eb
360 mA
V
OUT(0)
Logical ‘‘0’’ Output Voltage 54C, V
CC
e
4.5V
0.4 V
I
O
eb
360 mA
74C, V
CC
e
4.75V
0.4 V
I
O
eb
360 mA
Note 1: ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed. Except for ‘‘Operating Temperature Range’’
they are not meant to imply that the devices should be operated at these limits. The table of ‘‘Electrical Characteristics’’ provides conditions for actual device
operation.
2
DC Electrical Characteristics
Min/Max limits apply across temperature range unless otherwise specified (Continued)
Symbol Parameter Conditions Min Typ Max Units
OUTPUT DRIVE (See 54C/74C Family Characteristics Data Sheet) (Short Circuit Current)
I
SOURCE
Output Source Current V
CC
e
5V, V
OUT
e
0V,
b
1.75
b
3.3 mA
(P-Channel) T
A
e
25§C
I
SOURCE
Output Source Current V
CC
e
10V, V
OUT
e
0V,
b
8
b
15 mA
(P-Channel) T
A
e
25§C
I
SINK
Output Sink Current V
CC
e
5V, V
OUT
e
VCC,
1.75 3.6 mA
(N-Channel) T
A
e
25§C
I
SINK
Output Sink Current V
CC
e
10V, V
OUT
e
VCC,
816 mA
(N-Channel) T
A
e
25§C
AC Electrical Characteristics* T
A
e
25§C, C
L
e
50 pF, unless otherwise noted
Symbol Parameter Conditions Min Typ Max Units
t
pd0,tpd1
Propagation Delay Time to C
L
e
50 pF
(Figure 1)
Logical ‘‘0’’ or Logical ‘‘1’’ V
CC
e
5V 60 150 ns
from D.A. V
CC
e
10V 35 80 ns
V
CC
e
15V 25 60 ns
t0H,t
1H
Propagation Delay Time from R
L
e
10k, C
L
e
10 pF
(Figure 2)
Logical ‘‘0’’ or Logical ‘‘1’’ V
CC
e
5V, R
L
e
10k 80 200 ns
into High Impedance State V
CC
e
10V, C
L
e
10 pF 65 150 ns
V
CC
e
15V 50 110 ns
tH0,t
H1
Propagation Delay Time from R
L
e
10k, C
L
e
50 pF
(Figure 2)
High Impedance State to a V
CC
e
5V, R
L
e
10k 100 250 ns
Logical ‘‘0’’ or Logical ‘‘1’’ V
CC
e
10V, C
L
e
50 pF 55 125 ns
V
CC
e
15V 40 90 ns
C
IN
Input Capacitance Any Input (Note 2) 5 7.5 pF
C
OUT
TRI-STATE Output Capacitance Any Output (Note 2) 10 pF
*AC Parameters are guaranteed by DC correlated testing.
Note 1: ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed. Except for ‘‘Operating Temperature Range’’
they are not meant to imply that the devices should be operated at these limits. The table of ‘‘Electrical Characteristics’’ provides conditions for actual device
operation.
Note 2: Capacitance is guaranteed by periodic testing.
Switching Time Waveforms
TL/F/6037– 3
T1&T2&RC, T3&0.7 RC, where R&10k and C is external capacitor at KBM input.
FIGURE 1
TL/F/6037– 4
FIGURE 2
3
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