NSC MM54C906J-883 Datasheet
TL/F/5911
MM54C906/MM74C906 Hex Open Drain N-Channel Buffers
MM54C907/MM74C907 Hex Open Drain P-Channel Buffers
March 1988
MM54C906/MM74C906
Hex Open Drain N-Channel Buffers
MM54C907/MM74C907
Hex Open Drain P-Channel Buffers
General Description
These buffers employ monolithic CMOS technology in
achieving open drain outputs. The MM54C906/MM74C906
consists of six inverters driving six N-channel devices; and
the MM54C907/MM74C907 consists of six inverters driving
six P-channel devices. The open drain feature of these buffers makes level shifting or wire AND and wire OR functions
by just the addition of pull-up or pull-down resistors. All inputs are protected from static discharge by diode clamps to
V
CC
and to ground.
Features
Y
Wide supply voltage range 3V to 15V
Y
Guaranteed noise margin 1V
Y
High noise immunity 0.45 VCC(typ.)
Y
High current sourcing and sinking
open drain outputs
Connection and Logic Diagrams
Dual-In-Line Package
TL/F/5911– 1
Top View
Order Number MM54C906, MM54C907, MM74C906 or MM74C907
MM54C906/MM74C906
TL/F/5911– 2
MM54C907/MM74C907
TL/F/5911– 3
C
1995 National Semiconductor Corporation RRD-B30M105/Printed in U. S. A.
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Voltage at Any Input Pin
b
0.3V to V
CC
a
0.3V
Voltage at Any Output Pin
MM54C906/MM74C906
b
0.3V toa18V
MM54C907/MM74C907 V
CC
b
18 to V
CC
a
0.3V
Operating Temperature Range
MM54C906/MM54C907
b
55§Ctoa125§C
MM74C906/MM74C907
b
40§Ctoa85§C
Storage Temperature Range
b
65§Ctoa150§C
Power Dissipation
Dual-In-Line 700 mW
Small Outline 500 mW
Operating V
CC
Range 3V to 15V
Absolute Maximum V
CC
18V
Lead Temperature (TL)
(Soldering, 10 seconds) 260
§
C
DC Electrical Characteristics Min/Max limits apply across temperature range unless otherwise noted
Symbol Parameter Conditions Min Typ Max Units
CMOS TO CMOS
V
IN(1)
Logical ‘‘1’’ Input Voltage V
CC
e
5V 3.5 V
V
CC
e
10V 8.0 V
V
IN(0)
Logical ‘‘0’’ Input Voltage V
CC
e
5V 1.5 V
V
CC
e
10V 2 V
I
IN(1)
Logical ‘‘1’’ Input Current V
CC
e
15V, V
IN
e
15V 0.005 1 mA
I
IN(0)
Logical ‘‘0’’ Input Current V
CC
e
15V, V
IN
e
0V
b
1.0
b
0.005 mA
I
CC
Supply Current V
CC
e
15V, Output Open 0.05 15 mA
Output Leakage
MM54C906 V
CC
e
4.5V, V
IN
e
V
CC
b
1.5V
0.005 5 mA
V
CC
e
4.5V, V
OUT
e
18V
MM74C906 V
CC
e
4.75V, V
IN
e
V
CC
b
1.5V
0.005 5 mA
V
CC
e
4.75V, V
OUT
e
18V
MM54C907 V
CC
e
4.5V, V
IN
e1Va
0.1 V
CC
0.005 5 mA
V
CC
e
4.5V, V
OUT
e
V
CC
b
18V
MM74C907 V
CC
e
4.75V, V
IN
e1Va
0.1 V
CC
0.005 5 mA
V
CC
e
4.75V, V
OUT
e
V
CC
b
18V
CMOS/LPTTL INTERFACE
V
IN(1)
Logical ‘‘1’’ Input Voltage 54C, V
CC
e
4.5V V
CC
b
1.5V V
74C, V
CC
e
4.75V V
CC
b
1.5V V
V
IN(0)
Logical ‘‘0’’ Input Voltage 54C, V
CC
e
4.5V 0.8 V
74C, V
CC
e
4.75V 0.8 V
OUTPUT DRIVE CURRENT
MM54C906 V
CC
e
4.5V, V
IN
e1Va
0.1 V
CC
V
CC
e
4.5V, V
OUT
e
0.5V 2.1 8.0 mA
V
CC
e
4.5V, V
OUT
e
1.0V 4.2 12.0 mA
MM74C906 V
CC
e
4.75V, V
IN
e1Va
0.1 V
CC
V
CC
e
4.75V, V
OUT
e
0.5V 2.1 8.0 mA
V
CC
e
4.75V, V
OUT
e
1.0V 4.2 12.0 mA
MM54C907 V
CC
e
4.5V, V
IN
e
V
CC
b
1.5V
V
CC
e
4.5V, V
OUT
e
V
CC
b
0.5V
b
1.05
b
1.5 mA
V
CC
e
4.5V, V
OUT
e
V
CC
b
1V
b
2.1
b
3.0 mA
MM74C907 V
CC
e
4.75V, V
IN
e
V
CC
b
1.5V
V
CC
e
4.75V, V
OUT
e
V
CC
b
0.5V
b
1.05
b
1.5 mA
V
CC
e
4.75V, V
OUT
e
V
CC
b
1V
b
2.1
b
3.0 mA
MM54C906/MM74C906 V
CC
e
10V, V
IN
e
2V
V
CC
e
10V, V
OUT
e
0.5V 4.2
b
20 mA
V
CC
e
10V, V
OUT
e
1V 8.4
b
30 mA
MM54C907/MM74C907 V
CC
e
10V, V
IN
e
8V
V
CC
e
10V, V
OUT
e
9.5V
b
2.1
b
4.0 mA
V
CC
e
10V, V
OUT
e
9V
b
4.2
b
8.0 mA
2
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