NSC MM54C74J-883 Datasheet

TL/F/5885

MM54C74/MM74C74 Dual D Flip-Flop

February 1988

MM54C74/MM74C74 Dual D Flip-Flop

General Description

The MM54C74/MM74C74 dual D flip-flop is a monolithic
complementary MOS (CMOS) integrated circuit constructed
with N- and P-channel enhancement transistors. Each flip­flop has independent data, preset, clear and clock inputs
and Q and Q

outputs. The logic level present at the data
input is transferred to the output during the positive going
transition of the clock pulse. Preset or clear is independent
of the clock and accomplished by a low level at the preset
or clear input.

Features

Y

Supply voltage range 3V to 15V

Y

Tenth power TTL compatible Drive 2 LPT2L loads

Y

High noise immunity 0.45 VCC(typ.)

Y

Low power 50 nW (typ.)

Y

Medium speed operation 10 MHz (typ.)

with 10V supply

Applications

Y

Automotive

Y

Data terminals

Y

Instrumentation

Y

Medical electronics

Y

Alarm system

Y

Industrial electronics

Y

Remote metering

Y

Computers

Logic Diagram

TL/F/5885– 1

Truth Table

Preset Clear Q

n

Q

n

0000
0110
1001
11*Q

n

*Q

n

*No change in output from previous state.

Order Number MM54C74 or MM74C74

Connection Diagram

Dual-In-Line Package

TL/F/5885– 2

Top View

Note: A logic ‘‘0’’ on clear sets Q to logic ‘‘0’’.

A logic ‘‘0’’ on preset sets Q to logic ‘‘1’’.

C

1995 National Semiconductor Corporation RRD-B30M105/Printed in U. S. A.

Absolute Maximum Ratings (Note 1)

If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.

Voltage at Any Pin (Note 1)

b

0.3V to V

CC

a

0.3V

Operating Temperature Range

MM54C74

b

55§Ctoa125§C

MM74C74

b

40§Ctoa85§C

Storage Temperature Range

b

65§Ctoa150§C

Power Dissipation

Dual-In-Line 700 mW
Small Outline 500 mW

Lead Temperature (Soldering, 10 seconds) 260

§

C

Operating V

CC

Range 3V to 15V

VCC(Max) 18V

DC Electrical Characteristics Min/Max limits apply across temperature range unless otherwise specified

Symbol Parameter Conditions Min Typ Max Units

CMOS TO CMOS

V

IN(1)

Logical ‘‘1’’ Input Voltage V

CC

e

5V 3.5 V

V

CC

e

10V 80 V

V

IN(0)

Logical ‘‘0’’ Input Voltage V

CC

e

5V 1.5 V

V

CC

e

10V 2.0 V

V

OUT(1)

Logical ‘‘1’’ Output Voltage V

CC

e

5V 4.5 V

V

CC

e

10V 9.0 V

V

OUT(0)

Logical ‘‘0’’ Output Voltage V

CC

e

5V 0.5 V

V

CC

e

10V 1.0 V

I

IN(1)

Logical ‘‘1’’ Input Current V

CC

e

15V 1.0 mA

I

IN(0)

Logical ‘‘0’’ Input Current V

CC

e

15V

b

1.0 mA

I

CC

Supply Current V

CC

e

15V 0.05 60 mA

CMOS/LPTTL INTERFACE

V

IN(1)

Logical ‘‘1’’ Input Voltage 54C, V

CC

e

4.5V
V

CC

b

1.5

74C, V

CC

e

4.75V

V

IN(0)

Logical ‘‘0’’ Input Voltage 54C, V

CC

e

4.75V

0.8 V

74C, V

CC

e

4.75V

V

OUT(1)

Logical ‘‘1’’ Output Voltage 54C, V

CC

e

4.5V, I

D

eb

360 mA

2.4 V

74C, V

CC

e

4.75V, I

D

eb

360 mA

V

OUT(0)

Logical ‘‘0’’ Output Voltage 54C, V

CC

e

4.5V, I

D

e

360 mA

0.4 V

74C, V

CC

e

4.75V, I

D

e

360 mA

OUTPUT DRIVE (See 54C/74C Family Characteristics Data Sheet)

I

SOURCE

Output Source Current V

CC

e

5V, V

IN(0)

e

0V

b

1.75 mA

T

A

e

25§C, V

OUT

e

0V

I

SOURCE

Output Source Current V

CC

e

10V, V

IN(0)

e

0V

b

8.0 mA

T

A

e

25§C, V

OUT

e

0V

I

SINK

Output Sink Current V

CC

e

5V, V

IN(1)

e

5V

1.75 mA

T

A

e

25§C, V

OUT

e

V

CC

I

SINK

Output Sink Current V

CC

e

10V, V

IN(1)

e

10V

8.0 mA

T

A

e

25§C, V

OUT

e

V

CC

Note 1: ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed. Except for ‘‘Operating Temperature Range’’
they are not meant to imply that the devices should be operated at these limits. The table of ‘‘Electrical Characteristics’’ provides conditions for actual device
operation.

2