NSC MM54C174J-883 Datasheet

TL/F/5899

MM54C174/MM74C174 Hex D Flip-Flop

February 1988

MM54C174/MM74C174 Hex D Flip-Flop

General Description

The MM54C174/MM74C174 hex D flip-flop is a monolithic
complementary MOS (CMOS) integrated circuit constructed
with N- and P-channel enhancement transistors. All have a
direct clear input. Information at the D inputs meeting the
setup time requirements is transferred to the Q outputs on
the positive-going edge of the clock pulse. Clear is indepen­dent of clock and accomplished by a low level at the clear
input. All inputs are protected by diodes to V

CC

and GND.

Features

Y

Wide supply voltage range 3.0V to 15V

Y

Guaranteed noise margin 1.0V

Y

High noise immunity 0.45 VCC(typ.)

Y

Low power TTL compatibility Fan out of 2

driving 74L

Logic and Connection Diagrams

TL/F/5899– 1

TL/F/5899– 2

TL/F/5899– 3

Dual-In-Line Package

TL/F/5899– 4

Top View

Order Number MM54C174 or MM74C174

Truth Table

Inputs Output

Clear Clock D Q

LXXL
H

u

HH

H

u

LL

HLXQ

C

1995 National Semiconductor Corporation RRD-B30M105/Printed in U. S. A.

Absolute Maximum Ratings (Note 1)

If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.

Voltage at Any Pin

b

0.3V to V

CC

a

0.3V

Operating Temperature Range

MM54C174

b

55§Ctoa125§C

MM74C174

b

40§Ctoa85§C

Storage Temperature Range

b

65§Ctoa150§C

Power Dissipation (PD)

Dual-In-Line 700 mW
Small Outline 500 mW

Operating V

CC

Range 3.0V to 15V

Absolute Maximum V

CC

18V

Lead Temperature (Soldering, 10 sec.) 260§C

DC Electrical Characteristics Min/Max limits apply across temperature range unless otherwise specified

Symbol Parameter Conditions Min Typ Max Units

CMOS TO CMOS

V

IN(1)

Logical ‘‘1’’ Input Voltage V

CC

e

5V 3.5 V

V

CC

e

10V 8.0 V

V

IN(0)

Logical ‘‘0’’ Input Voltage V

CC

e

5V 1.5 V

V

CC

e

10V 2.0 V

V

OUT(1)

Logical ‘‘1’’ Output Voltage V

CC

e

5V, I

O

eb

10 mA 4.5 V

V

CC

e

10V, I

O

eb

10 mA 9.0 V

V

OUT(0)

Logical ‘‘0’’ Output Voltage V

CC

e

5V, I

O

e

10 mA 0.5 V

V

CC

e

10V, I

O

e

10 mA 1.0 V

I

IN(1)

Logical ‘‘1’’ Input Current V

CC

e

15V, V

IN

e

15V 0.005 1.0 mA

I

IN(0)

Logical ‘‘0’’ Input Current V

CC

e

15V, V

IN

e

0V

b

1.0

b

0.005 mA

I

CC

Supply Current V

CC

e

15V 0.05 300 mA

CMOS/LPTTL INTERFACE

V

IN(1)

Logical ‘‘1’’ Input Voltage 54C, V

CC

e

4.5V V

CC

b

1.5 V

74C, V

CC

e

4.75V V

CC

b

1.5 V

V

IN(0)

Logical ‘‘0’’ Input Voltage 54C, V

CC

e

4.5V 0.8 V

74C, V

CC

e

4.75V 0.8 V

V

OUT(1)

Logical ‘‘1’’ Output Voltage 54C, V

CC

e

4.5V, I

O

eb

360 mA 2.4 V

74C, V

CC

e

4.75V, I

O

eb

360 mA 2.4 V

V

OUT(0)

Logical ‘‘0’’ Output Voltage 54C, V

CC

e

4.5V, I

O

e

360 mA 0.4 V

74C, V

CC

e

4.75V, I

O

e

360 mA 0.4 V

OUTPUT DRIVE (See 54C/74C Family Characteristics Data Sheet) (short circuit current)

I

SOURCE

Output Source Current V

CC

e

5V

b

1.75

b

3.3 mA

(P-Channel) T

A

e

25§C, V

OUT

e

0V

I

SOURCE

Output Source Current V

CC

e

10V

b

8.0

b

15 mA

(P-Channel) T

A

e

25§C, V

OUT

e

0V

I

SINK

Output Sink Current V

CC

e

5V

1.75 3.6 mA

(N-Channel) T

A

e

25§C, V

OUT

e

0V

I

SINK

Output Sink Current V

CC

e

5V

8.0 16 mA

(N-Channel) T

A

e

25§C, V

OUT

e

0V

Note 1: ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed. Except for ‘‘Operating Temperature Range’’
they are not meant to imply that the devices should be operated at these limits. The table of ‘‘Electrical Characteristics’’ provides conditions for actual device
operation.

2