NSC MF10CCN, MF10CCWM, MF10ACN Datasheet
MF10
Universal Monolithic Dual Switched Capacitor Filter
General Description
The MF10 consists of 2 independent and extremely easy to
use, general purpose CMOS active filter building blocks.
Each block, together with anexternal clock and 3 to 4 resistors, can produce various 2nd order functions. Each building
block has 3 output pins. One of the outputs can be configured to perform either an allpass, highpass or a notch function; the remaining 2 output pins perform lowpass and bandpass functions. The center frequency of the lowpass and
bandpass 2nd order functions can be either directly dependent on the clock frequency, or they can depend on both
clock frequency and external resistor ratios. The center frequency of the notch and allpass functions is directly dependent on the clock frequency, while the highpass center frequency depends on both resistor ratio and clock. Up to 4th
order functions can be performed by cascading the two 2nd
order building blocks of the MF10; higher than 4th order
functions can be obtained by cascading MF10 packages.
System Block Diagram
Any of the classical filter configurations (such as Butterworth, Bessel, Cauer and Chebyshev) can be formed.
For pin-compatible device with improved performance refer
to LMF100 datasheet.
Features
n Easy to use
n Clock to center frequency ratio accuracy
n Filter cutoff frequency stability directly dependent on
external clock quality
n Low sensitivity to external component variation
n Separate highpass (or notch or allpass), bandpass,
lowpass outputs
n f
x Q range up to 200 kHz
O
n Operation up to 30 kHz
n 20-pin 0.3" wide Dual-In-Line package
n 20-pin Surface Mount (SO) wide-body package
±
June 1999
%
0.6
MF10 Universal Monolithic Dual Switched Capacitor Filter
Package in 20 pin molded wide body surface mount and 20 pin molded DIP.
© 1999 National Semiconductor Corporation DS010399 www.national.com
DS010399-1
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage (V
Voltage at Any Pin V
Input Current at Any Pin (Note 2) 5 mA
Package Input Current (Note 2) 20 mA
Power Dissipation (Note 3) 500 mW
Storage Temperature 150˚C
+−V−
) 14V
V
+
+ 0.3V
−
− 0.3V
SO Package:
Vapor Phase (60 Sec.) 215˚C
Infrared (15 Sec.) 220˚C
See AN-450 “Surface Mounting Methods and Their Effect
on Product Reliability” (Appendix D) for other methods of
soldering surface mount devices.
Operating Ratings (Note 1)
Temperature Range T
MF10ACN, MF10CCN 0˚C ≤ TA≤ 70˚C
MF10CCWM 0˚C ≤ T
MIN
≤ TA≤ T
≤ 70˚C
A
ESD Susceptability (Note 11) 2000V
Soldering Information
N Package: 10 sec 260˚C
Electrical Characteristics
+
=
V
+5.00V and V
=
25˚C.
Symbol Parameter Conditions Typical Tested Design Units
+−V−
V
I
S
f
O
f
CLK
f
CLK/fO
f
CLK/fO
H
OLP
V
OS1
V
OS2
V
OS3
V
OS2
V
OS3
V
OUT
GBW Op Amp Gain BW Product 2.5 MHz
SR Op Amp Slew Rate 7 V/µs
−
=
−5.00V unless otherwise specified. Boldface limits apply for T
Supply Voltage Min 9 V
Maximum Supply Clock Applied to Pins 10 & 11 8 12 12 mA
Current No Input Signal
Center Frequency Min fOxQ<200 kHz 0.1 0.2 Hz
Range Max 30 20 kHz
Clock Frequency Min 5.0 10 Hz
Range Max 1.5 1.0 MHz
50:1 Clock to
Center Frequency
Ratio Deviation
100:1 Clock to
Center Frequency
Ratio Deviation
Clock Feedthrough Q=10
Q Error (MAX) Q=10 V
(Note 4) Mode 1 f
DC Lowpass Gain Mode 1 R1=R2=10k 0
DC Offset Voltage (Note 5)
DC Offset Voltage Min V
(Note 5) Max (f
DC Offset Voltage Min V
(Note 5) Max (f
DC Offset Voltage V
(Note 5) (f
DC Offset Voltage V
(Note 5) (f
Minimum Output BP, LP Pins R
Voltage Swing N/AP/HP Pin R
Max 14 V
=
MF10C Q=10
MF10C Q=10
Min V
Max (f
Mode 1
Mode 1
Mode 1
pin12
CLK/fO
pin12
CLK/fO
pin12
CLK/fO
pin12
CLK/fO
V
pin12
(f
CLK/fO
pin12
CLK/fO
=
L
=
L
=
+5V S
=
50) −85 −85
=
+5V S
=
50)
=
+5V All Modes −70 −100 −100 mV
=
50) −20 −20
=
0V S
=
100)
=
0V S
=
100)
=
0V All Modes −140 mV
=
100)
5k
3.5k
5V
V
pin12
=
f
250 KHz
CLK
=
0V
V
pin12
=
f
500 kHz
CLK
=
5V
pin12
=
250 kHz
CLK
=
V
0V
pin12
=
f
500 kHz
CLK
+
=
V
A/B
−
=
V
A/B
+
=
V
A/B
−
=
V
A/B
to T
MIN
(Note 8) Limit Limit
±
0.2
±
0.2
10 mV
±
2
±
2
±
5.0
−150 −185 −185 mV
−70 mV
−300 mV
−140 mV
±
4.25
±
4.25
; all other limits T
MAX
MF10ACN, MF10CCN,
MF10CCWM
(Note 9) (Note 10)
±
1.5
±
1.5
±
6
±
6
±
0.2
±
20
±
3.8
±
3.8
=
A
±
1.5
±
1.5
±
6
±
6
±
0.2 dB
±
20 mV
±
3.8 V
±
3.8 V
T
MAX
J
%
%
%
%
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Electrical Characteristics (Continued)
+
=
V
+5.00V and V
=
25˚C.
Symbol Parameter Conditions Typical Tested Design Units
I
SC
−
Dynamic
Range(Note 6)
Maximum Output
Short
Circuit Current
(Note 7)
=
−5.00V unless otherwise specified. Boldface limits apply for T
=
V
+5V
pin12
=
(f
50)
CLK/fO
=
V
0V
pin12
=
(f
100)
Source 20 mA
Sink 3.0 mA
CLK/fO
to T
MIN
(Note 8) Limit Limit
83 dB
80 dB
; all other limits T
MAX
MF10ACN, MF10CCN,
MF10CCWM
(Note 9) (Note 10)
A
=
T
J
Logic Input Characteristics
=
Boldface limits apply for T
MIN
to T
MAX
; all other limits T
Parameter Conditions Typical Tested Design Units
+
−
=
=
=
(T
+5V, V
=
0V −3.0 −3.0 V
LSh
+
LSh
+
LSh
+
LSh
JMAX−TA
−
=
+10V, V
=
+5V +2.0 +2.0 V
−
=
=
+5V, V
=
0V +0.8 +0.8 V
−
=
+10V, V
=
+5V +0.8 +0.8 V
)/θJAor the number given in the Absolute Maximum Ratings, whichever is lower. For this device,
CMOS Clock Min Logical “1” V
Input Voltage Max Logical “0” V
Min Logical “1” V
Max Logical “0” V
TTL Clock Min Logical “1” V
Input Voltage Max Logical “0” V
Min Logical “1” V
Max Logical “0” V
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications do not apply when operating
the device beyond its specified operating conditions.
Note 2: When the input voltage (V
to 5 mA or less. The 20 mA package input current limits the number of pins that can exceed the power supply boundaries witha5mAcurrent limit to four.
Note 3: The maximum power dissipation must be derated at elevated temperatures and is dictated by T
allowable power dissipation at any temperature is P
=
T
125˚C, and the typical junction-to-ambient thermal resistance of the MF10ACN/CCN when board mounted is 55˚C/W. For the MF10AJ/CCJ, this number in-
JMAX
creases to 95˚C/W and for the MF10ACWM/CCWM this number is 66˚C/W.
Note 4: The accuracy of the Q value is a function of the center frequency (f
istics”.
Note 5: V
Note 6: For
the MF10 with a 50:1 CLK ratio and 280 µV rms for the MF10 with a 100:1 CLK ratio.
Note 7: The short circuit source current is measured by forcing the output that is being tested to its maximum positive voltage swing and then shorting that output
to the negative supply. The short circuit sink current is measured by forcing the output that is being tested to its maximum negative voltage swing and then shorting
that output to the positive supply. These are the worst case conditions.
Note 8: Typicals are at 25˚C and represent most likely parametric norm.
Note 9: Tested limits are guaranteed to National’s AOQL (Average Outgoing Quality Level).
Note 10: Design limits are guaranteed but not 100%tested. These limits are not used to calculate outgoing quality levels.
Note 11: Human body model, 100 pF discharged through a 1.5 kΩ resistor.
, and V
OS1,VOS2
±
5V supplies the dynamic range is referenced to 2.82V rms (4V peak) where the wideband noise over a 20 kHz bandwidth is typically 200 µV rms for
) at any pin exceeds the power supply rails (V
IN
D
refer to the internal offsets as discussed in the Applications Information Section 3.4.
OS3
=
T
25˚C
A
J
MF10ACN, MF10CCN,
MF10CCWM
(Note 8) Limit Limit
(Note 9) (Note 10)
−5V, +3.0 +3.0 V
=
0V, +8.0 +8.0 V
−5V, +2.0 +2.0 V
=
0V, +2.0 +2.0 V
<
IN
). This is illustrated in the curves under the heading “Typical Performance Character-
O
V−or V
>
V+) the absolute value of current at that pin should be limited
IN
, θJA, and the ambient temperature, TA. The maximum
JMAX
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Typical Performance Characteristics
Power Supply Current
vs Power Supply Voltage
Negative Output
Swing vs Temperature
Positive Output Voltage Swing
vs Load Resistance
(N/AP/HP Output)
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Positive Output Swing
vs Temperature
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Negative Output Voltage
Swing vs Load
Resistance (N/AP/HP Output)
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Crosstalk vs Clock
Frequency
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Q Deviation vs
Temperature
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Q Deviation vs
Temperature
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Q Deviation vs
Clock Frequency
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Typical Performance Characteristics (Continued)
Q Deviation vs
Clock Frequency
f
Deviation
CLK/fO
vs Clock Frequency
f
CLK/fO
vs Temperature
DS010399-43
f
CLK/fO
vs Clock Frequency
Deviation
Deviation
DS010399-44
f
Deviation
CLK/fO
vs Temperature
Deviation of f
vs Nominal Q
DS010399-45
CLK/fO
Deviation of f
vs Nominal Q
CLK/fO
DS010399-46
DS010399-49
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Pin Descriptions
LP(1,20), BP(2,19),
N/AP/HP(3,18)
INV(4,17) The inverting input of the summing
S1(5,16) S1 is a signal input pin used in the all-
S
(6) This pin activates a switch that con-
A/B
+
V
V
+
(7),V
(8) Analog positive supply and digital posi-
A
D
−
−
(14), V
A
D
LSh(9) Level shift pin; it accommodates vari-
CLKA(10),
CLKB(11)
The second order lowpass, bandpass
and notch/allpass/highpass outputs.
These outputs can typically sink 1.5
mAand source 3 mA. Each output typically swings to within 1V of each supply.
op-amp of each filter. These are high
impedance inputs, but the
non-inverting input is internally tied to
AGND, making INV
like summing junctions (low imped-
and INVBbehave
A
ance, current inputs).
pass filter configurations (see modes 4
and 5). The pin should be driven with a
source impedance of less than 1 kΩ.If
S1 is not driven with a signal it should
be tied to AGND (mid-supply).
nects one of the inputs of each filter’s
second summer to either AGND (S
tied to V−) or to the lowpass (LP) output (S
flexibility needed for configuring the fil-
tied to V+). This offers the
A/B
A/B
ter in its various modes of operation.
tive supply. These pins are internally
connected through the IC substrate
and therefore V
derived from the same power supply
A
+
and V
+
should be
D
source. They have been brought out
separately so they can be bypassed by
separate capacitors, if desired. They
can be externally tied together and bypassed by a single capacitor.
(13) Analog and digital negative supplies.
The same comments as for V
+
V
apply here.
D
+
and
A
ous clock levels with dual or single
supply operation. With dual
±
5V supplies, the MF10 can be driven with
CMOS clock levels (
±
5V) and the LSh
pin should be tied to the system
ground. If the same supplies as above
are used but only TTL clock levels, derived from 0V to +5V supply, are available, the LSh pin should be tied to the
system ground. For single supply operation (0V and +10V) the V
−
V
pins should be connected to the
D
system ground, the AGND pin should
A
be biased at +5V and the LSh pin
should also be tied to the system
ground for TTL clock levels. LSh
should be biased at +5V for CMOS
clock levels in 10V single-supply applications.
Clock inputs for each switched capacitor filter building block. They should
both be of the same level (TTL or
CMOS). The level shift (LSh) pin description discusses how to accommo-
date their levels. The duty cycle of the
clock should be close to 50%especially when clock frequencies above
200 kHz are used. This allows the
maximum time for the internal
op-amps to settle, which yields optimum filter operation.
50/100/CL(12) By tying this pin high a 50:1
clock-to-filter-center-frequency ratio is
obtained. Tying this pin at mid-supplies
(i.e. analog ground with dual supplies)
allows the filter to operate at a 100:1
clock-to-center-frequency ratio. When
the pin is tied low (i.e., negative supply
with dual supplies), a simple current
limiting circuit is triggered to limit the
overall supply current down to about
2.5 mA. The filtering action is then
aborted.
AGND(15) This is the analog ground pin. This pin
should be connected to the system
ground for dual supply operation or biased to mid-supply for single supply
operation. For a further discussion of
mid-supply biasing techniques see the
Applications Information (Section 3.2).
For optimum filter performance a
“clean” ground must be provided.
1.0 Definition of Terms
f
: the frequency of the external clock signal applied to pin
CLK
10 or 11.
f
: center frequency of the second order function complex
O
pole pair. f
MF10, and is the frequency of maximum bandpass gain.
(
Figure 1
f
notch
notch outputs.
f
: the center frequency of the second order complex zero
z
pair, if any. If f
observed as the frequency of a notch at the allpass output.
(
Figure 10
Q: “quality factor” of the 2nd order filter. Q is measured at the
bandpass outputs of the MF10 and is equal to f
the −3 dB bandwidth of the 2nd order bandpass filter (
1
). The value of Q determines the shape of the 2nd order fil-
ter responses as shown in
: the quality factor of the second order complex zero pair,
Q
Z
if any. Q
−
written:
,
where Q
H
OBP
H
OLP
(
Figure 2
H
OHP
(
Figure 3
is measured at the bandpass outputs of the
O
)
: the frequency of minimum (ideally zero) gain at the
is different from fOand if QZis high, it can be
z
)
Figure 6
.
is related to the allpass characteristic, which is
Z
=
Q for an all-pass response.
Z
: the gain (in V/V) of the bandpass output at f=fO.
: the gain (in V/V) of the lowpass output as f→0Hz
).
: the gain (in V/V) of the highpass output as f→f
).
divided by
O
Figure
CLK
/2
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1.0 Definition of Terms (Continued)
H
: the gain (in V/V) of the notch output as f→0 Hz and as
ON
f→f
/2, when the notch filter has equal gain above and
CLK
below the center frequency (
low-frequency gain differs from the high-frequency gain, as
in modes 2 and 3a (
Figure 11
ties below are used in place of H
and
Figure 4
Figure 8
.
ON
). When the
), the two quanti-
H
: the gain (in V/V) of the notch output as f→0 Hz.
ON1
: the gain (in V/V) of the notch output as f→f
H
ON2
CLK
/2.
(a)
(a)
DS010399-5
DS010399-7
(a)
DS010399-6
(b)
FIGURE 1. 2nd-Order Bandpass Response
DS010399-8
(b)
FIGURE 2. 2nd-Order Low-Pass Response
DS010399-9
DS010399-56
DS010399-57
DS010399-10
(b)
DS010399-58
FIGURE 3. 2nd-Order High-Pass Response
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