The LV8573A is intended for use in microprocessor based
systems where information is required for multi-tasking, data
logging or general time of day/date information. This device
is implemented in low voltage silicon gate microCMOS technology to provide low standby power in battery back-up environments. The circuit’s architecture is such that it looks
like a contiguous block of memory or I/O ports organized as
one block of 32 bytes. This includes the Control Registers,
the Clock Counters, the Alarm Compare RAM, and the Time
Save RAM.
Time and date are maintained from 1/100 of a second to
year and leap year in a BCD format, 12 or 24 hour modes.
Day of week and day of month counters are provided. Time
is controlled by an on-chip crystal oscillator requiring only
the addition of the 32.768 kHz crystal and two capacitors.
Power failure logic and control functions have been integrated on chip. This logic is used by the RTC to issue a power
fail interrupt, and lock out the mP interface. The time power
fails may be logged into RAM automatically when V
VCC. Additionally, two supply pins are provided. When V
BB
BB
Block Diagram
l
VCC, internal circuitry will automatically switch from the
main supply to the battery supply.
The LV8573A’s interrupt structure provides three basic
types of interrupts: Periodic, Alarm/Compare, and Power
Fail. Interrupt mask and status registers enable the masking
and easy determination of each interrupt.
Features
Y
3.3Vg10% supply
Y
Full function real time clock/calendar
Ð 12/24 hour mode timekeeping
Ð Day of week counter
Ð Parallel resonant oscillator
Y
Power fail features
Ð Internal power supply switch to external battery
Ð Power Supply Bus glitch protection
Ð Automatic log of time into RAM at power failure
Y
On-chip interrupt structure
l
Ð Periodic, alarm, and power fail interrupts
FIGURE 1
TRI-STATEÉis a registered trademark of National Semiconductor Corporation.
C
1995 National Semiconductor CorporationRRD-B30M105/Printed in U. S. A.
TL/F/11418
TL/F/11418– 1
Absolute Maximum Ratings (Notes1&2)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage (V
CC
)
DC Input Voltage (VIN)
DC Output Voltage (V
OUT
)
Storage Temperature Range
Power Dissipation (PD)500 mW
Lead Temperature (Soldering, 10 sec.)260§C
b
0.5V toa7.0V
b
0.5V to V
b
0.5V to V
b
65§Ctoa150§C
CC
CC
a
0.5V
a
0.5V
Operation Conditions
Supply Voltage (V
) (Note 3)3.03.6V
CC
Supply Voltage (VBB) (Note 3)2.2V
DC Input or Output Voltage
(V
IN,VOUT
)
Operation Temperature (T
Electr-Static Discharge Rating1kV
Typical Values
i
DIPBoard61§C/W
JA
Socket67
iJAPLCC Board80§C/W
Socket88
MinMaxUnit
0.0V
b
)
A
40
CC
a
§
§
b
0.4V
CC
85
C/W
C/W
V
C
§
DC Electrical Characteristics
V
CC
e
3.3Vg10%, V
BB
e
2.5V, V
PFAIL
l
VIH,C
e
100 pF unless otherwise specified
L
SymbolParameterConditionsMinMaxUnits
V
IH
V
IL
V
OH
V
OL
I
IN
I
OZ
I
LKG
I
CC
I
CC
I
BB
I
BLK
Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur.
Note 2: Unless otherwise specified all voltages are referenced to ground.
Note 3: In battery backed mode, V
Note 4: This parameter (V
Note 5: This specification tests I
Note 6: This specification tests I
Note 7: OSC IN is driven by a signal generator. Contents of the Test Register
High Level Input VoltageAny Inputs Except OSC IN,2.0V
(Note 4)OSC IN with External ClockV
Low Level Input VoltageAll Inputs Except OSC IN
OSC IN with External Clock
High Level Output VoltageI
(Excluding OSC OUT, INTR)I
Low Level Output VoltageI
(Excluding OSC OUT)I
Input Current (Except OSC IN)V
Output TRI-STATEÉCurrentV
Output High Leakage CurrentV
MFO, INTR PinsOutputs Open Drain
Standby Mode BatteryV
Supply CurrentOSC OUT
(Note 7)other pins
Battery Leakage2.2VsV
s
b
V
Single Supply Mode: Data retention voltage is 2.2V min.
In single Supply Mode (Power connected to V
BB
) is not tested on all pins at the same time.
IH
with all power fail circuitry disabled, by setting D7 of Interrupt Control Register 1 to 0.
CC
with all power fail circuitry enabled, by setting D7 of Interrupt Control Register 1 to 1.
CC
0.4V.
CC
pin) 3.0VsV
CC
eb
20 mAV
OUT
eb
2.0 mA2.4V
OUT
eb
20 mA0.2V
OUT
e
2.0 mA0.3V
OUT
e
VCCor GND
IN
e
VCCor GND
OUT
e
VCCor GND
OUT
e
32.768 kHz
OSC
e
VCCor GND (Note 5)220mA
IN
e
V
VCCor GND (Note 6)700mA
IN
e
V
VIHor VIL(Note 6)5mA
IN
e
GND
BB
e
VCCor GND30mA
IN
e
32.768 kHz
OSC
e
GND
CC
e
open circuit,
e
GND
e
F
32.768 kHz
OSC
s
2.6V
BB
other pins at GND
e
V
GND, V
CC
e
V
3.6V, V
CC
s
CC
e
2.6V0.8mA
BB
e
2.2V
BB
3.6V.
e
00(H) and the MFO pin is not configured as buffered oscillator out.
b
0.2V
BB
b
0.30.8V
b
0.30.2V
b
0.2V
CC
b
0.8mA
a
0.3V
CC
g
0.7mA
g
1mA
g
1mA
8mA
2
AC Electrical Characteristics
V
CC
e
3.3Vg10%, V
BB
e
2.5V, V
PFAIL
l
VIH,C
e
100 pF unless otherwise specified
L
SymbolParameterMinMaxUnits
READ TIMING
t
AR
t
RW
t
CD
t
RAH
t
RD
t
DZ
t
RCH
t
DS
Address Valid Prior to Read Strobe10ns
Read Strobe Width (Note 8)100ns
Chip Select to Data Valid Time100ns
Address Hold after Read (Note 9)2ns
Read Strobe to Valid Data90ns
Read or Chip Select to TRI-STATE80ns
Chip Select Hold after Read Strobe (Note 9)0ns
Minimum Inactive Time between Read or Write Accesses70ns
WRITE TIMING
t
AW
t
WAH
t
CW
t
WW
t
DW
t
WDH
t
WCH
Address Valid before Write Strobe10ns
Address Hold after Write Strobe (Note 9)2ns
Chip Select to End of Write Strobe110ns
Write Strobe Width (Note 10)100ns
Data Valid to End of Write Strobe70ns
Data Hold after Write Strobe (Note 9)2ns
Chip Select Hold after Write Strobe (Note 9)0ns
INTERRUPT TIMING
t
ROLL
Note 8: Read Strobe width as used in the read timing table is defined as the period when both chip select and read inputs are low. Hence read commences when
both signals are low and terminates when either signal returns high.
Note 9: Hold time is guaranteed by design but not production tested. This limit is not used to calculate outgoing quality levels.
Note 10: Write Strobe width as used in the write timing table is defined as the period when both chip select and write inputs are low. Hence write commences when
both signals are low and terminates when either signal returns high.
Clock rollover to INTR out typically 20 ms
AC Test Conditions
Input Pulse LevelsGND to 3.0V
Input Rise and Fall Times6 ns (10% –90%)
Input and Output
Reference Levels
TRI-STATE ReferenceActive High
Levels (Note 12)Active Low
S1
S1
Symbol
C
IN
C
OUT
e
100 pF, includes jig and scope capacitance.
L
e
VCCfor active low to high impedance measurements.
e
GND for active high to high impedance measurements.
e
open for all other timing measurements.
e
25§C, fe1 MHz)
A
Parameter
(Note 13)
Input Capacitance5pF
Output Capacitance7pF
Note 11: C
Note 12: S1
Capacitance (T
Note 13: This parameter is not 100% tested.
Note 14: Output rise and fall times 25 ns max (10%– 90%) with 100 pF load.
1.3V
a
0.5V
b
0.5V
TypUnits
TL/F/11418– 2
3
Timing Waveforms
Read Timing Diagram
TL/F/11418– 3
Write Timing Diagram
Pin Description
CS,RD,WR(Inputs): These pins interface to mP control
lines. The CS
write operations. Read and Write pins are also active low
and enable reading or writing to the RTC. All three pins are
disabled when power failure is detected. However, if a read
or write is in progress at this time, it will be allowed to complete its cycle.
A0–A4 (Inputs): These 5 pins are for register selection.
They individually control which location is to be accessed.
These inputs are disabled when power failure is detected.
OSC IN (Input): OSC OUT (Output): These two pins are
used to connect the crystal to the internal parallel resonant
oscillator. The oscillator is always running when power is
applied to V
MFO (Output): The multi-function output can be used as a
second interrupt (Power fail) output for interrupting the mP.
This pin can also provide an output for the oscillator. The
MFO output is configured as push-pull, active high for normal or single power supply operation and as an open drain
during standby mode (V
mode and a pull-up resistor is attached, it should be connected to a voltage no greater than V
INTR (Output): The interrupt output is used to interrupt the
processor when a timing event or power fail has occurred
and the respective interrupt has been enabled. The INTR
pin is an active low enable for the read and
and VCC.
BB
l
VCC). If in battery backed
BB
.
BB
TL/F/11418– 4
output is permanently configured active low, open drain. If in
battery backed mode and a pull-up resistor is attached, it
should be connected to a voltage no greater than V
D0–D7 (Input/Output): These 8 bidirectional pins connect
to the host mP’s data bus and are used to read from and
write to the RTC. When the PFAIL
pin goes low and a write
is not in progress, these pins are at TRI-STATE.
PFAIL
(Input): In battery backed mode, this pin can have a
digital signal applied to it via some external power detection
logic. When PFAIL
e
logic 0 the RTC goes into a lockout
mode, in a minimum of 30 ms or a maximum of 63 ms unless
lockout delay is programmed. In the single power supply
mode, this pin is not useable as an input and should be tied
to V
. Refer to section on Power Fail Functional Descrip-
CC
tion.
V
(Battery Power Pin): This pin is connected to a back-
BB
up power supply. This power supply is switched to the internal circuitry when the V
ing this pin eliminates the need for external logic to switch in
becomes lower than VBB. Utiliz-
CC
and out the back-up power supply. If this feature is not to be
used then this pin must be tied to ground, the RTC programmed for single power supply only, and power applied to
the V
pin.
CC
VCC: This is the main system power pin.
GND: This is the common ground power pin for both V
and VCC.
4
BB
.
BB
Connection Diagrams
In-Line Packages
Plastic Chip Carrier
Top View
TL/F/11418– 5
DIP: Order Number LV8573AN
See NS Package Number N24C
SOIC: Order Number LV8573AM
See NS Package Number M24B
Functional Description
The LV8573A contains a fast access real time clock, interrupt control logic, and power fail detect logic. All functions of
the RTC are controlled by a set of seven registers. A simplified block diagram that shows the major functional blocks is
given in
Figure 1
.
The blocks are described in the following sections:
1. Real Time Clock
2. Oscillator Prescaler
3. Interrupt Logic
4. Power Failure Logic
5. Additional Supply Management
The memory map of the RTC is shown in the memory addressing table
Register is used to select either control register block.
INITIAL POWER-ON of BOTH V
VBBand VCCmay be applied in any sequence. In order for
the power fail circuitry to function correctly, whenever power
is off, the V
maximum of 1 MX. The user should be aware that the control registers will contain random data. The user should ensure that the RTC is not in test mode (see register descriptions).
REAL TIME CLOCK FUNCTIONAL DESCRIPTION
As shown in
which count from 1/100 of a second to years. Each counter
counts in BCD and is synchronously clocked. The count sequence of the individual byte counters within the clock is
shown later in Table VII. Note that the day of week, day of
month, and month counters all roll over to 1. The hours
counter in 12 hour mode rolls over to 1 and the AM/PM bit
toggles when the hours rolls over to 12 (AM
The AM/PM bit is bit D7 in the hours counter.
All other counters roll over to 0. Upon initial application of
power the counters will contain random information.
(Figure 2).
pin must see a path to ground through a
CC
Figure 2
A control bit in the Main Status
and V
BB
CC
, the clock has 8 bytes of counters,
e
0, PMe1).
Top View
TL/F/11418– 6
Order Number LV8573AV
See NS Package Number V28A
TL/F/11418– 7
FIGURE 2. LV8573A Internal Memory Map
5
Functional Description (Continued)
READING THE CLOCK: VALIDATED READ
Since clocking of the counter occurs asynchronously to
reading of the counter, it is possible to read the counter
while it is being incremented (rollover). This may result in an
incorrect time reading. Thus to ensure a correct reading of
the entire contents of the clock (or that part of interest), it
must be read without a clock rollover occurring. In general
this can be done by checking a rollover bit. On this chip the
periodic interrupt status bits can serve this function. The
following program steps can be used to accomplish this.
1. Initialize program for reading clock.
2. Dummy read of periodic status bit to clear it.
3. Read counter bytes and store.
4. Read rollover bit, and test it.
5. If rollover occured go to 3.
6. If no rollover, done.
To detect the rollover, individual periodic status bits can be
polled. The periodic bit chosen should be equal to the highest frequency counter register to be read. That is if only
SECONDS through HOURS counters are read, then the
SECONDS periodic bit should be used.
READING THE CLOCK: INTERRUPT DRIVEN
Enabling the periodic interrupt mask bits cause interrupts
just as the clock rolls over. Enabling the desired update rate
and providing an interrupt service routine that executes in
less than 10 ms enables clock reading without checking for
a rollover.
READING THE CLOCK: LATCHED READ
Another method to read the clock that does not require
checking the rollover bit is to write a one into the Time Save
Enable bit (D7) of the Time Save Control Register, and then
to write a zero. Writing a one into this bit will enable the
clock contents to be duplicated in the Time Save RAM.
Changing the bit from a one to a zero will freeze and store
the contents of the clock in Time Save RAM. The time then
can be read without concern for clock rollover, since internal logic takes care of synchronization of the clock. Because only the bits used by the clock counters will be
latched, the Time Save RAM should be cleared prior to use
to ensure that random data stored in the unused bits do not
confuse the host microprocessor. This bit can also provide
time save at power failure, see the Additional Supply Management Functions section. With the Time Save Enable bit
at a logical 0, the Time Save RAM may be used as RAM if
the latched read function is not necessary.
INITIALIZING AND WRITING TO THE
CALENDAR-CLOCK
Upon initial application of power to the TCP or when making
time corrections, the time must be written into the clock. To
correctly write the time to the counters, the clock would
normally be stopped by writing the Start/Stop
Time Mode Register to a zero. This stops the clock from
counting and disables the carry circuitry. When initializing
the clock’s Real Time Mode Register, it is recommended
that first the various mode bits be written while maintaining
the Start/Stop
second time with the Start/Stop
bit reset, and then writing to the register a
bit set.
bit in the Real
The above method is useful when the entire clock is being
corrected. If one location is being updated the clock need
not be stopped since this will reset the prescaler, and time
will be lost. An ideal example of this is correcting the hours
for daylight savings time. To write to the clock ‘‘on the fly’’
the best method is to wait for the 1/100 of a second periodic interrupt. Then wait an additional 16 ms, and then write
the data to the clock.
PRESCALER/OSCILLATOR FUNCTIONAL
DESCRIPTION
Feeding the counter chain is a programmable prescaler
which divides the crystal oscillator frequency to 32 kHz and
further to 100 Hz for the counter chain (see
FIGURE 3. Programmable Clock Prescaler Block
In addition to the inverter, the oscillator feedback bias resistor is included on chip, as shown in
input may be driven from an external source if desired. Refer to test mode application note for details. The oscillator
stability is enhanced through the use of an on chip regulated
power supply.
The typical range of trimmer capacitor (as shown in Oscillator Circuit Diagram
the oscillator input pin is suggested only to allow accurate
tuning of the oscillator. This range is based on a typical
printed circuit board layout and may have to be changed
depending on the parasitic capacitance of the printed circuit
board or fixture being used. In all cases, the load capaci-tance specified by the crystal manufacturer (nominal value
11 pF for the 32.768 crystal) is what determines proper oscillation. This load capcitance is the series combination of
capacitance on each side of the crystal (with respect to
ground).
Figure 4
, and in the typical application) at
FIGURE 4. Oscillator Circuit Diagram
Figure 4
Figure 3
).
TL/F/11418– 8
. The oscillator
TL/F/11418– 9
6
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