NSC LMX3162VBH Datasheet
LMX3162
Single Chip Radio Transceiver
LMX3162 Single Chip Radio Transceiver
PRELIMINARY
March 2000
General Description
The LMX3162 Single Chip Radio Transceiverisamonolithic,
integrated radio transceiver optimized for use in ISM 2.45
GHz wireless systems. It is fabricated using National’s ABiC
V BiCMOS process (f
The LMX3162 contains phase locked loop (PLL), transmit
and receive functions. The 1.3 GHz PLL is shared between
transmit and receive sections. The transmitter includes a frequency doubler, and a high frequency buffer. The receiver
consists of a 2.5 GHz low noise mixer, an intermediate frequency (IF) amplifier, a high gain limiting amplifier, a frequency discriminator, a received signal strength indicator
(RSSI), and an analog DC compensation loop. The PLL,
doubler, and buffers can be used to implement open loop
modulation along with an external VCO and loop filter. The
circuit features on-chip voltage regulation to allow supply
voltages ranging from 3.0V to 5.5V. Two additional voltage
regulators provide a stable supply source to external discrete stages in the Tx and Rx chains.
The IF amplifier, high gain limiting amplifier, and discriminator are optimized for 110 MHz operation, with a total IF gain
of 85 dB. The single conversion receiver architecture provides a low cost, high performance solution for communications systems. The RSSI output may be used for channel
quality monitoring.
= 18 GHz).
T
Block Diagram
The Single Chip Radio Transceiver is available in a 48-pin
7mm X 7mm X 1.4mm PQFP surface mount plastic package.
Features
n Single chip solution for ISM 2.45 GHz RF transceiver
n System RF sensitivity to −93 dBm; RSSI sensitivity to
−100 dBm
n Two regulated voltage outputs for discrete amplifiers
n High gain (85 dB) intermediate frequency strip
n Allows unregulated 3.0V–5.5V supply voltage
n Power down mode for increased current savings
n System noise figure 6.5 dB (typ)
Applications
n ISM 2.45 GHz frequency band wireless systems
n Personal wireless communications (PCS/PCN)
n Wireless local area networks (WLANs)
n Other wireless communications systems
DS100929-1
MICROWIRE™is a trademark of National Semiconductor Corporation.
®
TRI-STATE
© 2000 National Semiconductor Corporation DS100929 www.national.com
is a registered trademark of National Semiconductor Corporation.
LMX3162 Connection Diagram
LMX3162
DS100929-2
Top View
Order Number LMX3162VBH or LMX3162VBHX
See NS Package Number VBH48A
Pin Descriptions
Pin No. Pin Name I/O Description
1V
2 MIXER
CC
OUT
3VCC— Power supply for mixer section.
4 GND — Ground.
5RF
IN
— Power supply for CMOS section of PLL and
ESD bussing.
O IF output from the mixer.
I RF input to the mixer.
6 GND — Ground.
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Pin Descriptions (Continued)
Pin No. Pin Name I/O Description
7TxV
REG
8VCC— Power supply for analog sections of PLL and
9 GND — Ground.
10 Tx
OUT
11 GND — Ground.
12 V
CC
13 GND — Ground.
14 GND — Ground.
15 f
IN
— Regulated power supply for external PA gain
stage.
doubler.
O Frequency doubler output.
— Power supply for analog sections of PLL and
doubler.
I RF Input to PLL and frequency doubler.
LMX3162
16 CE I Chip Enable. Pulling LOW powers down entire
chip. Taking CE HIGH powers up the
appropriate functional blocks depending on the
state of bits F6, F7, F11, and F12 programmed
in F-latch. It is necessary to initialize the internal
registers once, after the power up reset. The
registers’ contents are kept even in power-down
condition.
17 V
18 D
P
o
— Power supply for charge pump.
O Charge pump output. For connection to a loop
filter for driving the input of an external VCO.
19 V
CC
— Power supply for CMOS section of PLL and
ESD bussing.
20 GND — Ground.
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Pin Descriptions (Continued)
Pin No. Pin Name I/O Description
LMX3162
21 OUT 0 O Programmable CMOS output. Refer to Function
Register Programming Description section for
details.
22 Rx PD/OUT 1 I/O Receiver power down control input or
programmable CMOS output. Refer to Function
Register Programming Description section for
details.
23 Tx PD/OUT 2 I/O Transmitter power down control input or
programmable CMOS output. Refer to Function
Register Programming Description section for
details.
24 PLL PD I PLL power down control input. LOW for PLL
normal operations, and HIGH for PLL power
saving.
25 CLOCK I MICROWIRE™clock input. High impedance
CMOS input with Schmitt Trigger.
26 DATA I MICROWIRE data input. High impedance
CMOS input with Schmitt Trigger.
27 LE I MICROWIRE load enable input. High
impedance CMOS input with Schmitt Trigger.
28 OSC
IN
I Oscillator input. High impedance CMOS input
with feedback.
29 S FIELD I DC compensation circuit enable. While LOW,
the DC compensation circuit is enabled and the
threshold is updated through the DC
compensation loop. While HIGH, the switch is
opened, and the comparator threshold is held
by the external capacitor.
30 RSSI
31 THRESH O Threshold level to external comparator.
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OUT
O Received signal strength indicator (RSSI)
output.
Pin Descriptions (Continued)
Pin No. Pin Name I/O Description
32 DC COMP
IN
I Input to DC compensation circuit.
LMX3162
33 DISC
OUT
O Demodulated output of discriminator.
34 GND — Ground.
35 V
CC
36 QUAD
37 V
CC
IN
— Power supply for the discriminator circuit.
I Quadrature input for tank circuit.
— Power supply for limiter output stage.
38 GND — Ground.
39 V
CC
— Power supply for limiter gain stages.
40 GND — Ground.
41 V
42 LIM
CC
IN
— Power supply for IF amplifier gain stages.
I IF input to the limiter.
43 GND — Ground.
44 IF
45 V
OUT
CC
O IF output from IF amplifier.
— Power supply for IF amplifier output.
46 GND — Ground.
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Pin Descriptions (Continued)
Pin No. Pin Name I/O Description
LMX3162
47 IF
IN
I IF input to IF amplifier.
48 Rx V
REG
— Regulated power supply for external LNA
stages.
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