TL/F/6398
54LS164/DM54LS164/DM74LS164 8-Bit Serial In/Parallel Out Shift Registers
June 1989
54LS164/DM54LS164/DM74LS164
8-Bit Serial In/Parallel Out Shift Registers
General Description
These 8-bit shift registers feature gated serial inputs and an
asynchronous clear. A low logic level at either input inhibits
entry of the new data, and resets the first flip-flop to the low
level at the next clock pulse, thus providing complete control over incoming data. A high logic level on either input
enables the other input, which will then determine the state
of the first flip-flop. Data at the serial inputs may be changed
while the clock is high or low, but only information meeting
the setup and hold time requirements will be entered. Clocking occurs on the low-to-high level transition of the clock
input. All inputs are diode-clamped to minimize transmission-line effects.
Features
Y
Gated (enable/disable) serial inputs
Y
Fully buffered clock and serial inputs
Y
Asynchronous clear
Y
Typical clock frequency 36 MHz
Y
Typical power dissipation 80 mW
Y
Alternate Military/Aerospace device (54LS164) is available. Contact a National Semiconductor Sales Office/
Distributor for specifications.
Connection Diagram
Dual-In-Line Package
TL/F/6398– 1
Order Number 54LS164DMQB, 54LS164FMQB,
54LS164LMQB, DM54LS164J, DM54LS164W,
DM74LS164M or DM74LS164N
See NS Package Number E20A,
J14A, M14A, N14A or W14B
Function Table
Inputs Outputs
Clear Clock A B QAQB... Q
H
L X X X L L ... L
HLXXQ
A0QB0
... Q
H0
H
u
HHHQAn... Q
Gn
H
u
LX L QAn... Q
Gn
H
u
XL L QAn... Q
Gn
HeHigh Level (steady state), LeLow Level (steady state)
X
e
Don’t Care (any input, including transitions)
u
e
Transition from low to high level
Q
A0,QB0,QH0
e
The level of QA,QB,orQH, respectively, before the
indicated steady-state input conditions were established.
Q
An,QGn
e
The level of QAor QGbefore the most recentutransition of
the clock; indicates a one-bit shift.
Logic Diagram
TL/F/6398– 2
C
1995 National Semiconductor Corporation RRD-B30M105/Printed in U. S. A.