NSC DS96F175CJ Datasheet
DS96F173C/DS96F173M/DS96F175C/DS96F175M
EIA-485/EIA-422 Quad Differential Receivers
DS96F173C/DS96F173M/DS96F175C/DS96F175M EIA-485/EIA-422 Quad Differential Receivers
May 1998
General Description
The DS96F173 and the DS96F175 are high speed quad differential line receivers designed to meet the EIA-485 standard. The DS96F173andthe DS96F175 offer improved performance due to the use of L-FAST bipolar technology. The
use of LFAST technology allows the DS96F173 and
DS96F175 to operate at higher speeds while minimizing
power consumption.
The DS96F173 and the DS96F175 have TRI-STATE
puts and are optimized for balanced multipoint data bus
transmission at rates up to 15 Mbps. The receivers feature
high input impedance, input hysteresis for increased noise
immunity, and input sensitivity of 200 mV over a common
mode input voltage range of −7V to +12V.The receivers are
therefore suitable for multipoint applications in noisy environments. The DS96F173 features an active high and active
low Enable, common to all four receivers. The DS96F175
features separate active high Enables for each receiver pair.
®
Features
n Meets EIA-485, EIA-422A, EIA-423A standards
n Designed for multipoint bus applications
n TRI-STATE outputs
n Common mode input voltage range: −7V to +12V
n Operates from single +5.0V supply
n Reduced power consumption (I
n Input sensitivity of
out-
n Input hysteresis of 50 mV typical
n High input impedance
n Military temperature range available
n Qualified for MIL STD 883C
n Available to standard military drawings (SMD)
n Available in DIP(J), LCC(E), and FlatPak (W) packages
n DS96F173 and DS96F175 are lead and function
compatible with SN75173/175 or the
AM26LS32/MC3486
±
200 mV over common mode range
Logic Diagrams Function Tables
(Each Receiver) DS96F173
Differential Inputs Enable Output
A–B E E
V
≥ 0.2V H X H
ID
V
≤ −0.2V H X L
DS009627-10
DS96F175
ID
XLXZ
XXHZ
H = High Level
L = Low Level
Z = High Impedance (off)
X = Don’t Care
= 50 mA max)
CC
Y
XL H
XL L
(Each Receiver) DS96F175
DS009627-11
TRI-STATE®is a registered trademark of National Semiconductor Corporation.
© 1998 National Semiconductor Corporation DS009627 www.national.com
Differential Inputs Enable Output
A–B E Y
V
≥ 0.2V H H
ID
V
≤ −0.2V H L
ID
XLZ
COMMERCIAL
Absolute Maximum Ratings
Specifications for the 883 version of this product are
listed separately.
Storage Temperature Range (T
Lead Temperature
(Soldering, 60 sec.) 300˚C
Max. Package Power Dissipation (Note 1) at 25˚C
Ceramic DIP (J) 1500 mW
Supply Voltage 7.0V
Input Voltage, A or B Inputs
Differential Input Voltage
Enable Input Voltage 7.0V
) −65˚C to +175˚C
STG
(Note 2)
±
25V
±
25V
Recommended Operating
Conditions
Supply Voltage (V
)
CC
DS96F173C/DS96F175C 4.75 5.0 5.25 V
Common Mode Input
Voltage (V
Differential Input Voltage
)
(V
ID
) −7 +12 V
CM
Output Current HIGH (I
Output Current LOW (I
Operating Temperature (T
DS96F173C/DS96F175C 0 25 70 ˚C
Note 1: Derate package 10 mW/˚C above 25˚C.
Min Typ Max Units
|12| V
) −400 µA
OH
)11mA
OL
)
A
Low Level Output Current 50 mA
Electrical Characteristics (Notes 3, 4)
Over recommended supply voltage and operating temperature ranges, unless otherwise specified
Symbol Parameter Conditions Min Typ Max Units
V
TH
V
TL
V
TH−VTL
V
IH
V
IL
V
IC
V
OH
V
OL
I
OZ
I
I
I
IH
I
IL
R
I
I
OS
I
CC
I
CCX
Differential-Input VO=V
OH
High Threshold Voltage
Differential-Input (Note 5) VO=V
OL
−0.2 V
Low Threshold Voltage
Hysteresis (Note 6) VCM=0V 50 mV
Enable Input Voltage HIGH 2.0 V
Enable Input Voltage LOW 0.8 V
Enable Input Clamp Voltage II= −18 mA −1.5 V
Output Voltage HIGH VID= 200 mV 0˚C to +70˚C 2.8 V
I
= −400 µA −55˚C to +125˚C 2.5
OH
Output Voltage LOW VID= −200 mV IOL= 8.0 mA 0.45 V
I
= 11 mA 0.50
OL
High-Impedance State Output VO= 0.4V to 2.4V
Line Input Current (Note 7) Other Input = 0V VI= 12V 1.0 mA
V
= −7.0V −0.8
I
Enable Input Current HIGH VIH= 2.7V 20 µA
Enable Input Current LOW VIL= 0.4V −100 µA
Input Resistance 14 18 22 kΩ
Short Circuit Output Current (Note 8) −15 −85 mA
Supply Current No Load Outputs Enabled 50 mA
Outputs Disabled 50
0.2 V
±
20 µA
COMMERCIAL
Switching Characteristics
VCC= 5.0V, TA= 25˚C
Symbol Parameter Conditions Min Typ Max Units
t
PLH
t
PHL
t
ZH
t
ZL
t
HZ
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Propagation Delay Time, VID= −2.5V to +2.5V, 5.0 15 22 ns
Low to High Level Output C
=15pF,
L
Figure 1
Propagation Delay Time, VCM= 0V 5.0 15 22 ns
High to Low Level Output
Output Enable Time to High Level CL=15pF,
Output Enable Time to Low Level CL=15pF,
Output Disable Time from High Level CL= 5.0 pF,
Figure 2
Figure 3
Figure 2
12 16 ns
13 18 ns
14 20 ns
Switching Characteristics (Continued)
VCC= 5.0V, TA= 25˚C
Symbol Parameter Conditions Min Typ Max Units
t
LZ
|t
PLH–tPHL
Note 2: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the devices
should be operated at these limits. The tables of “Electrical Characteristics” provide conditions for actual device operation.
Note 3: Unless otherwise specified min/max limits apply across the 0˚C to +70˚C range for the DS96F173C/DS96F175C. All typicals are given for V
= 25˚C.
Note 4: All currents into the device pins are positive; all currents out of the device pins are negative. All voltages are reference to ground unless otherwise specified.
Note 5: The algebraic convention, when the less positive (more negative) limit is designated minimum, is used in this data sheet for common mode input voltage
and threshold voltage levels only.
Note 6: Hysteresis is the difference between the positive-going input threshold voltage. V
Note 7: Refer to EIA-485 Standard for exact conditions.
Note 8: Only one output at a time should be shorted.
Output Disable Time from Low Level CL= 5.0 pF,
| Pulse Width Distortion (SKEW)
Figure 1
Order Number: DS96F173CJ
DS96F175CJ
See NS Package Number J16A
Figure 3
14 18 ns
1.0 3.0 ns
, and the negative going input threshold voltage, VTL.
TH
= 5V and T
CC
A
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