April 2000
Geode™ GXm Processor
Integrated x86 Solution with MMX Support
General Description
The National Semiconductor® Geode™ GXm processor is an advanced 32-bit x86 compatible processor offering high performance, fully accelerated 2D graphics, a 64-bit synchronous DRAM controller and a PCI bus controller, all on a single chip that is compatible with Intel’s MMX technology.
The GXm processor core is a proven design that offers competitive CPU performance. It has integer and floating point execution units that are based on sixth-generation technology. The integer core contains a single, six-stage execution pipeline and offers advanced features such as operand forwarding, branch target buffers, and extensive write buffering. A 16 KB write-back L1 cache is accessed in a unique fashion that eliminates pipeline stalls to fetch operands that hit in the cache.
In addition to the advanced CPU features, the GXm processor integrates a host of functions which are typically implemented with external components. A full-function
graphics accelerator provides pixel processing and rendering functions.
A separate on-chip video buffer enables >30 fps MPEG1 video playback when used together with the CS5530 I/O companion chip. Graphics and system memory accesses are supported by a tightly-coupled synchronous DRAM (SDRAM) memory controller. This tightly coupled memory subsystem eliminates the need for an external L2 cache.
The GXm processor includes Virtual System Architecture® (VSA™ technology) enabling XpressGRAPHICS and XpressAUDIO subsystems as well as generic emulation capabilities. Software handler routines for the XpressGRAPHICS and XpressAUDIO subsystems can be included in the BIOS and provide compatible VGA and 16bit industry standard audio emulation. XpressAUDIO technology eliminates much of the hardware traditionally associated with audio functions.
Geode™ GXm Processor Internal Block Diagram
Write-Back |
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MMU |
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Integer |
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FPU |
Cache Unit |
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Unit |
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C-Bus
Internal Bus Interface Unit
X-Bus
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Integrated |
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Graphics |
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Memory |
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Display |
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PCI |
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Pipeline |
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Controller |
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Controller |
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Controller |
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Functions |
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SDRAM Port |
CS5530 |
PCI Bus |
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(CRT/LCD TFT) |
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National Semiconductor and Virtual System Architecture are registered trademarks of National Semiconductor Corporation. Geode and VSA are trademarks of National Semiconductor Corporation.
For a complete listing of National Semiconductor trademarks, please visit www.national.com/trademarks.
Support MMX with Solution x86 Integrated Processor GXm Geode™
© 2000 National Semiconductor Corporation |
www.national.com |
Geode™ GXm Processor
Features
General Features
Packaged in:
—352-Terminal Ball Grid Array (BGA) or
—320-Pin Staggered Pin Grid Array (SPGA)
0.35-micron four layer metal CMOS process
Split rail design (3.3V I/O and 2.9V core)
32-Bit x86 Processor
Supports the MMX instruction set extension for the acceleration of multimedia applications
Speeds offered up to 266 MHz
16 KB unified L1 cache
Integrated Floating Point Unit (FPU)
Re-entrant System Management Mode (SMM) enhanced for VSA
PCI Controller
Fixed, rotating, hybrid, or ping-pong arbitration
Supports up to three PCI bus masters
Synchronous CPU and PCI bus clock frequency
Supports concurrency between PCI master and L1 cache
Power Management
Designed to support CS5530 power management architecture
CPU only Suspend or full 3V Suspend supported:
—Clocks to CPU core stopped for CPU Suspend
—All on-chip clocks stopped for 3V Suspend
—Suspend refresh supported for 3V Suspend
Virtual Systems Architecture Technology
Architecture allows OS independent (software) virtualization of hardware functions
Provides compatible high performance legacy VGA core functionality
Note: GUI (Graphical User Interface) graphics acceleration is pure hardware.
Provides 16-bit XpressAUDIO subsystem
2D Graphics Accelerator
Graphics pipeline performance significantly increased over previous generations by pipelining burst reads/writes
Accelerates BitBLTs, line draw, text
Supports all 256 raster operations
Supports transparent BLTs
Runs at core clock frequency
Full VGA and VESA mode support
Special "Driver level” instructions utilize internal scratchpad for enhanced performance
Display Controller
Video Generator (VG) improves memory efficiency for display refresh with SDRAM
Supports a separate MPEG1 video buffer and data path to enable video acceleration in the CS5530
Internal palette RAM for use with the CS5530
Direct interface to CS5530 for CRT and TFT flat panel support which eliminates need for external RAMDAC
Hardware frame buffer compressor/decompressor
Hardware cursor
Supports up to 1280x1024x8 bpp and 1024x768x16 bpp
XpressRAM Subsystem
Memory control/interface directly from CPU
64-Bit wide memory bus
Support for:
—Two 168-pin unbuffered DIMMs
—Up to 16 open banks simultaneously
—Single or 16-byte reads (burst length of two)
www.national.com |
2 |
Revision 3.1 |
Table of Contents
1.0 Architecture Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
1.1 INTEGER UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1.2 FLOATING POINT UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.3 WRITE-BACK CACHE UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.4 MEMORY MANAGEMENT UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.4.1 Internal Bus Interface Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.5 INTEGRATED FUNCTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.5.1 Graphics Accelerator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.5.2 Display Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 1.5.3 XpressRAM Memory Subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 1.5.4 PCI Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
1.6 GEODE GXM/CS5530 SYSTEM DESIGNS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.0 Signal Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.1 PIN ASSIGNMENTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.2 SIGNAL DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 2.2.1 System Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 2.2.2 PCI Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 2.2.3 Memory Controller Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 2.2.4 Video Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 2.2.5 Power, Ground, and No Connect Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 2.2.6 Internal Test and Measurement Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
2.3 SUBSYSTEM SIGNAL CONNECTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 2.4 POWER PLANES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
3.0 Processor Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
3.1 CORE PROCESSOR INITIALIZATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
3.2 INSTRUCTION SET OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
3.2.1 Lock Prefix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
3.3 REGISTER SETS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
3.3.1 Application Register Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
3.3.2 System Register Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
3.3.3 Model Specific Register Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
3.3.4 Time Stamp Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
3.4 ADDRESS SPACES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
3.4.1 I/O Address Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
3.4.2 Memory Address Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
3.5 OFFSET, SEGMENT, AND PAGING MECHANISMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
3.6 OFFSET MECHANISM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
3.7 DESCRIPTORS AND SEGMENT MECHANISMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
3.7.1 Real and Virtual 8086 Mode Segment Mechanisms . . . . . . . . . . . . . . . . . . . . . . . 62
3.7.2 Segment Mechanism in Protective Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
3.7.3 GDTR and LDTR Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
3.7.4 Descriptor Bit Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
3.7.5 Gate Descriptors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
3.8 MULTITASKING AND TASK STATE SEGMENTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
3.9 PAGING MECHANISM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Processor GXm Geode™
Revision 3.1 |
3 |
www.national.com |
Geode™ GXm Processor
Table of Contents (Continued)
3.10 |
INTERRUPTS AND EXCEPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
74 |
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3.10.1 |
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
74 |
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3.10.2 |
Exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
74 |
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3.10.3 |
Interrupt Vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
75 |
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3.10.4 Interrupt and Exception Priorities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
76 |
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3.10.5 Exceptions in Real Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
77 |
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3.10.6 |
Error Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
77 |
3.11 |
SYSTEM MANAGEMENT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
78 |
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3.11.1 |
SMM Enhancements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
79 |
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3.11.2 |
SMM Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
79 |
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3.11.3 |
The SMI# Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
80 |
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3.11.4 |
SMM Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
80 |
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3.11.5 SMM Memory Space Header . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
80 |
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3.11.6 |
SMM Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
82 |
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3.11.7 |
SMM Memory Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
83 |
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3.11.8 |
SMI Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
83 |
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3.11.9 SMI Service Routine Execution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
83 |
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3.12 |
SHUTDOWN AND HALT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
86 |
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3.13 |
PROTECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
86 |
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3.13.1 |
Privilege Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
86 |
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3.13.2 |
I/O Privilege Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
86 |
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3.13.3 |
Privilege Level Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
87 |
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3.13.4 Initialization and Transition to Protected Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
87 |
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3.14 |
VIRTUAL 8086 MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
88 |
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3.14.1 |
Memory Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
88 |
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3.14.2 |
Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
88 |
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3.14.3 |
Interrupt Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
88 |
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3.14.4 Entering and Leaving Virtual 8086 Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
88 |
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3.15 FLOATING POINT UNIT OPERATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
89 |
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3.15.1 FPU (Floating Point Unit) Register Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
89 |
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3.15.2 FPU Tag Word Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
89 |
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3.15.3 |
FPU Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
89 |
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3.15.4 FPU Mode Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
89 |
4.0 Integrated Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
4.1 INTEGRATED FUNCTIONS PROGRAMMING INTERFACE . . . . . . . . . . . . . . . . . . . . . . . 92 4.1.1 Graphics Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 4.1.2 Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 4.1.3 Graphics Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 4.1.4 L1 Cache Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 4.1.5 Display Driver Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 4.1.6 CPU_READ/CPU_WRITE Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
4.2 INTERNAL BUS INTERFACE UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 4.2.1 FPU Error Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 4.2.2 A20M Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 4.2.3 SMI Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 4.2.4 640 KB to 1 MB Region . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 4.2.5 Internal Bus Interface Unit Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
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4 |
Revision 3.1 |
Table of Contents (Continued)
4.3 |
MEMORY CONTROLLER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
103 |
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4.3.1 |
Memory Array Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
104 |
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4.3.2 |
Memory Organizations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
105 |
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4.3.3 |
SDRAM Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
106 |
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4.3.4 |
Memory Controller Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
108 |
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4.3.5 |
Address Translation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
112 |
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4.3.6 |
Memory Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
115 |
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4.3.7 |
SDRAM Interface Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
118 |
4.4 |
GRAPHICS PIPELINE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
120 |
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4.4.1 |
BitBLT/Vector Engine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
120 |
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4.4.2 |
Master/Slave Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
121 |
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4.4.3 |
Pattern Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
121 |
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4.4.4 |
Source Expansion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
123 |
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4.4.5 |
Raster Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
123 |
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4.4.6 |
Graphics Pipeline Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
124 |
4.5 |
DISPLAY CONTROLLER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
129 |
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4.5.1 |
Display FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
130 |
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4.5.2 |
Compression Technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
130 |
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4.5.3 |
Motion Video Acceleration Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
130 |
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4.5.4 |
Hardware Cursor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
131 |
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4.5.5 |
Display Timing Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
131 |
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4.5.6 |
Dither and Frame-Rate Modulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
131 |
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4.5.7 |
Display Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
131 |
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4.5.8 |
Graphics Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
135 |
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4.5.9 |
Display Controller Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
136 |
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4.5.10 |
Memory Organization Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
144 |
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4.5.11 |
Timing Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
146 |
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4.5.12 |
Cursor Position Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
149 |
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4.5.13 |
Color Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
150 |
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4.5.14 |
Palette Access Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
151 |
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4.5.15 |
CS5530 Display Controller Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
153 |
4.6 |
PCI CONTROLLER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
155 |
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4.6.1 |
X-Bus PCI Slave . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
155 |
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4.6.2 |
X-Bus PCI Master . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
155 |
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4.6.3 |
PCI Arbiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
155 |
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4.6.4 |
Generating Configuration Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
155 |
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4.6.5 |
Generating Special Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
155 |
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4.6.6 |
PCI Configuration Space Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
156 |
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4.6.7 |
PCI Configuration Space Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
157 |
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4.6.8 |
PCI Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
162 |
5.0 Virtual Subsystem Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
165 |
5.1 VIRTUAL VGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
5.1.1 Traditional VGA Hardware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
5.2 GXM VIRTUAL VGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
5.2.1 Datapath Elements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
5.2.2 Video Refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
5.2.3 GXm VGA Hardware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
5.2.4 VGA Video BIOS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
5.2.5 Virtual VGA Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
Processor GXm Geode™
Revision 3.1 |
5 |
www.national.com |
Geode™ GXm Processor
Table of Contents (Continued) |
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6.0 Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
174 |
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6.1 |
APM SUPPORT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
174 |
6.2 |
CPU SUSPEND COMMAND REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
174 |
6.3 |
SUSPEND MODULATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
174 |
6.4 |
3-VOLT SUSPEND MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
174 |
6.5 |
SUSPEND MODE AND BUS CYCLES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
175 |
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6.5.1 Initiating Suspend with SUSP# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
175 |
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6.5.2 Initiating Suspend with HALT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
176 |
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6.5.3 Responding to a PCI Access During Suspend Mode . . . . . . . . . . . . . . . . . . . . . . |
177 |
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6.5.4 Stopping the Input Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
178 |
6.6 |
GXM PROCESSOR SERIAL BUS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
179 |
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6.6.1 Serial Packet Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
179 |
6.7 |
POWER MANAGEMENT REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
179 |
7.0 Electrical Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
7.1 PART NUMBERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 7.2 ELECTRICAL CONNECTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 7.2.1 Power/Ground Connections and Decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 7.2.2 Power Sequencing the Core and I/O Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 7.2.3 NC-Designated Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 7.2.4 Pull-Up and Pull-Down Resistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 7.2.5 Unused Input Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
7.3 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 7.4 OPERATING CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 7.5 DC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 7.6 AC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
8.0 Package Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
195 |
8.1 THERMAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 8.1.1 Heatsink Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 8.2 MECHANICAL PACKAGE OUTLINES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
9.0 Instruction Set. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
9.1 GENERAL INSTRUCTION SET FORMAT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 9.1.1 Prefix (Optional) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 9.1.2 Opcode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 9.1.3 mod and r/m Byte (Memory Addressing) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 9.1.4 reg Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 9.1.5 s-i-b Byte (Scale, Indexing, Base) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
9.2 CPUID INSTRUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208 9.2.1 Standard CPUID Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208 9.2.2 Extended CPUID Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210
9.3 PROCESSOR CORE INSTRUCTION SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212 9.4 FPU INSTRUCTION SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224 9.5 MMX INSTRUCTION SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229 9.6 NATIONAL SEMICONDUCTOR EXTENDED MMX INSTRUCTION SET . . . . . . . . . . . . . 234
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6 |
Revision 3.1 |
Table of Contents (Continued)
Appendix A Support Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236
A.1 ORDER INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236 A.2 DATA BOOK REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236
Processor GXm Geode™
Revision 3.1 |
7 |
www.national.com |
Geode™ GXm Processor
1.0Architecture Overview
The National Semiconductor Geode GXm processor is an x86-compatible 32-bit microprocessor. The decoupled load/store unit (within the memory management unit) allows multiple instructions in a single clock cycle. Other features include single-cycle execution, single-cycle instruction decode, 16 KB write-back cache, and clock rates up to 266 MHz. These features are made possible by the use of advanced-process technologies and superpipelining.
The GXm processor has low power consumption at all clock frequencies. Where additional power savings are required, designers can make use of Suspend mode, Stop Clock capability, and System Management Mode (SMM).
The GXm processor is divided into major functional blocks (as shown in Figure 1-1):
•Integer Unit
•Floating Point Unit (FPU)
•Write-Back Cache Unit
•Memory Management Unit (MMU)
•Internal Bus Interface Unit
•Integrated Functions
Instructions are executed in the integer unit and in the floating point unit. The cache unit stores the most recently used data and instructions and provides fast access to this information for the integer and floating point units.
1.1 INTEGER UNIT
The integer unit consists of:
•Instruction Buffer
•Instruction Fetch
•Instruction Decoder and Execution
The superpipelined integer unit fetches, decodes, and executes x86 instructions through the use of a six-stage integer pipeline.
The instruction fetch pipeline stage generates, from the on-chip cache, a continuous high-speed instruction stream for use by the processor. Up to 128 bits of code are read during a single clock cycle.
Branch prediction logic within the prefetch unit generates a predicted target address for unconditional or conditional branch instructions. When a branch instruction is detected, the instruction fetch stage starts loading instructions at the predicted address within a single clock cycle. Up to 48 bytes of code are queued prior to the instruction decode stage.
The instruction decode stage evaluates the code stream provided by the instruction fetch stage and determines the number of bytes in each instruction and the instruction type. Instructions are processed and decoded at a maximum rate of one instruction per clock.
The address calculation function is super-pipelined and contains two stages, AC1 and AC2. If the instruction refers to a memory operand, AC1 calculates a linear memory address for the instruction.
The AC2 stage performs any required memory management functions, cache accesses, and register file accesses. If a floating point instruction is detected by AC2, the instruction is sent to the floating point unit for processing.
The execution stage, under control of microcode, executes instructions using the operands provided by the address calculation stage.
Write-back, the last stage of the integer unit, updates the register file within the integer unit or writes to the load/store unit within the memory management unit.
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Internal Bus Interface Unit
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SDRAM Port |
CS5530 |
PCI Bus |
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Figure 1-1. Internal Block Diagram
www.national.com |
8 |
Revision 3.1 |
Architecture Overview (Continued)
1.2FLOATING POINT UNIT
The FPU (Floating Point Unit) interfaces to the integer unit and the cache unit through a 64-bit bus. The FPU is x87- instruction-set compatible and adheres to the IEEE-754 standard. Because almost all applications that contain FPU instructions also contain integer instructions, the GXm processor’s FPU achieves high performance by completing integer and FPU operations in parallel.
FPU instructions are dispatched to the pipeline within the integer unit. The address calculation stage of the pipeline checks for memory management exceptions and accesses memory operands for use by the FPU. Once the instructions and operands have been provided to the FPU, the FPU completes instruction execution independently of the integer unit.
1.3WRITE-BACK CACHE UNIT
The 16 KB write-back unified cache is a data/instruction cache and is configured as four-way set associative. The cache stores up to 16 KB of code and data in 1024 cache lines.
The GXm processor provides the ability to allocate a portion of the L1 cache as a scratchpad, which is used to accelerate the Virtual Systems Architecture algorithms as well as for some graphics operations.
1.4MEMORY MANAGEMENT UNIT
The memory management unit (MMU) translates the linear address supplied by the integer unit into a physical address to be used by the cache unit and the internal bus interface unit. Memory management procedures are x86compatible, adhering to standard paging mechanisms.
The MMU also contains a load/store unit that is responsible for scheduling cache and external memory accesses. The load/store unit incorporates two performanceenhancing features:
•Load-store reordering that gives priority to memory reads required by the integer unit over writes to external memory.
•Memory-read bypassing that eliminates unnecessary memory reads by using valid data from the execution unit.
1.4.1Internal Bus Interface Unit
The internal bus interface unit provides a bridge from the GXm processor to the integrated system functions (i.e., memory subsystem, display controller, graphics pipeline) and the PCI bus interface.
When external memory access is required, the physical address is calculated by the memory management unit and then passed to the internal bus interface unit, which translates the cycle to an X-Bus cycle (the X-Bus is a National Semiconductor proprietary internal bus which provides a common interface for all of the system modules). The X-Bus memory cycle now is arbitrated between
other pending X-Bus memory requests to the SDRAM controller before completing.
In addition, the internal bus interface unit provides configuration control for up to 20 different regions within system memory with separate controls for read access, write access, cacheability, and PCI access.
1.5INTEGRATED FUNCTIONS
The GXm processor integrates the following functions traditionally implemented using external devices:
•High-performance 2D graphics accelerator
•Separate CRT and TFT data paths from the display controller
•SDRAM memory controller
•PCI bridge
The processor has also been enhanced to support National Semiconductor’s proprietary Virtual System Architecture (VSA) implementation.
The GXm processor implements a Unified Memory Architecture (UMA). By using National Semiconductor’s Display Compression Technology (DCT), the performance degradation inherent in traditional UMA systems is eliminated.
1.5.1Graphics Accelerator
The graphics accelerator is a full-featured GUI (Graphical User Interface) accelerator. The graphics pipeline implements a bitBLT engine for frame buffer bitBLTs and rectangular fills. Additional instructions in the integer unit may be processed, as the bitBLT engine assists the CPU in the bitBLT operations that take place between system memory and the frame buffer. This combination of hardware and software is used by the display driver to provide very fast transfers in both directions between system memory and the frame buffer. The bitBLT engine also draws ran- domly-oriented vectors, and scanlines for polygon fill. All of the pipeline operations described in the following list can be applied to any bitBLT operation.
•Pattern Memory. Render with 8x8 dither, 8x8 monochrome, or 8x1 color pattern.
•Color Expansion. Expand monochrome bitmaps to full-depth 8- or 16-bit colors.
•Transparency. Suppresses drawing of background pixels for transparent text.
•Raster Operations. Boolean operation combines source, destination, and pattern bitmaps.
Processor GXm Geode™
Revision 3.1 |
9 |
www.national.com |
Geode™ GXm Processor
Architecture Overview (Continued)
1.5.2Display Controller
The display port is a direct interface to the CS5530 which drives a TFT flat panel display, LCD panel, or a CRT display.
The display controller (video generator) retrieves image data from the frame buffer region of memory, performs a color-look-up if required, inserts the cursor overlay into the pixel stream, generates display timing, and formats the pixel data for output to a variety of display devices. The display controller contains Display Compression Technology (DCT) that allows the GXm processor to refresh the display from a compressed copy of the frame buffer. DCT typically decreases the screen-refresh bandwidth requirement by a factor of 15 to 20, further minimizing bandwidth contention.
1.5.3XpressRAM Memory Subsystem
The memory controller drives a 64-bit SDRAM port directly. The SDRAM memory array contains both the main system memory and the graphics frame buffer. Up to four module banks of SDRAM are supported. Each module bank will have two or four component banks depending on the memory size and organization. The maximum configuration is four module banks with four component banks providing a total of 16 open banks. The maximum memory size is 1 GB.
The memory controller handles multiple requests for memory data from the GXm processor, the graphics accelerator and the display controller. The memory controller contains extensive buffering logic that helps minimize contention for memory bandwidth between graphics and CPU requests. The memory controller cooperates with the internal bus controller to determine the cacheability of all memory references.
1.5.4PCI Controller
The GXm processor incorporates a full-function PCI interface module that includes the PCI arbiter. All accesses to external I/O devices are sent over the PCI bus, although most memory accesses are serviced by the SDRAM controller. The Internal Bus Interface Unit contains address mapping logic that determines if memory accesses are targeted for the SDRAM or for the PCI bus.
www.national.com |
10 |
Revision 3.1 |
Architecture Overview (Continued)
1.6 GEODE GXM/CS5530 SYSTEM DESIGNS
The GXm Integrated Subsystem with MMX support consists of two chips, the GXm Processor and the CS5530 I/O companion. The subsystem provides high performance using 32-bit x86 processing. The two chips integrate video, audio and memory interface functions normally performed by external hardware.
As described in separate manuals, the CS5530 enables the full features of the GXm processor with MMX support. These features include full VGA and VESA video, 16-bit stereo sound, IDE interface, ISA interface, SMM power
management, and AT compatibility logic. In addition, the newer CS5530 provides an Ultra DMA/33 interface, MPEG2 assist, and AC97 Version 2.0 compliant audio.
Figure 1-2 shows a basic block system diagram (refer to Figure 2-4 on page 34 for detailed subsystem interconnection signals). It includes the National Semiconductor CS9210 Dual-Scan Flat Panel Display Controller for designs that need to interface to a DSTN panel (instead of TFT panel).
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RGB Port |
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Figure 1-2. Geode™ GXm/CS5530 System Block Diagram
Processor GXm Geode™
Revision 3.1 |
11 |
www.national.com |
Geode™ GXm Processor
Architecture Overview (Continued)
The CS9210 converts the digital RGB output of the CS5530 I/O companion chip to the digital output suitable for driving a dual-scan color STN (DSTN) flat panel LCD. It connects to the digital RGB output of a GXm processor or 55x0 and drives the graphics data onto a dual-scan flat
panel LCD. It can drive all standard dual-scan color STN flat panels up to 1024x768 resolution. Figure 1-3 shows an example of a CS9210 interface in a typical GXm Integrated Subsystem.
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Pixel Data |
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DSTN
LCD
Figure 1-3. CS9210 Interface System Diagram
www.national.com |
12 |
Revision 3.1 |
2.0Signal Definitions
This section describes the external interface of the Geode GXm processor. Figure 2-1 shows the signals organized by their functional interface groups (internal test and electrical pins are not shown).
2.1PIN ASSIGNMENTS
The tables in this section use several common abbreviations. Table 2-1 lists the mnemonics and their meanings.
Figure 2-2 on page 14 shows the pin assignment for the 352 BGA with Tables 2-2 and 2-3 listing the pin assignments sorted by pin number and alphabetically by signal name, respectively.
Figure 2-3 on page 19 shows the pin assignment for the 320 SPGA with Tables 2-4 and 2-5 listing the pin assignments sorted by pin number and alphabetically by signal name, respectively.
In Section 2.2 “Signal Descriptions” starting on Page 24 a description of each signal is provided within its associated functional group.
Following the signal descriptions, information regarding subsystem signal connections and split power planes and decoupling is provided.
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Table 2-1. Pin Type Definitions
Mnemonic |
Definition |
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I |
Standard input pin. |
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I/O |
Bidirectional pin. |
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O |
Totem-pole output. |
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OD |
Open-drain output structure that allows |
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Pull-up resistor |
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Pull-down resistor |
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Sustained tri-state, an active-low tri-state |
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VCC (PWR) |
Power pin. |
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VSS (GND) |
Ground pin |
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# |
The "#" symbol at the end of a signal |
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SYSCLK |
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MD[63:0] |
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CLKMODE[2:0] |
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MA[12:0] |
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System |
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RESET |
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BA[1:0] |
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INTR |
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RASA#, RASB# |
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Interface |
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IRQ13 |
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CASA#, CASB# |
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Memory |
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Signals |
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SMI# |
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CS[3:0]# |
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Controller |
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SUSP# |
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WEA#, WEB# |
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Interface |
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SUSPA# |
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DQM[7:0] |
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SERIALP |
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CKEA, CKEB |
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Signals |
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Geode™ GXm |
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SDCLK[3:0] |
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SDCLK_IN |
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AD[31:0] |
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Processor |
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SDCLK_OUT |
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C/BE[3:0]# |
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PAR |
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PCLK |
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FRAME# |
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VID_CLK |
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IRDY# |
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DCLK |
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PCI |
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TRDY# |
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CRT_HSYNC |
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Interface |
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STOP# |
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CRT_VSYNC |
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Video |
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LOCK# |
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FP_HSYNC |
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Signals |
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Interface |
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DEVSEL# |
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FP_VSYNC |
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Signals |
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PERR# |
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ENA_DISP |
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SERR# |
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VID_RDY |
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REQ[2:0]# |
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VID_VAL |
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GNT[2:0]# |
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VID_DATA[7:0] |
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PIXEL[17:0] |
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Figure 2-1. Functional Block Diagram |
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Processor GXm Geode™
Revision 3.1 |
13 |
www.national.com |
Processor |
Signal Definitions (Continued) |
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Index Corner |
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GXm |
1 |
2 |
3 |
4 |
5 |
6 |
7 |
8 |
9 |
10 |
11 |
12 |
13 |
14 |
15 |
16 |
17 |
18 |
19 |
20 |
21 |
22 |
23 |
24 |
25 |
26 |
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A |
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A |
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VSS |
VSS |
AD27 |
AD24 |
AD21 |
AD16 |
VCC2 FRAM#DEVS# VCC3 PERR# AD15 |
VSS |
AD11 CBE0# |
AD6 |
VCC2 |
AD4 |
AD2 |
VCC3 |
AD0 |
AD1 |
TEST2 |
MD2 |
VSS |
VSS |
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Geode™ |
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B |
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B |
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VSS |
VSS |
AD28 |
AD25 |
AD22 |
AD18 |
VCC2 CBE2# TRDY# VCC3 LOCK# |
PAR |
AD14 |
AD12 |
AD9 |
AD7 |
VCC2 |
INTR |
AD3 |
VCC3 TEST1 TEST3 |
MD1 |
MD33 |
VSS |
VSS |
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C |
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C |
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AD29 |
AD31 |
AD30 |
AD26 |
AD23 |
AD19 |
VCC2 |
AD17 |
IRDY# VCC3 STOP#SERR# CBE1# AD13 |
AD10 |
AD8 |
VCC2 |
AD5 |
SMI# |
VCC3 TEST0 IRQ13 MD32 |
MD34 |
MD3 |
MD35 |
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D |
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D |
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GNT0# |
TDI |
REQ2# |
VSS |
CBE3# |
VSS |
VCC2 |
VSS |
VSS |
VCC3 |
VSS |
VSS |
VSS |
VSS |
VSS |
VSS |
VCC2 |
VSS |
VSS |
VCC3 |
VSS |
MD0 |
VSS |
MD4 |
MD36 |
TDN |
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E |
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E |
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GNT2#SUSPA#REQ0# AD20 |
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MD6 |
TDP |
MD5 |
MD37 |
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F |
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F |
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TD0 |
GNT1# TEST |
VSS |
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VSS |
MD38 |
MD7 |
MD39 |
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G |
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G |
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VCC3 VCC3 VCC3 VCC3 |
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VCC3 VCC3 VCC3 VCC3 |
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H |
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H |
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TMS SUSP# REQ1# |
VSS |
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VSS |
MD8 |
MD40 |
MD9 |
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J |
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J |
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FPVSY TCLK RESET |
VSS |
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VSS |
MD41 |
MD10 |
MD42 |
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K |
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K |
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VCC2 VCC2 VCC2 VCC2 |
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VCC2 VCC2 VCC2 VCC2 |
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L |
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L |
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CKM1 FPHSYSERLP |
VSS |
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VSS |
MD11 MD43 MD12 |
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M |
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Geode™ GXm |
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M |
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CKM2 VIDVAL CKM0 |
VSS |
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VSS |
MD44 |
MD13 |
MD45 |
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N |
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N |
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VSS |
PIX1 |
PIX0 |
VSS |
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Processor |
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VSS |
MD14 |
MD46 |
MD15 |
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P |
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P |
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VIDCLK PIX3 |
PIX2 |
VSS |
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VSS |
MD47 CASA#SYSCLK |
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R |
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R |
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PIX4 |
PIX5 |
PIX6 |
VSS |
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352 BGA - Top View |
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VSS |
WEB# WEA# CASB# |
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T |
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T |
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PIX7 |
PIX8 |
PIX9 |
VSS |
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VSS |
DQM0 DQM4 DQM1 |
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U |
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U |
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VCC3 VCC3 VCC3 VCC3 |
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VCC3 VCC3 VCC3 VCC3 |
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V |
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V |
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PIX10 |
PIX11 |
PIX12 |
VSS |
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VSS |
DQM5 |
CS2# |
CS0# |
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W |
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W |
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PIX13 CRTHS PIX14 |
VSS |
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VSS |
RASA# RASB# |
MA0 |
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Y |
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Y |
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VCC2 VCC2 VCC2 VCC2 |
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VCC2 VCC2 VCC2 VCC2 |
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AA |
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AA |
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PIX15 PIX16 CRTVS |
VSS |
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VSS |
MA1 |
MA2 |
MA3 |
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AB |
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AB |
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DCLK |
PIX17 VDAT6 VDAT7 |
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MA4 |
MA5 |
MA6 |
MA7 |
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AC |
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AC |
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PCLK |
FLT# |
VDAT4 |
VSS VOLDET VSS |
VCC2 |
VSS |
VSS |
VCC3 |
VSS |
VSS |
VSS |
VSS |
VSS |
VSS |
VCC2 |
VSS |
VSS |
VCC3 |
VSS |
DQM6 |
VSS |
MA8 |
MA9 |
MA10 |
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AD |
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AD |
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VRDY VDAT5 VDAT3 VDAT0 EDISP MD63 |
VCC2 |
MD62 |
MD29 |
VCC3 |
MD59 |
MD26 |
MD56 |
MD55 |
MD22 CKEB VCC2 |
MD51 |
MD18 |
VCC3 |
MD48 DQM3 |
CS1# |
MA11 |
BA0 |
BA1 |
|||||||||
|
AE |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
AE |
|
|
VSS |
VSS |
VDAT2 SCLK3 SCLK1RWCLK VCC2 SCKIN MD61 |
VCC3 |
MD28 |
MD58 |
MD25 |
MD24 |
MD54 |
MD21 |
VCC2 |
MD20 |
MD50 |
VCC3 |
MD17 DQM7 |
CS3# |
MA12 |
VSS |
VSS |
||||||||
|
AF |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
AF |
|
|
VSS |
VSS |
VDAT1 SCLK0 SCLK2 MD31 VCC2SCKOUTMD30 VCC3 MD60 MD27 MD57 |
VSS |
MD23 MD53 VCC2 MD52 MD19 VCC3 MD49 MD16 DQM2 CKEA |
VSS |
VSS |
||||||||||||||||||||
|
1 |
2 |
3 |
4 |
5 |
6 |
7 |
8 |
9 |
10 |
11 |
12 |
13 |
14 |
15 |
16 |
17 |
18 |
19 |
20 |
21 |
22 |
23 |
24 |
25 |
26 |
Note: Signal names have been abbreviated in this figure due to space constraints.
= GND terminal
= PWR terminal (VCC2 = VCC_CORE; VCC3 = VCC_IO)
Figure 2-2. 352 BGA Pin Assignment Diagram
For order information refer to Section A.1 “Order Information” on page 236.
www.national.com |
14 |
Revision 3.1 |
Signal Definitions (Continued)
Table 2-2. 352 BGA Pin Assignments - Sorted by Pin Number
Pin |
|
|
Pin |
|
|
Pin |
|
|
Pin |
|
|
Pin |
|
No. |
Signal Name |
|
No. |
Signal Name |
|
No. |
Signal Name |
|
No. |
Signal Name |
|
No. |
Signal Name |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
A1 |
VSS |
|
B23 |
MD1 |
|
D19 |
VSS |
|
K1 |
VCC2 |
|
T1 |
PIXEL7 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
A2 |
VSS |
|
B24 |
MD33 |
|
D20 |
VCC3 |
|
K2 |
VCC2 |
|
T2 |
PIXEL8 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
A3 |
AD27 |
|
B25 |
VSS |
|
D21 |
VSS |
|
K3 |
VCC2 |
|
T3 |
PIXEL9 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
A4 |
AD24 |
|
B26 |
VSS |
|
D22 |
MD0 |
|
K4 |
VCC2 |
|
T4 |
VSS |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
A5 |
AD21 |
|
C1 |
AD29 |
|
D23 |
VSS |
|
K23 |
VCC2 |
|
T23 |
VSS |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
A6 |
AD16 |
|
C2 |
AD31 |
|
D24 |
MD4 |
|
K24 |
VCC2 |
|
T24 |
DQM0 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
A7 |
VCC2 |
|
C3 |
AD30 |
|
D25 |
MD36 |
|
K25 |
VCC2 |
|
T25 |
DQM4 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
A8 |
FRAME# |
|
C4 |
AD26 |
|
D26 |
TDN |
|
K26 |
VCC2 |
|
T26 |
DQM1 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
A9 |
DEVSEL# |
|
C5 |
AD23 |
|
E1 |
GNT2# |
|
L1 |
CLKMODE1 |
|
U1 |
VCC3 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
A10 |
VCC3 |
|
C6 |
AD19 |
|
E2 |
SUSPA# |
|
L2 |
FP_HSYNC |
|
U2 |
VCC3 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
A11 |
PERR# |
|
C7 |
VCC2 |
|
E3 |
REQ0# |
|
L3 |
SERIALP |
|
U3 |
VCC3 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
A12 |
AD15 |
|
C8 |
AD17 |
|
E4 |
AD20 |
|
L4 |
VSS |
|
U4 |
VCC3 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
A13 |
VSS |
|
C9 |
IRDY# |
|
E23 |
MD6 |
|
L23 |
VSS |
|
U23 |
VCC3 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
A14 |
AD11 |
|
C10 |
VCC3 |
|
E24 |
TDP |
|
L24 |
MD11 |
|
U24 |
VCC3 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
A15 |
C/BE0# |
|
C11 |
STOP# |
|
E25 |
MD5 |
|
L25 |
MD43 |
|
U25 |
VCC3 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
A16 |
AD6 |
|
C12 |
SERR# |
|
E26 |
MD37 |
|
L26 |
MD12 |
|
U26 |
VCC3 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
A17 |
VCC2 |
|
C13 |
C/BE1# |
|
F1 |
TDO |
|
M1 |
CLKMODE2 |
|
V1 |
PIXEL10 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
A18 |
AD4 |
|
C14 |
AD13 |
|
F2 |
GNT1# |
|
M2 |
VID_VAL |
|
V2 |
PIXEL11 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
A19 |
AD2 |
|
C15 |
AD10 |
|
F3 |
TEST |
|
M3 |
CLKMODE0 |
|
V3 |
PIXEL12 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
A20 |
VCC3 |
|
C16 |
AD8 |
|
F4 |
VSS |
|
M4 |
VSS |
|
V4 |
VSS |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
A21 |
AD0 |
|
C17 |
VCC2 |
|
F23 |
VSS |
|
M23 |
VSS |
|
V23 |
VSS |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
A22 |
AD1 |
|
C18 |
AD5 |
|
F24 |
MD38 |
|
M24 |
MD44 |
|
V24 |
DQM5 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
A23 |
TEST2 |
|
C19 |
SMI# |
|
F25 |
MD7 |
|
M25 |
MD13 |
|
V25 |
CS2# |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
A24 |
MD2 |
|
C20 |
VCC3 |
|
F26 |
MD39 |
|
M26 |
MD45 |
|
V26 |
CS0# |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
A25 |
VSS |
|
C21 |
TEST0 |
|
G1 |
VCC3 |
|
N1 |
VSS |
|
W1 |
PIXEL13 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
A26 |
VSS |
|
C22 |
IRQ13 |
|
G2 |
VCC3 |
|
N2 |
PIXEL1 |
|
W2 |
CRT_HSYNC |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
B1 |
VSS |
|
C23 |
MD32 |
|
G3 |
VCC3 |
|
N3 |
PIXEL0 |
|
W3 |
PIXEL14 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
B2 |
VSS |
|
C24 |
MD34 |
|
G4 |
VCC3 |
|
N4 |
VSS |
|
W4 |
VSS |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
B3 |
AD28 |
|
C25 |
MD3 |
|
G23 |
VCC3 |
|
N23 |
VSS |
|
W23 |
VSS |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
B4 |
AD25 |
|
C26 |
MD35 |
|
G24 |
VCC3 |
|
N24 |
MD14 |
|
W24 |
RASA# |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
B5 |
AD22 |
|
D1 |
GNT0# |
|
G25 |
VCC3 |
|
N25 |
MD46 |
|
W25 |
RASB# |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
B6 |
AD18 |
|
D2 |
TDI |
|
G26 |
VCC3 |
|
N26 |
MD15 |
|
W26 |
MA0 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
B7 |
VCC2 |
|
D3 |
REQ2# |
|
H1 |
TMS |
|
P1 |
VID_CLK |
|
Y1 |
VCC2 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
B8 |
C/BE2# |
|
D4 |
VSS |
|
H2 |
SUSP# |
|
P2 |
PIXEL3 |
|
Y2 |
VCC2 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
B9 |
TRDY# |
|
D5 |
C/BE3# |
|
H3 |
REQ1# |
|
P3 |
PIXEL2 |
|
Y3 |
VCC2 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
B10 |
VCC3 |
|
D6 |
VSS |
|
H4 |
VSS |
|
P4 |
VSS |
|
Y4 |
VCC2 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
B11 |
LOCK# |
|
D7 |
VCC2 |
|
H23 |
VSS |
|
P23 |
VSS |
|
Y23 |
VCC2 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
B12 |
PAR |
|
D8 |
VSS |
|
H24 |
MD8 |
|
P24 |
MD47 |
|
Y24 |
VCC2 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
B13 |
AD14 |
|
D9 |
VSS |
|
H25 |
MD40 |
|
P25 |
CASA# |
|
Y25 |
VCC2 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
B14 |
AD12 |
|
D10 |
VCC3 |
|
H26 |
MD9 |
|
P26 |
SYSCLK |
|
Y26 |
VCC2 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
B15 |
AD9 |
|
D11 |
VSS |
|
J1 |
FP_VSYNC |
|
R1 |
PIXEL4 |
|
AA1 |
PIXEL15 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
B16 |
AD7 |
|
D12 |
VSS |
|
J2 |
TCLK |
|
R2 |
PIXEL5 |
|
AA2 |
PIXEL16 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
B17 |
VCC2 |
|
D13 |
VSS |
|
J3 |
RESET |
|
R3 |
PIXEL6 |
|
AA3 |
CRT_VSYNC |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
B18 |
INTR |
|
D14 |
VSS |
|
J4 |
VSS |
|
R4 |
VSS |
|
AA4 |
VSS |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
B19 |
AD3 |
|
D15 |
VSS |
|
J23 |
VSS |
|
R23 |
VSS |
|
AA23 |
VSS |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
B20 |
VCC3 |
|
D16 |
VSS |
|
J24 |
MD41 |
|
R24 |
WEB# |
|
AA24 |
MA1 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
B21 |
TEST1 |
|
D17 |
VCC2 |
|
J25 |
MD10 |
|
R25 |
WEA# |
|
AA25 |
MA2 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
B22 |
TEST3 |
|
D18 |
VSS |
|
J26 |
MD42 |
|
R26 |
CASB# |
|
AA26 |
MA3 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Processor GXm Geode™
Revision 3.1 |
15 |
www.national.com |
Geode™ GXm Processor
Signal Definitions (Continued)
|
|
Table 2-2. |
352 BGA Pin Assignments - Sorted by Pin Number (Continued) |
|
||||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Pin |
|
|
|
Pin |
|
|
Pin |
|
|
Pin |
|
|
Pin |
|
No. |
Signal Name |
|
|
No. |
Signal Name |
|
No. |
Signal Name |
|
No. |
Signal Name |
|
No. |
Signal Name |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
AB1 |
DCLK |
|
|
AC16 |
VSS |
|
AD13 |
MD56 |
|
AE10 |
VCC3 |
|
AF7 |
VCC2 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
AB2 |
PIXEL17 |
|
|
AC17 |
VCC2 |
|
AD14 |
MD55 |
|
AE11 |
MD28 |
|
AF8 |
SDCLK_OUT |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
AB3 |
VID_DATA6 |
|
|
AC18 |
VSS |
|
AD15 |
MD22 |
|
AE12 |
MD58 |
|
AF9 |
MD30 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
AB4 |
VID_DATA7 |
|
|
AC19 |
VSS |
|
AD16 |
CKEB |
|
AE13 |
MD25 |
|
AF10 |
VCC3 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
AB23 |
MA4 |
|
|
AC20 |
VCC3 |
|
AD17 |
VCC2 |
|
AE14 |
MD24 |
|
AF11 |
MD60 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
AB24 |
MA5 |
|
|
AC21 |
VSS |
|
AD18 |
MD51 |
|
AE15 |
MD54 |
|
AF12 |
MD27 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
AB25 |
MA6 |
|
|
AC22 |
DQM6 |
|
AD19 |
MD18 |
|
AE16 |
MD21 |
|
AF13 |
MD57 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
AB26 |
MA7 |
|
|
AC23 |
VSS |
|
AD20 |
VCC3 |
|
AE17 |
VCC2 |
|
AF14 |
VSS |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
AC1 |
PCLK |
|
|
AC24 |
MA8 |
|
AD21 |
MD48 |
|
AE18 |
MD20 |
|
AF15 |
MD23 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
AC2 |
FLT# |
|
|
AC25 |
MA9 |
|
AD22 |
DQM3 |
|
AE19 |
MD50 |
|
AF16 |
MD53 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
AC3 |
VID_DATA4 |
|
|
AC26 |
MA10 |
|
AD23 |
CS1# |
|
AE20 |
VCC3 |
|
AF17 |
VCC2 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
AC4 |
VSS |
|
|
AD1 |
VID_RDY |
|
AD24 |
MA11 |
|
AE21 |
MD17 |
|
AF18 |
MD52 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
AC5 |
VOLDET |
|
|
AD2 |
VID_DATA5 |
|
AD25 |
BA0 |
|
AE22 |
DQM7 |
|
AF19 |
MD19 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
AC6 |
VSS |
|
|
AD3 |
VID_DATA3 |
|
AD26 |
BA1 |
|
AE23 |
CS3# |
|
AF20 |
VCC3 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
AC7 |
VCC2 |
|
|
AD4 |
VID_DATA0 |
|
AE1 |
VSS |
|
AE24 |
MA12 |
|
AF21 |
MD49 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
AC8 |
VSS |
|
|
AD5 |
ENA_DISP |
|
AE2 |
VSS |
|
AE25 |
VSS |
|
AF22 |
MD16 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
AC9 |
VSS |
|
|
AD6 |
MD63 |
|
AE3 |
VID_DATA2 |
|
AE26 |
VSS |
|
AF23 |
DQM2 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
AC10 |
VCC3 |
|
|
AD7 |
VCC2 |
|
AE4 |
SDCLK3 |
|
AF1 |
VSS |
|
AF24 |
CKEA |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
AC11 |
VSS |
|
|
AD8 |
MD62 |
|
AE5 |
SDCLK1 |
|
AF2 |
VSS |
|
AF25 |
VSS |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
AC12 |
VSS |
|
|
AD9 |
MD29 |
|
AE6 |
RW_CLK |
|
AF3 |
VID_DATA1 |
|
AF26 |
VSS |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
AC13 |
VSS |
|
|
AD10 |
VCC3 |
|
AE7 |
VCC2 |
|
AF4 |
SDCLK0 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
AC14 |
VSS |
|
|
AD11 |
MD59 |
|
AE8 |
SDCLK_IN |
|
AF5 |
SDCLK2 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
AC15 |
VSS |
|
|
AD12 |
MD26 |
|
AE9 |
MD61 |
|
AF6 |
MD31 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
www.national.com |
16 |
Revision 3.1 |
Signal Definitions (Continued)
Table 2-3. 352 BGA Pin Assignments - Sorted Alphabetically by Signal Name
Signal Name |
Type |
Pin No. |
|
Signal Name |
Type |
Pin No. |
|
Signal Name |
Type |
Pin No. |
|
Signal Name |
Type |
Pin No. |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
AD0 |
I/O |
A21 |
|
DQM0 |
O |
T24 |
|
MD20 |
I/O |
AE18 |
|
PIXEL6 |
O |
R3 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
AD1 |
I/O |
A22 |
|
DQM1 |
O |
T26 |
|
MD21 |
I/O |
AE16 |
|
PIXEL7 |
O |
T1 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
AD2 |
I/O |
A19 |
|
DQM2 |
O |
AF23 |
|
MD22 |
I/O |
AD15 |
|
PIXEL8 |
O |
T2 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
AD3 |
I/O |
B19 |
|
DQM3 |
O |
AD22 |
|
MD23 |
I/O |
AF15 |
|
PIXEL9 |
O |
T3 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
AD4 |
I/O |
A18 |
|
DQM4 |
O |
T25 |
|
MD24 |
I/O |
AE14 |
|
PIXEL10 |
O |
V1 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
AD5 |
I/O |
C18 |
|
DQM5 |
O |
V24 |
|
MD25 |
I/O |
AE13 |
|
PIXEL11 |
O |
V2 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
AD6 |
I/O |
A16 |
|
DQM6 |
O |
AC22 |
|
MD26 |
I/O |
AD12 |
|
PIXEL12 |
O |
V3 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
AD7 |
I/O |
B16 |
|
DQM7 |
O |
AE22 |
|
MD27 |
I/O |
AF12 |
|
PIXEL13 |
O |
W1 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
AD8 |
I/O |
C16 |
|
ENA_DISP |
O |
AD5 |
|
MD28 |
I/O |
AE11 |
|
PIXEL14 |
O |
W3 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
AD9 |
I/O |
B15 |
|
FLT# |
I |
AC2 |
|
MD29 |
I/O |
AD9 |
|
PIXEL15 |
O |
AA1 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
AD10 |
I/O |
C15 |
|
FP_HSYNC |
O |
L2 |
|
MD30 |
I/O |
AF9 |
|
PIXEL16 |
O |
AA2 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
AD11 |
I/O |
A14 |
|
FP_VSYNC |
O |
J1 |
|
MD31 |
I/O |
AF6 |
|
PIXEL17 |
O |
AB2 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
AD12 |
I/O |
B14 |
|
FRAME# |
s/t/s |
A8 (PU) |
|
MD32 |
I/O |
C23 |
|
RASA# |
O |
W24 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
AD13 |
I/O |
C14 |
|
GNT0# |
O |
D1 |
|
MD33 |
I/O |
B24 |
|
RASB# |
O |
W25 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
AD14 |
I/O |
B13 |
|
GNT1# |
O |
F2 |
|
MD34 |
I/O |
C24 |
|
REQ0# |
I |
E3 (PU) |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
AD15 |
I/O |
A12 |
|
GNT2# |
O |
E1 |
|
MD35 |
I/O |
C26 |
|
REQ1# |
I |
H3 (PU) |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
AD16 |
I/O |
A6 |
|
INTR |
I |
B18 |
|
MD36 |
I/O |
D25 |
|
REQ2# |
I |
D3 (PU) |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
AD17 |
I/O |
C8 |
|
IRDY# |
s/t/s |
C9 (PU) |
|
MD37 |
I/O |
E26 |
|
RESET |
I |
J3 |
AD18 |
I/O |
B6 |
|
IRQ13 |
O |
C22 |
|
MD38 |
I/O |
F24 |
|
RW_CLK |
O |
AE6 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
AD19 |
I/O |
C6 |
|
LOCK# |
s/t/s |
B11 (PU) |
|
MD39 |
I/O |
F26 |
|
SDCLK_IN |
I |
AE8 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
AD20 |
I/O |
E4 |
|
MA0 |
O |
W26 |
|
MD40 |
I/O |
H25 |
|
SDCLK_OUT |
O |
AF8 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
AD21 |
I/O |
A5 |
|
MA1 |
O |
AA24 |
|
MD41 |
I/O |
J24 |
|
SDCLK0 |
O |
AF4 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
AD22 |
I/O |
B5 |
|
MA2 |
O |
AA25 |
|
MD42 |
I/O |
J26 |
|
SDCLK1 |
O |
AE5 |
AD23 |
I/O |
C5 |
|
MA3 |
O |
AA26 |
|
MD43 |
I/O |
L25 |
|
SDCLK2 |
O |
AF5 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
AD24 |
I/O |
A4 |
|
MA4 |
O |
AB23 |
|
MD44 |
I/O |
M24 |
|
SDCLK3 |
O |
AE4 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
AD25 |
I/O |
B4 |
|
MA5 |
O |
AB24 |
|
MD45 |
I/O |
M26 |
|
SERIALP |
O |
L3 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
AD26 |
I/O |
C4 |
|
MA6 |
O |
AB25 |
|
MD46 |
I/O |
N25 |
|
SERR# |
OD |
C12 (PU) |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
AD27 |
I/O |
A3 |
|
MA7 |
O |
AB26 |
|
MD47 |
I/O |
P24 |
|
SMI# |
I |
C19 |
AD28 |
I/O |
B3 |
|
MA8 |
O |
AC24 |
|
MD48 |
I/O |
AD21 |
|
STOP# |
s/t/s |
C11 (PU) |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
AD29 |
I/O |
C1 |
|
MA9 |
O |
AC25 |
|
MD49 |
I/O |
AF21 |
|
SUSP# |
I |
H2 (PU) |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
AD30 |
I/O |
C3 |
|
MA10 |
O |
AC26 |
|
MD50 |
I/O |
AE19 |
|
SUSPA# |
O |
E2 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
AD31 |
I/O |
C2 |
|
MA11 |
O |
AD24 |
|
MD51 |
I/O |
AD18 |
|
SYSCLK |
I |
P26 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
BA0 |
O |
AD25 |
|
MA12 |
O |
AE24 |
|
MD52 |
I/O |
AF18 |
|
TCLK |
I |
J2 (PU) |
BA1 |
O |
AD26 |
|
MD0 |
I/O |
D22 |
|
MD53 |
I/O |
AF16 |
|
TDI |
I |
D2 (PU) |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
CASA# |
O |
P25 |
|
MD1 |
I/O |
B23 |
|
MD54 |
I/O |
AE15 |
|
TDN |
O |
D26 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
CASB# |
O |
R26 |
|
MD2 |
I/O |
A24 |
|
MD55 |
I/O |
AD14 |
|
TDO |
O |
F1 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
C/BE0# |
I/O |
A15 |
|
MD3 |
I/O |
C25 |
|
MD56 |
I/O |
AD13 |
|
TDP |
O |
E24 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
C/BE1# |
I/O |
C13 |
|
MD4 |
I/O |
D24 |
|
MD57 |
I/O |
AF13 |
|
TEST |
I |
F3 (PD) |
C/BE2# |
I/O |
B8 |
|
MD5 |
I/O |
E25 |
|
MD58 |
I/O |
AE12 |
|
TEST0 |
O |
C21 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
C/BE3# |
I/O |
D5 |
|
MD6 |
I/O |
E23 |
|
MD59 |
I/O |
AD11 |
|
TEST1 |
O |
B21 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
CKEA |
O |
AF24 |
|
MD7 |
I/O |
F25 |
|
MD60 |
I/O |
AF11 |
|
TEST2 |
O |
A23 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
CKEB |
O |
AD16 |
|
MD8 |
I/O |
H24 |
|
MD61 |
I/O |
AE9 |
|
TEST3 |
O |
B22 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
CLKMODE0 |
I |
M3 |
|
MD9 |
I/O |
H26 |
|
MD62 |
I/O |
AD8 |
|
TMS |
I |
H1 (PU) |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
CLKMODE1 |
I |
L1 |
|
MD10 |
I/O |
J25 |
|
MD63 |
I/O |
AD6 |
|
TRDY# |
s/t/s |
B9 (PU) |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
CLKMODE2 |
I |
M1 |
|
MD11 |
I/O |
L24 |
|
PAR |
I/O |
B12 |
|
VCC2 |
PWR |
A7 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
CRT_HSYNC |
O |
W2 |
|
MD12 |
I/O |
L26 |
|
PCLK |
O |
AC1 |
|
VCC2 |
PWR |
A17 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
CRT_VSYNC |
O |
AA3 |
|
MD13 |
I/O |
M25 |
|
PERR# |
s/t/s |
A11 (PU) |
|
VCC2 |
PWR |
B7 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
CS0# |
O |
V26 |
|
MD14 |
I/O |
N24 |
|
PIXEL0 |
O |
N3 |
|
VCC2 |
PWR |
B17 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
CS1# |
O |
AD23 |
|
MD15 |
I/O |
N26 |
|
PIXEL1 |
O |
N2 |
|
VCC2 |
PWR |
C7 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
CS2# |
O |
V25 |
|
MD16 |
I/O |
AF22 |
|
PIXEL2 |
O |
P3 |
|
VCC2 |
PWR |
C17 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
CS3# |
O |
AE23 |
|
MD17 |
I/O |
AE21 |
|
PIXEL3 |
O |
P2 |
|
VCC2 |
PWR |
D7 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
DCLK |
I |
AB1 |
|
MD18 |
I/O |
AD19 |
|
PIXEL4 |
O |
R1 |
|
VCC2 |
PWR |
D17 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
DEVSEL# |
s/t/s |
A9 (PU) |
|
MD19 |
I/O |
AF19 |
|
PIXEL5 |
O |
R2 |
|
VCC2 |
PWR |
K1 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Processor GXm Geode™
Revision 3.1 |
17 |
www.national.com |
Geode™ GXm Processor
Signal Definitions (Continued)
Table 2-3. 352 BGA Pin Assignments - Sorted Alphabetically by Signal Name (Continued)
Signal Name |
Type |
Pin No. |
|
Signal Name |
Type |
Pin No. |
|
Signal Name |
Type |
Pin No. |
|
Signal Name |
Type |
Pin No. |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
VCC2 |
PWR |
K2 |
|
VCC3 |
PWR |
G25 |
|
VSS |
GND |
B25 |
|
VSS |
GND |
W4 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
VCC2 |
PWR |
K3 |
|
VCC3 |
PWR |
G26 |
|
VSS |
GND |
B26 |
|
VSS |
GND |
W23 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
VCC2 |
PWR |
K4 |
|
VCC3 |
PWR |
U1 |
|
VSS |
GND |
D4 |
|
VSS |
GND |
AA4 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
VCC2 |
PWR |
K23 |
|
VCC3 |
PWR |
U2 |
|
VSS |
GND |
D6 |
|
VSS |
GND |
AA23 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
VCC2 |
PWR |
K24 |
|
VCC3 |
PWR |
U3 |
|
VSS |
GND |
D8 |
|
VSS |
GND |
AC4 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
VCC2 |
PWR |
K25 |
|
VCC3 |
PWR |
U4 |
|
VSS |
GND |
D9 |
|
VSS |
GND |
AC6 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
VCC2 |
PWR |
K26 |
|
VCC3 |
PWR |
U23 |
|
VSS |
GND |
D11 |
|
VSS |
GND |
AC8 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
VCC2 |
PWR |
Y1 |
|
VCC3 |
PWR |
U24 |
|
VSS |
GND |
D12 |
|
VSS |
GND |
AC9 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
VCC2 |
PWR |
Y2 |
|
VCC3 |
PWR |
U25 |
|
VSS |
GND |
D13 |
|
VSS |
GND |
AC11 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
VCC2 |
PWR |
Y3 |
|
VCC3 |
PWR |
U26 |
|
VSS |
GND |
D14 |
|
VSS |
GND |
AC12 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
VCC2 |
PWR |
Y4 |
|
VCC3 |
PWR |
AC10 |
|
VSS |
GND |
D15 |
|
VSS |
GND |
AC13 |
|
|
|
|
|
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|
|
|
|
|
|
|
|
VCC2 |
PWR |
Y23 |
|
VCC3 |
PWR |
AC20 |
|
VSS |
GND |
D16 |
|
VSS |
GND |
AC14 |
|
|
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|
|
|
|
|
|
VCC2 |
PWR |
Y24 |
|
VCC3 |
PWR |
AD10 |
|
VSS |
GND |
D18 |
|
VSS |
GND |
AC15 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
VCC2 |
PWR |
Y25 |
|
VCC3 |
PWR |
AD20 |
|
VSS |
GND |
D19 |
|
VSS |
GND |
AC16 |
|
|
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|
|
|
|
|
VCC2 |
PWR |
Y26 |
|
VCC3 |
PWR |
AE10 |
|
VSS |
GND |
D21 |
|
VSS |
GND |
AC18 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
VCC2 |
PWR |
AC7 |
|
VCC3 |
PWR |
AE20 |
|
VSS |
GND |
D23 |
|
VSS |
GND |
AC19 |
|
|
|
|
|
|
|
|
|
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|
|
|
|
|
VCC2 |
PWR |
AC17 |
|
VCC3 |
PWR |
AF10 |
|
VSS |
GND |
F4 |
|
VSS |
GND |
AC21 |
|
|
|
|
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|
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|
|
|
|
|
|
VCC2 |
PWR |
AD7 |
|
VCC3 |
PWR |
AF20 |
|
VSS |
GND |
F23 |
|
VSS |
GND |
AC23 |
|
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|
|
|
VCC2 |
PWR |
AD17 |
|
VID_CLK |
O |
P1 |
|
VSS |
GND |
H4 |
|
VSS |
GND |
AE1 |
|
|
|
|
|
|
|
|
|
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|
|
|
|
|
VCC2 |
PWR |
AE7 |
|
VID_DATA0 |
O |
AD4 |
|
VSS |
GND |
H23 |
|
VSS |
GND |
AE2 |
|
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|
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|
|
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|
|
|
|
VCC2 |
PWR |
AE17 |
|
VID_DATA1 |
O |
AF3 |
|
VSS |
GND |
J4 |
|
VSS |
GND |
AE25 |
|
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|
VCC2 |
PWR |
AF7 |
|
VID_DATA2 |
O |
AE3 |
|
VSS |
GND |
J23 |
|
VSS |
GND |
AE26 |
|
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|
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|
VCC2 |
PWR |
AF17 |
|
VID_DATA3 |
O |
AD3 |
|
VSS |
GND |
L4 |
|
VSS |
GND |
AF1 |
|
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|
|
|
VCC3 |
PWR |
A10 |
|
VID_DATA4 |
O |
AC3 |
|
VSS |
GND |
L23 |
|
VSS |
GND |
AF2 |
|
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|
|
|
|
VCC3 |
PWR |
A20 |
|
VID_DATA5 |
O |
AD2 |
|
VSS |
GND |
M4 |
|
VSS |
GND |
AF14 |
|
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|
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|
VCC3 |
PWR |
B10 |
|
VID_DATA6 |
O |
AB3 |
|
VSS |
GND |
M23 |
|
VSS |
GND |
AF25 |
|
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|
|
|
|
VCC3 |
PWR |
B20 |
|
VID_DATA7 |
O |
AB4 |
|
VSS |
GND |
N1 |
|
VSS |
GND |
AF26 |
|
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|
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|
VCC3 |
PWR |
C10 |
|
VID_RDY |
I |
AD1 |
|
VSS |
GND |
N4 |
|
WEA# |
O |
R25 |
|
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|
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|
|
|
|
|
|
VCC3 |
PWR |
C20 |
|
VID_VAL |
O |
M2 |
|
VSS |
GND |
N23 |
|
WEB# |
O |
R24 |
|
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|
|
|
|
|
|
|
|
|
|
VCC3 |
PWR |
D10 |
|
VOLDET |
O |
AC5 |
|
VSS |
GND |
P4 |
|
Note: PU/PD indicates pin is |
||
VCC3 |
PWR |
D20 |
|
VSS |
GND |
A1 |
|
VSS |
GND |
P23 |
|
internally connected to |
||
VCC3 |
PWR |
G1 |
|
VSS |
GND |
A2 |
|
VSS |
GND |
R4 |
|
a 20-kohm pull-up/- |
||
|
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|
|
down resistor. |
|
|
VCC3 |
PWR |
G2 |
|
VSS |
GND |
A13 |
|
VSS |
GND |
R23 |
|
|||
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|||||||||
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|
VCC3 |
PWR |
G3 |
|
VSS |
GND |
A25 |
|
VSS |
GND |
T4 |
|
|
|
|
|
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|
|
|
|
VCC3 |
PWR |
G4 |
|
VSS |
GND |
A26 |
|
VSS |
GND |
T23 |
|
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|
VCC3 |
PWR |
G23 |
|
VSS |
GND |
B1 |
|
VSS |
GND |
V4 |
|
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|
VCC3 |
PWR |
G24 |
|
VSS |
GND |
B2 |
|
VSS |
GND |
V23 |
|
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|
www.national.com |
18 |
Revision 3.1 |
Signal Definitions (Continued)
Index Corner |
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1 |
2 |
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3 |
4 |
5 |
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6 |
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7 |
8 |
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9 |
10 |
11 |
12 |
13 |
14 |
15 |
16 |
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17 |
18 |
19 |
20 |
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21 |
22 |
23 |
24 |
25 |
26 |
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27 |
28 |
29 |
30 |
31 |
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32 |
33 |
|
34 |
35 |
36 |
37 |
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A |
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A |
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|
VCC3 |
AD25 |
|
VSS |
|
VCC2 |
AD16 |
|
VCC3 |
STOP# |
SERR# |
|
VSS |
|
AD11 |
|
AD8 |
VCC3 |
|
AD2 |
VCC2 |
VSS |
|
TST0 |
|
VCC3 |
|
VSS |
|||||||||||||||||
B |
|
|
|
AD27 |
CBE3# |
|
AD21 |
AD19 |
CBE2# |
TRDY# |
LOCK# |
CBE1# |
AD13 |
|
AD9 |
|
AD6 |
|
AD3 |
|
SMI# |
|
AD1 |
|
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TST2 |
MD33 |
|
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B |
||||||||||||||||
VSS |
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MD2 |
||||||||||||||||||||||||||||||||||||
C |
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C |
VCC3 |
|
AD31 |
AD26 |
|
AD23 |
VCC2 |
AD18 |
FRAME# |
VSS |
PAR |
VCC3 |
AD10 |
|
VSS |
|
AD4 |
|
|
AD0 |
VCC2 |
IRQ13 |
MD1 |
|
MD34 |
|
VCC3 |
||||||||||||||||||||
D |
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D |
AD30 |
|
AD29 |
AD24 |
|
AD22 |
AD20 |
AD17 |
IRDY# |
PERR# |
AD14 |
|
AD12 |
|
AD7 |
|
INTR |
|
TST1 |
TST3 |
MD0 |
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MD32 |
MD3 |
MD35 |
|||||||||||||||||||||
E |
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E |
REQ0# |
|
REQ2# |
AD28 |
|
VSS |
|
VCC2 |
VCC2 |
|
VSS DEVSEL# |
AD15 |
|
VSS |
|
CBE0# |
AD5 |
|
VSS |
|
VCC2 |
VCC2 |
VSS |
|
MD4 |
|
MD36 |
|
TDN |
||||||||||||||||||
F |
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F |
GNT0# |
|
TDI |
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MD5 |
|
TDP |
|||||
G |
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G |
VSS |
CLKMODE2 |
VSS |
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VSS |
|
MD37 |
|
VSS |
||||||
H |
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H |
GNT2# |
|
SUSPA# |
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MD6 |
MD38 |
|||||||
J |
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J |
TDO |
|
VSS |
TEST |
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VCC2 |
|
VSS |
|
MD7 |
|||||
K |
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K |
REQ1# |
|
GNT1# |
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MD39 |
MD8 |
|||||||
L |
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L |
VCC2 |
|
VCC2 |
VCC2 |
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VCC2 |
|
VCC2 |
|
VCC2 |
|||||
M |
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M |
RESET |
|
SUSP# |
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MD40 |
MD9 |
|||||||
N |
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N |
VCC3 |
|
TMS |
VSS |
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VSS |
|
MD41 |
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VCC3 |
|||||
P |
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P |
FPVSYN |
|
TCK |
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MD10 |
MD42 |
|||||||
Q |
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Q |
SERIALP |
VSS |
NC |
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MD11 |
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VSS |
|
MD43 |
|||||
R |
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R |
CKMD1 |
FPHSYN |
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MD44 |
MD12 |
||||||||
S |
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S |
CKMD0 |
VID_VAL |
PIX0 |
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Geode™ GXm |
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MD14 |
|
MD13 |
|
MD45 |
|||||||||||||||||
T |
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T |
||||||||||||
PIX1 |
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PIX2 |
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MD15 |
MD46 |
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U |
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Processor |
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U |
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VSS |
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VCC3 |
VSS |
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VSS |
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VCC3 |
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VSS |
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PIX3 |
VID_CLK |
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SYSCLK MD47 |
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V |
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V |
W |
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W |
PIX6 |
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PIX5 |
PIX4 |
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320 SPGA - Top View |
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WEA# |
WEB# |
CASA# |
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X |
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X |
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NC |
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PIX9 |
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DQM0 |
CASB# |
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Y |
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Y |
PIX8 |
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VSS |
PIX7 |
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DQM1 |
VSS |
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DQM4 |
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Z |
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Z |
NC |
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PIX10 |
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CS2# |
DQM5 |
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AA |
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AA |
VCC3 |
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PIX11 |
VSS |
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VSS |
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CS0# |
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VCC3 |
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AB |
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AB |
PIX12 |
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PIX13 |
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RASB# |
RASA# |
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AC |
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AC |
VCC2 |
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VCC2 |
VCC2 |
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VCC2 |
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VCC2 |
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VCC2 |
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AD |
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AD |
CRTHSYN |
DCLK |
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MA2 |
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MA0 |
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AE |
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AE |
PIX14 |
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VSS |
VCC2 |
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VCC2 |
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VSS |
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MA1 |
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AF |
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AF |
PIX15 |
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PIX16 |
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MA4 |
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MA3 |
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AG |
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AG |
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VSS |
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PIX17 |
VSS |
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VSS |
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MA5 |
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VSS |
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AH |
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AH |
CRTVSYN |
VDAT6 |
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MA10 |
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MA8 |
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MA6 |
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AJ |
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AJ |
PCLK |
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FLT# |
VDAT5 |
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VSS |
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VCC2 |
MD31 |
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VSS |
MD60 |
MD57 |
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VSS |
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MD22 |
MD52 |
VSS |
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VCC2 |
VCC2 |
VSS |
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BA1 |
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MA9 |
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MA7 |
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AK |
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AK |
VRDY |
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VSS |
VDAT0 |
SDCLK0 |
SDCLK2 SDCLKIN |
MD29 |
MD27 |
MD56 |
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MD55 |
MD21 |
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MD20 |
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MD50 |
MD16 |
DQM3 |
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CS3# |
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VSS |
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BA0 |
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AL |
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AL |
VCC2 |
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VDAT4 |
VDAT2 |
SDCLK1 |
VCC2 |
RWCLK SDCLKOUT |
VSS |
MD58 |
VCC3 |
MD23 |
|
VSS |
MD19 |
MD49 |
VCC2 |
DQM6 |
CKEA |
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MA11 |
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VCC3 |
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AM |
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AM |
VDAT7 |
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VDAT3 |
ENDIS |
SDCLK3 |
MD63 |
MD30 |
MD61 |
MD59 |
MD25 |
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MD24 |
MD53 |
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MD51 |
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MD18 |
MD48 |
DQM7 |
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DQM2 |
MA12 |
VOLDET |
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AN |
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AN |
VSS |
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VCC2 |
VDAT1 |
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VSS |
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VCC2 |
MD62 |
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VCC3 |
MD28 |
MD26 |
|
VSS |
|
MD54 |
CKEB VCC3 |
MD17 |
VCC2 |
VSS |
|
CS1# |
|
VCC3 |
|
VSS |
||||||||||||||||||||
1 |
2 |
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3 |
4 |
5 |
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6 |
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7 |
8 |
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9 |
10 |
11 |
12 |
13 |
14 |
15 |
16 |
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17 |
18 |
19 |
20 |
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21 |
22 |
23 |
24 |
25 |
26 |
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27 |
28 |
29 |
30 |
31 |
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32 |
33 |
|
34 |
35 |
36 |
37 |
Note: Signal names have been abbreviated in this figure due to space constraints.
= Denotes GND terminal
= Denotes PWR terminal (VCC2 = VCC_CORE; VCC3 = VCC_IO)
Figure 2-3. 320 SPGA Pin Assignment Diagram
For order information refer to Section A.1 “Order Information” on page 236.
Processor GXm Geode™
Revision 3.1 |
19 |
www.national.com |
Geode™ GXm Processor
Signal Definitions (Continued)
Table 2-4. 320 SPGA Pin Assignments - Sorted by Pin Number
Pin |
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Pin |
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Pin |
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Pin |
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Pin |
|
No. |
Signal Name |
|
No. |
Signal Name |
|
No. |
Signal Name |
|
No. |
Signal Name |
|
No. |
Signal Name |
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A3 |
VCC3 |
|
C25 |
AD4 |
|
G1 |
VSS |
|
R34 |
MD44 |
|
AB2 |
PIXEL12 |
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A5 |
AD25 |
|
C27 |
AD0 |
|
G3 |
CLKMODE2 |
|
R36 |
MD12 |
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AB4 |
PIXEL13 |
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A7 |
VSS |
|
C29 |
VCC2 |
|
G5 |
VSS |
|
S1 |
CLKMODE0 |
|
AB34 |
RASB# |
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A9 |
VCC2 |
|
C31 |
IRQ13 |
|
G33 |
VSS |
|
S3 |
VID_VAL |
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AB36 |
RASA# |
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A11 |
AD16 |
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C33 |
MD1 |
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G35 |
MD37 |
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S5 |
PIXEL0 |
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AC1 |
VCC2 |
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A13 |
VCC3 |
|
C35 |
MD34 |
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G37 |
VSS |
|
S33 |
MD14 |
|
AC3 |
VCC2 |
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A15 |
STOP# |
|
C37 |
VCC3 |
|
H2 |
GNT2# |
|
S35 |
MD13 |
|
AC5 |
VCC2 |
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A17 |
SERR# |
|
D2 |
AD30 |
|
H4 |
SUSPA# |
|
S37 |
MD45 |
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AC33 |
VCC2 |
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A19 |
VSS |
|
D4 |
AD29 |
|
H34 |
MD6 |
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T2 |
PIXEL1 |
|
AC35 |
VCC2 |
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A21 |
AD11 |
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D6 |
AD24 |
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H36 |
MD38 |
|
T4 |
PIXEL2 |
|
AC37 |
VCC2 |
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A23 |
AD8 |
|
D8 |
AD22 |
|
J1 |
TDO |
|
T34 |
MD15 |
|
AD2 |
CRT_HSYNC |
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A25 |
VCC3 |
|
D10 |
AD20 |
|
J3 |
VSS |
|
T36 |
MD46 |
|
AD4 |
DCLK |
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A27 |
AD2 |
|
D12 |
AD17 |
|
J5 |
TEST |
|
U1 |
VSS |
|
AD34 |
MA2 |
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A29 |
VCC2 |
|
D14 |
IRDY# |
|
J33 |
VCC2 |
|
U3 |
VCC3 |
|
AD36 |
MA0 |
|
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|
A31 |
VSS |
|
D16 |
PERR# |
|
J35 |
VSS |
|
U5 |
VSS |
|
AE1 |
PIXEL14 |
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|
A33 |
TEST0 |
|
D18 |
AD14 |
|
J37 |
MD7 |
|
U33 |
VSS |
|
AE3 |
VSS |
|
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|
A35 |
VCC3 |
|
D20 |
AD12 |
|
K2 |
REQ1# |
|
U35 |
VCC3 |
|
AE5 |
VCC2 |
|
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|
A37 |
VSS |
|
D22 |
AD7 |
|
K4 |
GNT1# |
|
U37 |
VSS |
|
AE33 |
VCC2 |
|
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|
|
B2 |
VSS |
|
D24 |
INTR |
|
K34 |
MD39 |
|
V2 |
PIXEL3 |
|
AE35 |
VSS |
|
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|
|
B4 |
AD27 |
|
D26 |
TEST1 |
|
K36 |
MD8 |
|
V4 |
VID_CLK |
|
AE37 |
MA1 |
|
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|
|
B6 |
C/BE3# |
|
D28 |
TEST3 |
|
L1 |
VCC2 |
|
V34 |
SYSCLK |
|
AF2 |
PIXEL15 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
B8 |
AD21 |
|
D30 |
MD0 |
|
L3 |
VCC2 |
|
V36 |
MD47 |
|
AF4 |
PIXEL16 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
B10 |
AD19 |
|
D32 |
MD32 |
|
L5 |
VCC2 |
|
W1 |
PIXEL6 |
|
AF34 |
MA4 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
B12 |
C/BE2# |
|
D34 |
MD3 |
|
L33 |
VCC2 |
|
W3 |
PIXEL5 |
|
AF36 |
MA3 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
B14 |
TRDY# |
|
D36 |
MD35 |
|
L35 |
VCC2 |
|
W5 |
PIXEL4 |
|
AG1 |
VSS |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
B16 |
LOCK# |
|
E1 |
REQ0# |
|
L37 |
VCC2 |
|
W33 |
WEA# |
|
AG3 |
PIXEL17 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
B18 |
C/BE1# |
|
E3 |
REQ2# |
|
M2 |
RESET |
|
W35 |
WEB# |
|
AG5 |
VSS |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
B20 |
AD13 |
|
E5 |
AD28 |
|
M4 |
SUSP# |
|
W37 |
CASA# |
|
AG33 |
VSS |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
B22 |
AD9 |
|
E7 |
VSS |
|
M34 |
MD40 |
|
X2 |
NC |
|
AG35 |
MA5 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
B24 |
AD6 |
|
E9 |
VCC2 |
|
M36 |
MD9 |
|
X4 |
PIXEL9 |
|
AG37 |
VSS |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
B26 |
AD3 |
|
E11 |
VCC2 |
|
N1 |
VCC3 |
|
X34 |
DQM0 |
|
AH2 |
CRT_VSYNC |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
B28 |
SMI# |
|
E13 |
VSS |
|
N3 |
TMS |
|
X36 |
CASB# |
|
AH4 |
VID_DATA6 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
B30 |
AD1 |
|
E15 |
DEVSEL# |
|
N5 |
VSS |
|
Y1 |
PIXEL8 |
|
AH32 |
MA10 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
B32 |
TEST2 |
|
E17 |
AD15 |
|
N33 |
VSS |
|
Y3 |
VSS |
|
AH34 |
MA8 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
B34 |
MD33 |
|
E19 |
VSS |
|
N35 |
MD41 |
|
Y5 |
PIXEL7 |
|
AH36 |
MA6 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
B36 |
MD2 |
|
E21 |
C/BE0# |
|
N37 |
VCC3 |
|
Y33 |
DQM1 |
|
AJ1 |
PCLK |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
C1 |
VCC3 |
|
E23 |
AD5 |
|
P2 |
FP_VSYNC |
|
Y35 |
VSS |
|
AJ3 |
FTL# |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
C3 |
AD31 |
|
E25 |
VSS |
|
P4 |
TCLK |
|
Y37 |
DQM4 |
|
AJ5 |
VID_DATA5 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
C5 |
AD26 |
|
E27 |
VCC2 |
|
P34 |
MD10 |
|
Z2 |
NC |
|
AJ7 |
VSS |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
C7 |
AD23 |
|
E29 |
VCC2 |
|
P36 |
MD42 |
|
Z4 |
PIXEL10 |
|
AJ9 |
VCC2 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
C9 |
VCC2 |
|
E31 |
VSS |
|
Q1 |
SERIALP |
|
Z34 |
CS2# |
|
AJ11 |
MD31 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
C11 |
AD18 |
|
E33 |
MD4 |
|
Q3 |
VSS |
|
Z36 |
DQM5 |
|
AJ13 |
VSS |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
C13 |
FRAME# |
|
E35 |
MD36 |
|
Q5 |
NC |
|
AA1 |
VCC3 |
|
AJ15 |
MD60 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
C15 |
VSS |
|
E37 |
TDN |
|
Q33 |
MD11 |
|
AA3 |
PIXEL11 |
|
AJ17 |
MD57 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
C17 |
PAR |
|
F2 |
GNT0# |
|
Q35 |
VSS |
|
AA5 |
VSS |
|
AJ19 |
VSS |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
C19 |
VCC3 |
|
F4 |
TDI |
|
Q37 |
MD43 |
|
AA33 |
VSS |
|
AJ21 |
MD22 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
C21 |
AD10 |
|
F34 |
MD5 |
|
R2 |
CLKMODE1 |
|
AA35 |
CS0# |
|
AJ23 |
MD52 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
C23 |
VSS |
|
F36 |
TDP |
|
R4 |
FP_HSYNC |
|
AA37 |
VCC3 |
|
AJ25 |
VSS |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
www.national.com |
20 |
Revision 3.1 |
Signal Definitions (Continued)
|
|
Table 2-4. |
320 SPGA Pin Assignments - Sorted by Pin Number (Continued) |
|
||||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Pin |
|
|
|
Pin |
|
|
Pin |
|
|
Pin |
|
|
Pin |
|
No. |
Signal Name |
|
|
No. |
Signal Name |
|
No. |
Signal Name |
|
No. |
Signal Name |
|
No. |
Signal Name |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
AJ27 |
VCC2 |
|
|
AK24 |
MD20 |
|
AL21 |
MD23 |
|
AM18 |
MD25 |
|
AN15 |
MD28 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
AJ29 |
VCC2 |
|
|
AK26 |
MD50 |
|
AL23 |
VSS |
|
AM20 |
MD24 |
|
AN17 |
MD26 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
AJ31 |
VSS |
|
|
AK28 |
MD16 |
|
AL25 |
MD19 |
|
AM22 |
MD53 |
|
AN19 |
VSS |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
AJ33 |
BA1 |
|
|
AK30 |
DQM3 |
|
AL27 |
MD49 |
|
AM24 |
MD51 |
|
AN21 |
MD54 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
AJ35 |
MA9 |
|
|
AK32 |
CS3# |
|
AL29 |
VCC2 |
|
AM26 |
MD18 |
|
AN23 |
CKEB |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
AJ37 |
MA7 |
|
|
AK34 |
VSS |
|
AL31 |
DQM6 |
|
AM28 |
MD48 |
|
AN25 |
VCC3 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
AK2 |
VID_RDY |
|
|
AK36 |
BA0 |
|
AL33 |
CKEA |
|
AM30 |
DQM7 |
|
AN27 |
MD17 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
AK4 |
VSS |
|
|
AL1 |
VCC2 |
|
AL35 |
MA11 |
|
AM32 |
DQM2 |
|
AN29 |
VCC2 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
AK6 |
VID_DATA0 |
|
|
AL3 |
VID_DATA4 |
|
AL37 |
VCC3 |
|
AM34 |
MA12 |
|
AN31 |
VSS |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
AK8 |
SDCLK0 |
|
|
AL5 |
VID_DATA2 |
|
AM2 |
VID_DATA7 |
|
AM36 |
VOLDET |
|
AN33 |
CS1# |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
AK10 |
SDCLK2 |
|
|
AL7 |
SDCLK1 |
|
AM4 |
VID_DATA3 |
|
AN1 |
VSS |
|
AN35 |
VCC3 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
AK12 |
SDCLK_IN |
|
|
AL9 |
VCC2 |
|
AM6 |
ENA_DISP |
|
AN3 |
VCC2 |
|
AN37 |
VSS |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
AK14 |
MD29 |
|
|
AL11 |
RW_CLK |
|
AM8 |
SDCLK3 |
|
AN5 |
VID_DATA1 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
AK16 |
MD27 |
|
|
AL13 |
SDCLK_OUT |
|
AM10 |
MD63 |
|
AN7 |
VSS |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
AK18 |
MD56 |
|
|
AL15 |
VSS |
|
AM12 |
MD30 |
|
AN9 |
VCC2 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
AK20 |
MD55 |
|
|
AL17 |
MD58 |
|
AM14 |
MD61 |
|
AN11 |
MD62 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
AK22 |
MD21 |
|
|
AL19 |
VCC3 |
|
AM16 |
MD59 |
|
AN13 |
VCC3 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Processor GXm Geode™
Revision 3.1 |
21 |
www.national.com |
Geode™ GXm Processor
Signal Definitions (Continued)
Table 2-5. 320 SPGA Pin Assignments - Sorted Alphabetically by Signal Name
Signal Name |
Type |
Pin. No. |
|
Signal Name |
Type |
Pin. No. |
|
Signal Name |
Type |
Pin. No. |
|
Signal Name |
Type |
Pin. No. |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
AD0 |
I/O |
C27 |
|
DQM0 |
O |
X34 |
|
MD20 |
I/O |
AK24 |
|
PIXEL3 |
O |
V2 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
AD1 |
I/O |
B30 |
|
DQM1 |
O |
Y33 |
|
MD21 |
I/O |
AK22 |
|
PIXEL4 |
O |
W5 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
AD2 |
I/O |
A27 |
|
DQM2 |
O |
AM32 |
|
MD22 |
I/O |
AJ21 |
|
PIXEL5 |
O |
W3 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
AD3 |
I/O |
B26 |
|
DQM3 |
O |
AK30 |
|
MD23 |
I/O |
AL21 |
|
PIXEL6 |
O |
W1 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
AD4 |
I/O |
C25 |
|
DQM4 |
O |
Y37 |
|
MD24 |
I/O |
AM20 |
|
PIXEL7 |
O |
Y5 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
AD5 |
I/O |
E23 |
|
DQM5 |
O |
Z36 |
|
MD25 |
I/O |
AM18 |
|
PIXEL8 |
O |
Y1 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
AD6 |
I/O |
B24 |
|
DQM6 |
O |
AL31 |
|
MD26 |
I/O |
AN17 |
|
PIXEL9 |
O |
X4 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
AD7 |
I/O |
D22 |
|
DQM7 |
O |
AM30 |
|
MD27 |
I/O |
AK16 |
|
PIXEL10 |
O |
Z4 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
AD8 |
I/O |
A23 |
|
ENA_DISP |
O |
AM6 |
|
MD28 |
I/O |
AN15 |
|
PIXEL11 |
O |
AA3 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
AD9 |
I/O |
B22 |
|
FLT# |
I |
AJ3 |
|
MD29 |
I/O |
AK14 |
|
PIXEL12 |
O |
AB2 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
AD10 |
I/O |
C21 |
|
FP_HSYNC |
O |
R4 |
|
MD30 |
I/O |
AM12 |
|
PIXEL13 |
O |
AB4 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
AD11 |
I/O |
A21 |
|
FP_VSYNC |
O |
P2 |
|
MD31 |
I/O |
AJ11 |
|
PIXEL14 |
O |
AE1 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
AD12 |
I/O |
D20 |
|
FRAME# |
s/t/s |
C13 (PU) |
|
MD32 |
I/O |
D32 |
|
PIXEL15 |
O |
AF2 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
AD13 |
I/O |
B20 |
|
GNT0# |
O |
F2 |
|
MD33 |
I/O |
B34 |
|
PIXEL16 |
O |
AF4 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
AD14 |
I/O |
D18 |
|
GNT1# |
O |
K4 |
|
MD34 |
I/O |
C35 |
|
PIXEL17 |
O |
AG3 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
AD15 |
I/O |
E17 |
|
GNT2# |
O |
H2 |
|
MD35 |
I/O |
D36 |
|
RASA# |
O |
AB36 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
AD16 |
I/O |
A11 |
|
INTR |
I |
D24 |
|
MD36 |
I/O |
E35 |
|
RASB# |
O |
AB34 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
AD17 |
I/O |
D12 |
|
IRDY# |
s/t/s |
D14 (PU) |
|
MD37 |
I/O |
G35 |
|
REQ0# |
I |
E1 (PU) |
AD18 |
I/O |
C11 |
|
IRQ13 |
O |
C31 |
|
MD38 |
I/O |
H36 |
|
REQ1# |
I |
K2 (PU) |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
AD19 |
I/O |
B10 |
|
LOCK# |
s/t/s |
B16 (PU) |
|
MD39 |
I/O |
K34 |
|
REQ2# |
I |
E3 (PU) |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
AD20 |
I/O |
D10 |
|
MA0 |
O |
AD36 |
|
MD40 |
I/O |
M34 |
|
RESET |
I |
M2 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
AD21 |
I/O |
B8 |
|
MA1 |
O |
AE37 |
|
MD41 |
I/O |
N35 |
|
RW_CLK |
O |
AL11 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
AD22 |
I/O |
D8 |
|
MA2 |
O |
AD34 |
|
MD42 |
I/O |
P36 |
|
SDCLK_IN |
I |
AK12 |
AD23 |
I/O |
C7 |
|
MA3 |
O |
AF36 |
|
MD43 |
I/O |
Q37 |
|
SDCLK_OUT |
O |
AL13 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
AD24 |
I/O |
D6 |
|
MA4 |
O |
AF34 |
|
MD44 |
I/O |
R34 |
|
SDCLK0 |
O |
AK8 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
AD25 |
I/O |
A5 |
|
MA5 |
O |
AG35 |
|
MD45 |
I/O |
S37 |
|
SDCLK1 |
O |
AL7 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
AD26 |
I/O |
C5 |
|
MA6 |
O |
AH36 |
|
MD46 |
I/O |
T36 |
|
SDCLK2 |
O |
AK10 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
AD27 |
I/O |
B4 |
|
MA7 |
O |
AJ37 |
|
MD47 |
I/O |
V36 |
|
SDCLK3 |
O |
AM8 |
AD28 |
I/O |
E5 |
|
MA8 |
O |
AH34 |
|
MD48 |
I/O |
AM28 |
|
SERIALP |
O |
Q1 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
AD29 |
I/O |
D4 |
|
MA9 |
O |
AJ35 |
|
MD49 |
I/O |
AL27 |
|
SERR# |
OD |
A17 (PU) |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
AD30 |
I/O |
D2 |
|
MA10 |
O |
AH32 |
|
MD50 |
I/O |
AK26 |
|
SMI# |
I |
B28 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
AD31 |
I/O |
C3 |
|
MA11 |
O |
AL35 |
|
MD51 |
I/O |
AM24 |
|
STOP# |
s/t/s |
A15 (PU) |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
BA0 |
O |
AK36 |
|
MA12 |
O |
AM34 |
|
MD52 |
I/O |
AJ23 |
|
SUSP# |
I |
M4 (PU) |
BA1 |
O |
AJ33 |
|
MD0 |
I/O |
D30 |
|
MD53 |
I/O |
AM22 |
|
SUSPA# |
O |
H4 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
CASA# |
O |
W37 |
|
MD1 |
I/O |
C33 |
|
MD54 |
I/O |
AN21 |
|
SYSCLK |
I |
V34 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
CASB# |
O |
X36 |
|
MD2 |
I/O |
B36 |
|
MD55 |
I/O |
AK20 |
|
TCLK |
I |
P4 (PU) |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
C/BE0# |
I/O |
E21 |
|
MD3 |
I/O |
D34 |
|
MD56 |
I/O |
AK18 |
|
TDI |
I |
F4 (PU) |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
C/BE1# |
I/O |
B18 |
|
MD4 |
I/O |
E33 |
|
MD57 |
I/O |
AJ17 |
|
TDN |
O |
E37 |
C/BE2# |
I/O |
B12 |
|
MD5 |
I/O |
F34 |
|
MD58 |
I/O |
AL17 |
|
TDO |
O |
J1 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
C/BE3# |
I/O |
B6 |
|
MD6 |
I/O |
H34 |
|
MD59 |
I/O |
AM16 |
|
TDP |
O |
F36 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
CKEA |
O |
AL33 |
|
MD7 |
I/O |
J37 |
|
MD60 |
I/O |
AJ15 |
|
TEST |
I |
J5 (PD) |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
CKEB |
O |
AN23 |
|
MD8 |
I/O |
K36 |
|
MD61 |
I/O |
AM14 |
|
TEST0 |
O |
A33 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
CLKMODE0 |
I |
S1 |
|
MD9 |
I/O |
M36 |
|
MD62 |
I/O |
AN11 |
|
TEST1 |
O |
D26 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
CLKMODE1 |
I |
R2 |
|
MD10 |
I/O |
P34 |
|
MD63 |
I/O |
AM10 |
|
TEST2 |
O |
B32 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
CLKMODE2 |
I |
G3 |
|
MD11 |
I/O |
Q33 |
|
NC |
|
Q5 |
|
TEST3 |
O |
D28 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
CRT_HSYNC |
O |
AD2 |
|
MD12 |
I/O |
R36 |
|
NC |
|
X2 |
|
TMS |
I |
N3 (PU) |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
CRT_VSYNC |
O |
AH2 |
|
MD13 |
I/O |
S35 |
|
NC |
|
Z2 |
|
TRDY# |
s/t/s |
B14 (PU) |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
CS0# |
O |
AA35 |
|
MD14 |
I/O |
S33 |
|
PAR |
I/O |
C17 |
|
VCC2 |
PWR |
A9 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
CS1# |
O |
AN33 |
|
MD15 |
I/O |
T34 |
|
PCLK |
O |
AJ1 |
|
VCC2 |
PWR |
A29 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
CS2# |
O |
Z34 |
|
MD16 |
I/O |
AK28 |
|
PERR# |
s/t/s |
D16 (PU) |
|
VCC2 |
PWR |
C9 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
CS3# |
O |
AK32 |
|
MD17 |
I/O |
AN27 |
|
PIXEL0 |
O |
S5 |
|
VCC2 |
PWR |
C29 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
DCLK |
I |
AD4 |
|
MD18 |
I/O |
AM26 |
|
PIXEL1 |
O |
T2 |
|
VCC2 |
PWR |
E9 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
DEVSEL# |
s/t/s |
E15 (PU) |
|
MD19 |
I/O |
AL25 |
|
PIXEL2 |
O |
T4 |
|
VCC2 |
PWR |
E11 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
www.national.com |
22 |
Revision 3.1 |
Signal Definitions (Continued)
Table 2-5. 320 SPGA Pin Assignments - Sorted Alphabetically by Signal Name (Continued)
Signal Name |
Type |
Pin. No. |
|
Signal Name |
Type |
Pin. No. |
|
Signal Name |
Type |
Pin. No. |
|
Signal Name |
Type |
Pin. No. |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
VCC2 |
PWR |
E27 |
|
VCC3 |
PWR |
A35 |
|
VSS |
GND |
A31 |
|
VSS |
GND |
AE35 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
VCC2 |
PWR |
E29 |
|
VCC3 |
PWR |
C1 |
|
VSS |
GND |
A37 |
|
VSS |
GND |
AG1 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
VCC2 |
PWR |
J33 |
|
VCC3 |
PWR |
C19 |
|
VSS |
GND |
B2 |
|
VSS |
GND |
AG5 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
VCC2 |
PWR |
L1 |
|
VCC3 |
PWR |
C37 |
|
VSS |
GND |
C15 |
|
VSS |
GND |
AG33 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
VCC2 |
PWR |
L3 |
|
VCC3 |
PWR |
N1 |
|
VSS |
GND |
C23 |
|
VSS |
GND |
AG37 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
VCC2 |
PWR |
L5 |
|
VCC3 |
PWR |
N37 |
|
VSS |
GND |
E7 |
|
VSS |
GND |
AJ7 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
VCC2 |
PWR |
L33 |
|
VCC3 |
PWR |
U3 |
|
VSS |
GND |
E13 |
|
VSS |
GND |
AJ13 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
VCC2 |
PWR |
L35 |
|
VCC3 |
PWR |
U35 |
|
VSS |
GND |
E19 |
|
VSS |
GND |
AJ19 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
VCC2 |
PWR |
L37 |
|
VCC3 |
PWR |
AA1 |
|
VSS |
GND |
E25 |
|
VSS |
GND |
AJ25 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
VCC2 |
PWR |
AC1 |
|
VCC3 |
PWR |
AA37 |
|
VSS |
GND |
E31 |
|
VSS |
GND |
AJ31 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
VCC2 |
PWR |
AC3 |
|
VCC3 |
PWR |
AL19 |
|
VSS |
GND |
G1 |
|
VSS |
GND |
AK4 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
VCC2 |
PWR |
AC5 |
|
VCC3 |
PWR |
AL37 |
|
VSS |
GND |
G5 |
|
VSS |
GND |
AK34 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
VCC2 |
PWR |
AC33 |
|
VCC3 |
PWR |
AN13 |
|
VSS |
GND |
G33 |
|
VSS |
GND |
AL15 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
VCC2 |
PWR |
AC35 |
|
VCC3 |
PWR |
AN25 |
|
VSS |
GND |
G37 |
|
VSS |
GND |
AL23 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
VCC2 |
PWR |
AC37 |
|
VCC3 |
PWR |
AN35 |
|
VSS |
GND |
J3 |
|
VSS |
GND |
AN1 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
VCC2 |
PWR |
AE5 |
|
VID_CLK |
O |
V4 |
|
VSS |
GND |
J35 |
|
VSS |
GND |
AN7 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
VCC2 |
PWR |
AE33 |
|
VID_DATA0 |
O |
AK6 |
|
VSS |
GND |
N5 |
|
VSS |
GND |
AN19 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
VCC2 |
PWR |
AJ9 |
|
VID_DATA1 |
O |
AN5 |
|
VSS |
GND |
N33 |
|
VSS |
GND |
AN31 |
VCC2 |
PWR |
AJ27 |
|
VID_DATA2 |
O |
AL5 |
|
VSS |
GND |
Q3 |
|
VSS |
GND |
AN37 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
VCC2 |
PWR |
AJ29 |
|
VID_DATA3 |
O |
AM4 |
|
VSS |
GND |
Q35 |
|
WEA# |
O |
W33 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
VCC2 |
PWR |
AL1 |
|
VID_DATA4 |
O |
AL3 |
|
VSS |
GND |
U1 |
|
WEB# |
O |
W35 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
VCC2 |
PWR |
AL9 |
|
VID_DATA5 |
O |
AJ5 |
|
VSS |
GND |
U5 |
|
Note: PU/PD indicates pin is |
||
|
|
|
|
|
|
|
|
|
|
|
|
|||
VCC2 |
PWR |
AL29 |
|
VID_DATA6 |
O |
AH4 |
|
VSS |
GND |
U33 |
||||
|
|
|
internally connected to |
|||||||||||
VCC2 |
PWR |
AN3 |
|
VID_DATA7 |
O |
AM2 |
|
VSS |
GND |
U37 |
|
|||
|
|
|
a 20-kohm pull-up/ |
|||||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|||
VCC2 |
PWR |
AN9 |
|
VID_RDY |
I |
AK2 |
|
VSS |
GND |
Y3 |
||||
|
|
|
down resistor |
|
||||||||||
VCC2 |
PWR |
AN29 |
|
VID_VAL |
O |
S3 |
|
VSS |
GND |
Y35 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
VCC3 |
PWR |
A3 |
|
VOLDET |
O |
AM36 |
|
VSS |
GND |
AA5 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
VCC3 |
PWR |
A13 |
|
VSS |
GND |
A7 |
|
VSS |
GND |
AA33 |
|
|
|
|
VCC3 |
PWR |
A25 |
|
VSS |
GND |
A19 |
|
VSS |
GND |
AE3 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Processor GXm Geode™
Revision 3.1 |
23 |
www.national.com |
Geode™ GXm Processor
Signal Definitions (Continued)
2.2SIGNAL DESCRIPTIONS
2.2.1System Interface Signals
|
BGA |
SPGA |
|
|
Signal Name |
Pin No. |
Pin No. |
Type |
Description |
|
|
|
|
|
SYSCLK |
P26 |
V34 |
I |
System Clock |
|
|
|
|
System Clock runs synchronously with the PCI bus. The internal |
|
|
|
|
clock of the GXm processor is generated by an internal PLL |
|
|
|
|
which multiplies the SYSCLK input and can run up to eight times |
|
|
|
|
faster. The SYSCLK to core clock multiplier is configured using |
|
|
|
|
the CLKMOD[2:0] inputs. |
|
|
|
|
The SYSCLK input is a fixed frequency which can only be |
|
|
|
|
stopped or varied when the GXm processor is in a full 3V Sus- |
|
|
|
|
pend. (Section 6.4 “3-Volt Suspend Mode” on page 174 for |
|
|
|
|
details regarding this mode.) |
|
|
|
|
|
CLKMODE[2:0] |
M1, L1, |
G3, R2, |
I |
Clock Mode |
|
M3 |
S1 |
|
These signals are used to set the core clock multiplier. The PCI |
|
|
|
|
|
|
|
|
|
clock "SYSCLK" is multiplied by the value programmed by CLK- |
|
|
|
|
MODE[2:0] to generate the GXm processor’s core clock. |
|
|
|
|
CLKMODE2 is valid only for GXm processor revision 4.0 and up. |
|
|
|
|
The value read from DIR1 (Device ID Register 1, refer to |
|
|
|
|
page 51) affects the definition of the CLKMODE pins. |
|
|
|
|
If DIR1 = 30h-33h then CLKMODE[1:0]: |
|
|
|
|
00 = SYSCLK multiplied by 4 (Test mode only) |
|
|
|
|
01 = SYSCLK multiplied by 6 |
|
|
|
|
10 = SYSCLK multiplied by 7 |
|
|
|
|
11 = SYSCLK multiplied by 5 |
|
|
|
|
If DIR1 = 34h-4Fh then CLKMODE[1:0]: |
|
|
|
|
00 = SYSCLK multiplied by 4 (Test mode only) |
|
|
|
|
01 = SYSCLK multiplied by 6 |
|
|
|
|
10 = SYSCLK multiplied by 7 |
|
|
|
|
11 = SYSCLK multiplied by 8 |
|
|
|
|
If DIR1 > or = 50h then CLKMODE[2:0]: |
|
|
|
|
000 = SYSCLK multiplied by 4 (Test mode only) |
|
|
|
|
001 = SYSCLK multiplied by 10 |
|
|
|
|
010 = SYSCLK multiplied by 9 |
|
|
|
|
011 = SYSCLK multiplied by 5 |
|
|
|
|
100 = SYSCLK multiplied by 4 |
|
|
|
|
101 = SYSCLK multiplied by 6 |
|
|
|
|
110 = SYSCLK multiplied by 7 |
|
|
|
|
111 = SYSCLK multiplied by 8 |
|
|
|
|
|
RESET |
J3 |
M2 |
I |
Reset |
|
|
|
|
RESET aborts all operations in progress and places the |
|
|
|
|
GXm processor into a reset state. RESET forces the CPU and |
|
|
|
|
peripheral functions to begin executing at a known state. All data |
|
|
|
|
in the on-chip cache is invalidated. |
|
|
|
|
RESET is an asynchronous input but must meet specified setup |
|
|
|
|
and hold times to guarantee recognition at a particular clock |
|
|
|
|
edge. This input is typically generated during the Power-On- |
|
|
|
|
Reset sequence. |
|
|
|
|
Note: Warm Reset does not require an input on the GXm pro- |
|
|
|
|
cessor since the function is virtualized using SMM. |
|
|
|
|
|
www.national.com |
24 |
Revision 3.1 |
Signal Definitions (Continued)
2.2.1 System Interface Signals (Continued)
|
BGA |
SPGA |
|
|
Signal Name |
Pin No. |
Pin No. |
Type |
Description |
|
|
|
|
|
INTR |
B18 |
D24 |
I |
(Maskable) Interrupt Request |
|
|
|
|
INTR is a level-sensitive input that causes the GXm processor to |
|
|
|
|
Suspend execution of the current instruction stream and begin |
|
|
|
|
execution of an interrupt service routine. The INTR input can be |
|
|
|
|
masked through the Flags Register IF bit. (See Table 3-4 on |
|
|
|
|
page 43 for bit definitions.) |
|
|
|
|
|
IRQ13 |
C22 |
C31 |
O |
Interrupt Request Level 13 |
|
|
|
|
IRQ13 is asserted if an on-chip floating point error occurs. |
|
|
|
|
When a floating point error occurs, the GXm processor asserts |
|
|
|
|
the IRQ13 pin. The floating point interrupt handler then performs |
|
|
|
|
an OUT instruction to I/O address F0h or F1h. The GXm proces- |
|
|
|
|
sor accepts either of these cycles and clears the IRQ13 pin. |
|
|
|
|
Refer to Section 3.4.1 “I/O Address Space” on page 60 for fur- |
|
|
|
|
ther information on IN/OUT instructions. |
|
|
|
|
|
SMI# |
C19 |
B28 |
I |
System Management Interrupt |
|
|
|
|
SMI# is a level-sensitive interrupt. SMI# puts the GXm processor |
|
|
|
|
into System Management Mode (SMM). |
|
|
|
|
|
SUSP# |
H2 |
M4 |
I |
Suspend Request |
|
(PU) |
(PU) |
|
This signal is used to request that the GXm processor enter Sus- |
|
|
|
|
|
|
|
|
|
pend mode. After recognition of an active SUSP# input, the pro- |
|
|
|
|
cessor completes execution of the current instruction, any |
|
|
|
|
pending decoded instructions and associated bus cycles. |
|
|
|
|
SUSP# is ignored following RESET# and is enabled by setting |
|
|
|
|
the SUSP bit in CCR2. (See Table 16 on page 44 for CCR2 bit |
|
|
|
|
definitions.) |
|
|
|
|
Since the GXm processor includes system logic functions as well |
|
|
|
|
as the CPU core, there are special modes designed to support |
|
|
|
|
the different power management states associated with APM, |
|
|
|
|
ACPI, and portable designs. The part can be configured to stop |
|
|
|
|
only the CPU core clocks, or all clocks. When all clocks are |
|
|
|
|
stopped, the external clock can also be stopped. (See Section |
|
|
|
|
6.0 “Power Management” on page 174 for more details regarding |
|
|
|
|
power management states.) |
|
|
|
|
This pin is internally connected to a 20-kohm pull-up resistor. |
|
|
|
|
SUSP# is pulled up when not active. |
|
|
|
|
|
SUSPA# |
E2 |
H4 |
O |
Suspend Acknowledge |
|
|
|
|
Suspend Acknowledge indicates that the GXm processor has |
|
|
|
|
entered low-power Suspend mode as a result of SUSP# asser- |
|
|
|
|
tion or execution of a HALT instruction. SUSPA# is enabled by |
|
|
|
|
setting the SUSP bit in CCR2. (See Table 16 on page 44 for |
|
|
|
|
CCR2 bit definitions.) |
|
|
|
|
The SYSCLK input may be stopped after SUSPA# has been |
|
|
|
|
asserted to further reduce power consumption if the system is |
|
|
|
|
configured for 3V Suspend mode. (Section 6.4 “3-Volt Suspend |
|
|
|
|
Mode” on page 174 for details regarding this mode.) |
|
|
|
|
|
SERIALP |
L3 |
Q1 |
O |
Serial Packet |
|
|
|
|
Serial Packet is the single wire serial-transmission signal to the |
|
|
|
|
CS5530 chip. The clock used for this interface is the PCI clock |
|
|
|
|
(SYSCLK). This interface carries packets of miscellaneous infor- |
|
|
|
|
mation to the chipset to be used by the VSA software handlers. |
|
|
|
|
|
Processor GXm Geode™
Revision 3.1 |
25 |
www.national.com |
Geode™ GXm Processor
Signal Definitions (Continued)
2.2.2PCI Interface Signals
|
BGA |
SPGA |
|
|
|
Signal Name |
Pin No. |
Pin No |
Type |
Description |
|
|
|
|
|
|
|
AD[31:0] |
Refer |
Refer |
I/O |
Multiplexed Address and Data |
|
|
to Table |
to Table |
|
Addresses and data are multiplexed on the same PCI pins. A bus |
|
|
2-3 |
2-5 |
|
||
|
|
transaction consists of an address phase in the cycle in which |
|||
|
|
|
|
||
|
|
|
|
FRAME# is asserted followed by one or more data phases. Dur- |
|
|
|
|
|
ing the address phase, AD[31:0] contain a physical 32-bit |
|
|
|
|
|
address. For I/O, this is a byte address, for configuration and |
|
|
|
|
|
memory it is a DWORD address. During data phases, AD[7:0] |
|
|
|
|
|
contain the least significant byte (LSB) and AD[31:24] contain |
|
|
|
|
|
the most significant byte (MSB). Write data is stable and valid |
|
|
|
|
|
when IRDY# is asserted and read data is stable and valid when |
|
|
|
|
|
TRDY# is asserted. Data is transferred during those SYSCLKS |
|
|
|
|
|
where both IRDY# and TRDY# are asserted. |
|
|
|
|
|
|
|
C/BE[3:0]# |
D5, |
B6, |
I/O |
Multiplexed Command and Byte Enables |
|
|
B8, |
B12, |
|
Bus command and byte enables are multiplexed on the same |
|
|
C13, |
B18, |
|
||
|
|
PCI pins. During the address phase of a transaction when |
|||
|
A15 |
E21 |
|
||
|
|
FRAME# is active, C/BE[3:0]# define the bus command. During |
|||
|
|
|
|
||
|
|
|
|
the data phase C/BE[3:0]# are used as byte enables. The byte |
|
|
|
|
|
enables are valid for the entire data phase and determine which |
|
|
|
|
|
byte lanes carry meaningful data. C/BE0# applies to byte 0 |
|
|
|
|
|
(LSB) and C/BE3# applies to byte 3 (MSB). |
|
|
|
|
|
The command encoding and types are listed below. |
|
|
|
|
|
0000 |
= Interrupt Acknowledge |
|
|
|
|
0001 |
= Special Cycle |
|
|
|
|
0010 |
= I/O Read |
|
|
|
|
0011 |
= I/O Write |
|
|
|
|
0100 |
= Reserved |
|
|
|
|
0101 |
= Reserved |
|
|
|
|
0110 |
= Memory Read |
|
|
|
|
0111 |
= Memory Write |
|
|
|
|
1000 |
= Reserved |
|
|
|
|
1001 |
= Reserved |
|
|
|
|
1010 |
= Configuration Read |
|
|
|
|
1011 |
= Configuration Write |
|
|
|
|
1100 |
= Memory Read Multiple |
|
|
|
|
1101 |
= Dual Address Cycle (Reserved) |
|
|
|
|
1110 |
= Memory Read Line |
|
|
|
|
1111 |
= Memory Write and Invalidate |
|
|
|
|
|
|
PAR |
B12 |
C17 |
I/O |
Parity |
|
|
|
|
|
Parity generation is required by all PCI agents: the master drives |
|
|
|
|
|
PAR for address and write-data phases, the target drives PAR for |
|
|
|
|
|
read-data phases. Parity is even across AD[31:0] and |
|
|
|
|
|
C/BE[3:0]#. |
|
|
|
|
|
For address phases, PAR is stable and valid one SYSCLK after |
|
|
|
|
|
the address phase. It has the same timing as AD[31:0] but |
|
|
|
|
|
delayed by one SYSCLK. |
|
|
|
|
|
For data phases, PAR is stable and valid one SYSCLK after |
|
|
|
|
|
either IRDY# is asserted on a write transaction or after TRDY# is |
|
|
|
|
|
asserted on a read transaction. Once PAR is valid, it remains |
|
|
|
|
|
valid until one SYSCLK after the completion of the data phase. |
|
|
|
|
|
(Also see PERR#.) |
|
|
|
|
|
|
|
www.national.com |
26 |
Revision 3.1 |
Signal Definitions (Continued)
2.2.2 PCI Interface Signals |
(Continued) |
|
||
|
BGA |
SPGA |
|
|
Signal Name |
Pin No. |
Pin No |
Type |
Description |
|
|
|
|
|
FRAME# |
A8 |
C13 |
s/t/s |
Frame |
|
(PU) |
(PU) |
|
Cycle Frame is driven by the current master to indicate the |
|
|
|
|
|
|
|
|
|
beginning and duration of an access. FRAME# is asserted to |
|
|
|
|
indicate a bus transaction is beginning. While FRAME# is |
|
|
|
|
asserted, data transfers continue. When FRAME# is deasserted, |
|
|
|
|
the transaction is in the final data phase. |
|
|
|
|
This pin is internally connected to a 20-kohm pull-up resistor. |
|
|
|
|
|
IRDY# |
C9 |
D14 |
s/t/s |
Initiator Ready |
|
(PU) |
(PU) |
|
Initiator Ready is asserted to indicate that the bus master is able |
|
|
|
|
|
|
|
|
|
to complete the current data phase of the transaction. IRDY# is |
|
|
|
|
used in conjunction with TRDY#. A data phase is completed on |
|
|
|
|
any SYSCLK in which both IRDY# and TRDY# are sampled |
|
|
|
|
asserted. During a write, IRDY# indicates valid data is present |
|
|
|
|
on AD[31:0]. During a read, it indicates the master is prepared to |
|
|
|
|
accept data. Wait cycles are inserted until both IRDY# and |
|
|
|
|
TRDY# are asserted together. |
|
|
|
|
This pin is internally connected to a 20-kohm pull-up resistor. |
|
|
|
|
|
TRDY# |
B9 |
B14 |
s/t/s |
Target Ready |
|
(PU) |
(PU) |
|
TRDY# is asserted to indicate that the target agent is able to |
|
|
|
|
|
|
|
|
|
complete the current data phase of the transaction. TRDY# is |
|
|
|
|
used in conjunction with IRDY#. A data phase is complete on any |
|
|
|
|
SYSCLK in which both TRDY# and IRDY# are sampled |
|
|
|
|
asserted. During a read, TRDY# indicates that valid data is |
|
|
|
|
present on AD[31:0]. During a write, it indicates the target is pre- |
|
|
|
|
pared to accept data. Wait cycles are inserted until both IRDY# |
|
|
|
|
and TRDY# are asserted together. |
|
|
|
|
This pin is internally connected to a 20-kohm pull-up resistor. |
|
|
|
|
|
STOP# |
C11 |
A15 |
s/t/s |
Target Stop |
|
(PU) |
(PU) |
|
STOP# is asserted to indicate that the current target is request- |
|
|
|
|
|
|
|
|
|
ing the master to stop the current transaction. This signal is used |
|
|
|
|
with DEVSEL# to indicate retry, disconnect or target abort. If |
|
|
|
|
STOP# is sampled active while a master, FRAME# will be deas- |
|
|
|
|
serted and the cycle stopped within three SYSCLK cycles. As an |
|
|
|
|
input, STOP# can be asserted in the following cases. 1) If a PCI |
|
|
|
|
master tries to access memory that has been locked by another |
|
|
|
|
master. This condition is detected if FRAME# and LOCK# are |
|
|
|
|
asserted during an address phase. 2) STOP# will also be |
|
|
|
|
asserted if the PCI write buffers are full or if a previously buffered |
|
|
|
|
cycle has not completed. 3) Finally, STOP# can be asserted on |
|
|
|
|
read cycles that cross cache line boundaries. This is conditional |
|
|
|
|
based upon the programming of bit 1 in PCI Control Function 2 |
|
|
|
|
Register. (See Table 4-37 on page 156 for programming details.) |
|
|
|
|
This pin is internally connected to a 20-kohm pull-up resistor. |
|
|
|
|
|
Processor GXm Geode™
Revision 3.1 |
27 |
www.national.com |
Geode™ GXm Processor
Signal Definitions (Continued)
2.2.2 PCI Interface Signals |
(Continued) |
|
||
|
BGA |
SPGA |
|
|
Signal Name |
Pin No. |
Pin No |
Type |
Description |
|
|
|
|
|
LOCK# |
B11 |
B16 |
s/t/s |
Lock Operation |
|
(PU) |
(PU) |
|
LOCK# indicates an atomic operation that may require multiple |
|
|
|
|
|
|
|
|
|
transactions to complete. When LOCK# is asserted, nonexclu- |
|
|
|
|
sive transactions may proceed to an address that is not currently |
|
|
|
|
locked (at least 16 bytes must be locked). A grant to start a trans- |
|
|
|
|
action on PCI does not guarantee control of LOCK#. Control of |
|
|
|
|
LOCK# is obtained under it own protocol in conjunction with |
|
|
|
|
GNT#. It is possible for different agents to use PCI while a single |
|
|
|
|
master retains ownership of LOCK#. The arbiter can implement |
|
|
|
|
a complete system lock. In this mode, if LOCK# is active, no |
|
|
|
|
other master can gain access to the system until the LOCK# is |
|
|
|
|
deasserted. |
|
|
|
|
This pin is internally connected to a 20-kohm pull-up resistor. |
|
|
|
|
|
DEVSEL# |
A9 |
E15 |
s/t/s |
Device Select |
|
(PU) |
(PU) |
|
DEVSEL# indicates that the driving device has decoded its |
|
|
|
|
|
|
|
|
|
address as the target of the current access. As an input, |
|
|
|
|
DEVSEL# indicates whether any device on the bus has been |
|
|
|
|
selected. DEVSEL# will also be driven by any agent that has the |
|
|
|
|
ability to accept cycles on a subtractive decode basis. As a mas- |
|
|
|
|
ter, if no DEVSEL# is detected within and up to the subtractive |
|
|
|
|
decode clock, a master abort cycle will result expect for special |
|
|
|
|
cycles which do not expect a DEVSEL# returned. |
|
|
|
|
This pin is internally connected to a 20-kohm pull-up resistor. |
|
|
|
|
|
PERR# |
A11 |
D16 |
s/t/s |
Parity Error |
|
(PU) |
(PU) |
|
PERR# is used for reporting of data parity errors during all PCI |
|
|
|
|
|
|
|
|
|
transactions except a Special Cycle. The PERR# line is driven |
|
|
|
|
two SYSCLKs after the data in which the error was detected. |
|
|
|
|
This is one SYSCLK after the PAR that is attached to the data. |
|
|
|
|
The minimum duration of PERR# is one SYSCLK for each data |
|
|
|
|
phase in which a data parity error is detected. PERR# must be |
|
|
|
|
driven high for one SYSCLK before being in TRI-STATE mode. A |
|
|
|
|
target asserts PERR# on write cycles if it has claimed the cycle |
|
|
|
|
with DEVSEL#. The master asserts PERR# on read cycles. |
|
|
|
|
This pin is internally connected to a 20-kohm pull-up resistor. |
|
|
|
|
|
SERR# |
C12 |
A17 |
OD |
System Error |
|
(PU) |
(PU) |
|
System Error may be asserted by any agent for reporting errors |
|
|
|
|
|
|
|
|
|
other than PCI parity. The intent is to have the PCI central agent |
|
|
|
|
assert NMI to the processor. When the Parity Enable bit is set in |
|
|
|
|
the Memory Controller Configuration register, SERR# will be |
|
|
|
|
asserted upon detecting a parity error on read operations from |
|
|
|
|
DRAM. |
|
|
|
|
|
REQ[2:0]# |
D3, |
E3, |
I |
Request Lines |
|
H3, |
K2, |
|
Request indicates to the arbiter that an agent desires use of the |
|
E3 |
E1 |
|
|
|
|
bus. Each master has its own REQ# line. REQ# priorities are |
||
|
(PU) |
(PU) |
|
|
|
|
based on the arbitration scheme chosen. |
||
|
|
|
|
|
|
|
|
|
Each of these pins are internally connected to a 20-kohm pull-up |
|
|
|
|
resistor. |
|
|
|
|
|
www.national.com |
28 |
Revision 3.1 |
Signal Definitions (Continued)
2.2.2PCI Interface Signals (Continued)
|
BGA |
SPGA |
|
|
Signal Name |
Pin No. |
Pin No |
Type |
Description |
|
|
|
|
|
GNT[2:0]# |
E1, |
H2, |
O |
Grant Lines |
|
F2, |
K4, |
|
Grant indicates to the requesting master that it has been granted |
|
D1 |
F2 |
|
|
|
|
access to the bus. Each master has its own GNT# line. GNT# |
||
|
|
|
|
|
|
|
|
|
can be pulled away at any time a higher REQ# is received or if |
|
|
|
|
the master does not begin a cycle within a minimum period of |
|
|
|
|
time (16 SYSCLKs). |
|
|
|
|
|
2.2.3Memory Controller Interface Signals
|
BGA |
SPGA |
|
|
Signal Name |
Pin No. |
Pin No. |
Type |
Description |
|
|
|
|
|
Note: The memory controller interface supports two types of memory configurations: SDRAM modules on the system board and JEDEC DIMM connectors. Refer to Section 4.3 “Memory Controller” on page 103 for detailed information regarding signal connections.
MD[63:0] |
Refer |
Refer |
I/O |
Memory Data Bus |
|
to Table |
to Table |
|
The data bus lines driven to/from system memory. |
|
2-3 |
2-5 |
|
|
|
|
|
||
|
|
|
|
|
MA[12:0] |
Refer |
Refer |
O |
Memory Address Bus |
|
to Table |
to Table |
|
The multiplexed row/column address lines driven to the system |
|
2-3 |
2-5 |
|
|
|
|
memory. |
||
|
|
|
|
|
|
|
|
|
Supports 256 Mbit SDRAM. |
|
|
|
|
|
BA[1:0] |
AD26, |
AJ33, |
O |
Bank Address Bits |
|
AD25 |
AK36 |
|
These bits are used to select the component bank within the |
|
|
|
|
|
|
|
|
|
SDRAM. |
|
|
|
|
|
CS[3:0]# |
AE23, |
AK32, |
O |
Chip Selects |
|
V25, |
Z34, |
|
The chip selects are used to select the module bank within the |
|
AD23, |
AN33, |
|
|
|
|
system memory. Each chip select corresponds to a specific mod- |
||
|
V26 |
AA35 |
|
|
|
|
ule bank. |
||
|
|
|
|
|
|
|
|
|
If CS# is high, the bank(s) do not respond to RAS#, CAS#, WE# |
|
|
|
|
until the bank is selected again. |
|
|
|
|
|
RASA#, |
W24, |
AB36, |
O |
Row Address Strobe |
RASB# |
W25 |
AB34 |
|
RAS#, CAS#, WE# and CKE are encoded to support the differ- |
|
|
|
|
|
|
|
|
|
ent SDRAM commands. RASA# is used with CS[1:0]#. RASB# |
|
|
|
|
is used with CS[3:2]#. |
|
|
|
|
|
CASA#, |
P25, |
W37, |
O |
Column Address Strobe |
CASB# |
R26 |
X36 |
|
RAS#, CAS#, WE# and CKE are encoded to support the differ- |
|
|
|
|
|
|
|
|
|
ent SDRAM commands. CASA# is used with CS[1:0]#. CASB# |
|
|
|
|
is used with CS[3:2]#. |
|
|
|
|
|
WEA#, |
R25, |
W33, |
O |
Write Enable |
WEB# |
R24 |
W35 |
|
RAS#, CAS#, WE# and CKE are encoded to support the differ- |
|
|
|
|
|
|
|
|
|
ent SDRAM commands. WEA# is used with CS[1:0]#. WEB# is |
|
|
|
|
used with CS[3:2]#. |
|
|
|
|
|
Processor GXm Geode™
Revision 3.1 |
29 |
www.national.com |
Geode™ GXm Processor
Signal Definitions (Continued)
2.2.3Memory Controller Interface Signals (Continued)
|
BGA |
SPGA |
|
|
Signal Name |
Pin No. |
Pin No. |
Type |
Description |
|
|
|
|
|
DQM[7:0] |
Refer |
Refer |
O |
Data Mask Control Bits |
|
to Table |
to Table |
|
During memory read cycles, these outputs control whether the |
|
2-3 |
2-5 |
|
|
|
|
SDRAM output buffers are driven on the MD bus or not. All DQM |
||
|
|
|
|
|
|
|
|
|
signals are asserted during read cycles. |
|
|
|
|
During memory write cycles, these outputs control whether or |
|
|
|
|
not MD data will be written into the SDRAM. |
|
|
|
|
DQM[7:0] connect directly to the DQM7-0 pins of each connec- |
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tor. |
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CKEA, |
AF24, |
AL33, |
O |
Clock Enable |
CKEB |
AD16 |
AN23 |
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For normal operation CKE is held high. CKE goes low during |
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Suspend. |
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SDCLK[3:0] |
AE4, |
AM8, |
O |
SDRAM Clocks |
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AF5, |
AK10, |
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The SDRAM samples all the control, address, and data using |
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AE5, |
AL7, |
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these clocks. |
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AF4 |
AK8 |
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SDCLK_IN |
AE8 |
AK12 |
I |
SDRAM Clock Input |
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The GXm processor samples the memory read data on this |
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clock. Works in conjunction with the SDCLK_OUT signal. |
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SDCLK_OUT |
AF8 |
AL13 |
O |
SDRAM Clock Output |
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This output is routed back to SDCLK_IN. The board designer |
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should vary the length of the board trace to control skew |
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between SDCLK_IN and SDCLK. |
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2.2.4Video Interface Signals
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BGA |
SPGA |
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Signal Name |
Pin No |
Pin No |
Type |
Description |
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PCLK |
AC1 |
AJ1 |
O |
Pixel Port Clock |
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Pixel Port Clock represents the pixel dotclock or a 2x multiple of |
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the dotclock for some 16-bit-per-pixel modes. It determines the |
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data transfer rate from the GXm processor to the CS5530. |
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VID_CLK |
P1 |
V4 |
O |
Video Clock |
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Video Clock represents the video port clock to the CS5530. This |
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pin is only used if the Video Port is enabled. |
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DCLK |
AB1 |
AD4 |
I |
DOT Clock |
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The DCLK input is driven from the CS5530 and represents the |
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pixel dot clock. In some cases, such as when displaying 16 BPP |
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data with an eight-bit-graphics pixel port, this clock will actually |
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be a 2x multiple of the dotclock. |
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CRT_HSYNC |
W2 |
AD2 |
O |
CRT Horizontal Sync |
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CRT Horizontal Sync establishes the line rate and horizontal |
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retrace interval for an attached CRT. The polarity is programma- |
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ble and depends on the display mode. |
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www.national.com |
30 |
Revision 3.1 |