NSC DS92LV090ATVEHX, DS92LV090ATVEH Datasheet
DS92LV090A
9 Channel Bus LVDS Transceiver
General Description
The DS92LV090Ais one in a series of Bus LVDS transceivers designed specifically for the high speed, low power proprietary backplane or cable interfaces. The device operates
from a single 3.3V power supply and includes nine differential line drivers and nine receivers. To minimize bus loading,
the driver outputs and receiver inputs are internally connected. The separate I/O of the logic side allows for loop
back support. Thedevice also features a flow through pinout
which allows easy PCB routing for short stubs between its
pins and the connector.
The driver translates 3V TTL levels (single-ended) to differential Bus LVDS (BLVDS) output levels. This allows for high
speed operation, while consuming minimal power with reduced EMI. In addition, the differential signaling provides
common mode noise rejection of
±
1V.
The receiver threshold is less than
±
100 mV over a±1V
common mode range and translates the differential Bus
LVDS to standard (TTL/CMOS) levels. (See Applications Information Section for more details.)
Features
n Bus LVDS Signaling
n 3.2 nanosecond propagation delay max
n Chip to Chip skew
±
800ps
n Low power CMOS design
n High Signaling Rate Capability (above 100 Mbps)
n 0.1V to 2.3V Common Mode Range for V
ID
= 200mV
n
±
100 mV Receiver Sensitivity
n Supports open and terminated failsafe on port pins
n 3.3V operation
n Glitch free power up/down (Driver & Receiver disabled)
n Light Bus Loading (5 pF typical) per Bus LVDS load
n Designed for Double Termination Applications
n Balanced Output Impedance
n Product offered in 64 pin TQFP package
n High impedance Bus pins on power off (V
CC
= 0V)
n Driver Channel to Channel skew (same device) 230ps
typical
n Receiver Channel to Channel skew (same device)
370ps typical
Simplified Functional Diagram
TRI-STATE®is a registered trademark of National Semiconductor Corporation.
DS100111-1
April 2000
DS92LV090A9 Channel Bus LVDS Transceiver
© 2000 National Semiconductor Corporation DS100111 www.national.com
Connection Diagram
Pinout Description
Pin Name Pin # Input/Output Descriptions
DO+/RI+ 27, 31, 35, 37, 41,
45, 47, 51, 55
I/O True Bus LVDS Driver Outputs and Receiver Inputs.
DO−/RI− 26, 30, 34, 36, 40,
44, 46, 50, 54
I/O Complimentary Bus LVDS Driver Outputs and Receiver Inputs.
D
IN
2, 6, 12, 18, 20, 22,
58, 60, 62
I TTL Driver Input.
RO 3, 7, 13, 19, 21, 23,
59, 61, 63
O TTL Receiver Output.
RE
17 I Receiver Enable TTL Input (Active Low).
DE 16 I Driver Enable TTL Input (Active High).
GND 4, 5, 9, 14, 25, 56 Power Ground for digital circuitry (must connect to GND on PC board).
These pins connected internally.
V
CC
10, 15, 24, 57, 64 Power VCCfor digital circuitry (must connect to VCCon PC board). These
pins connected internally.
AGND 28, 33, 43, 49, 53 Power Ground for analog circuitry (must connect to GND on PC board).
These pins connected internally.
AV
CC
29, 32, 42, 48, 52 Power Analog VCC(must connect to VCCon PC board). These pins
connected internally.
NC 1, 8, 11, 38, 39 N/A Leave open circuit, do not connect.
DS100111-2
Top View
Order Number DS92LV090ATVEH
See NS Package Number VEH064DB
DS92LV090A
www.national.com 2
Absolute Maximum Ratings (Notes 1, 2)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage (V
CC
) 4.0V
Enable Input Voltage
(DE, RE)
−0.3V to (VCC+0.3V)
Driver Input Voltage (D
IN
) −0.3V to (VCC+0.3V)
Receiver Output Voltage
(R
OUT
) −0.3V to (VCC+0.3V)
Bus Pin Voltage (DO/RI
±
) −0.3V to +3.9V
ESD (HBM 1.5 kΩ, 100 pF)
>
4.5 kV
Driver Short Circuit Duration momentary
Receiver Short Circuit
Duration momentary
Maximum Package Power Dissipation at 25˚C
TQFP 1.74 W
Derate TQFP Package 13.9 mW/˚C
θ
ja
71.7˚C/W
θ
jc
10.9˚C/W
Storage Temperature
Range −65˚C to +150˚C
Lead Temperature
(Soldering, 4 sec.) 260˚C
Recommended Operating
Conditions
Min Max Units
Supply Voltage (V
CC
) 3.0 3.6 V
Receiver Input Voltage 0.0 2.4 V
Operating Free Air Temperature −40 +85 ˚C
Maximum Input Edge Rate
(Note 6)(20% to 80%) ∆t/∆V
Data 1.0 ns/V
Control 3.0 ns/V
DC Electrical Characteristics
Over recommended operating supply voltage and temperature ranges unless otherwise specified (Notes 2, 3)
Symbol Parameter Conditions Pin Min Typ Max Units
V
OD
Output Differential
Voltage
RL=27Ω,
Figure 1
DO+/RI+,
DO−/RI−
240 300 460 mV
∆V
OD
VODMagnitude Change 27 mV
V
OS
Offset Voltage 1.1 1.3 1.5 V
∆V
OS
Offset Magnitude
Change
510mV
V
OH
Driver Output High
Voltage
RL=27Ω
1.4 1.65 V
V
OL
Driver Output Low
Voltage
RL=27Ω
0.95 1.1 V
I
OSD
Output Short Circuit
Current (Note 10)
VOD= 0V, DE = VCC, Driver
outputs shorted together
|36| |65| mA
V
OH
Voltage Output High
(Note 11)
VID= +300 mV IOH= −400 µA R
OUT
VCC−0.2 V
Inputs Open V
CC
−0.2 V
Inputs
Terminated,
R
L
=27Ω
V
CC
−0.2 V
V
OL
Voltage Output Low IOL= 2.0 mA, VID= −300 mV 0.05 0.075 V
I
OD
Receiver Output
Dynamic Current (Note
10)
V
ID
= 300mV, V
OUT=VCC
−1.0V −110 |75|
mA
V
ID
= −300mV, V
OUT
= 1.0V |75|
110 mA
V
TH
Input Threshold High DE = 0V, VCM= 1.5V DO+/RI+,
DO−/RI−
+100 mV
V
TL
Input Threshold Low −100 mV
V
CMR
Receiver Common
Mode Range
|VID|/2 2.4 −
|V
ID
|/2
V
I
IN
Input Current DE = 0V, RE = 2.4V,
VIN= +2.4V or 0V
−20
±
1 +20 µA
V
CC
= 0V, VIN= +2.4V or 0V −20
±
1 +20 µA
DS92LV090A
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