NSC DS91M040TSQX, DS91M040 Datasheet

May 13, 2008

DS91M040
125 MHz Quad M-LVDS Transceiver

General Description

The DS91M040 is a quad M-LVDS transceiver designed for
driving / receiving clock or data signals to / from up to four
multipoint networks.

M-LVDS (Multipoint LVDS) is a new family of bus interface
devices based on LVDS technology specifically designed for
multipoint and multidrop cable and backplane applications. It
differs from standard LVDS in providing increased drive cur­rent to handle double terminations that are required in multi­point applications. Controlled transition times minimize re­flections that are common in multipoint configurations due to
unterminated stubs. M-LVDS devices also have a very large
input common mode voltage range for additional noise margin
in heavily loaded and noisy backplane environments.

A single DS91M040 channel is a half-duplex transceiver that
accepts LVTTL/LVCMOS signals at the driver inputs and con­verts them to differential M-LVDS signal levels. The receiver
inputs accept low voltage differential signals (LVDS, BLVDS,
M-LVDS, LVPECL and CML) and convert them to 3V LVC­MOS signals. The DS91M040 supports both M-LVDS type 1
and type 2 receiver inputs.

Features

■

DC - 125 MHz / 250 Mbps low jitter, low skew, low power
operation

■

Wide Input Common Mode Voltage Range allows up to
±2V of GND noise

■

Conforms to TIA/EIA-899 M-LVDS Standard

■

Pin selectable M-LVDS receiver type (1 or 2)

■

Controlled transition times (2.0 ns typ) minimize reflections

■

8 kV ESD on M-LVDS I/O pins protects adjoining
components

■

Flow-through pinout simplifies PCB layout

■

Small 5 mm x 5 mm LLP-32 space saving package

Applications

■

Multidrop / Multipoint clock and data distribution

■

High-Speed, Low Power, Short-Reach alternative to TIA/
EIA-485/422

■

Clock distribution in AdvancedTCA (ATCA) and
MicroTCA (μTCA) backplanes

Typical Application

30042202

© 2008 National Semiconductor Corporation 300422 www.national.com

DS91M040 125 MHz Quad M-LVDS Transceiver

Ordering Information

Order Number Receiver Input Function Package Type

DS91M040TSQ Type 1 or 2 Quad M-LVDS Transciever LLP-32

Connection Diagram

30042201

Logic Diagram

30042203

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DS91M040

Pin Descriptions

Number Name I/O, Type Description

1, 3, 5, 7 RO O, LVCMOS Receiver output pin.

26, 28, 13, 15 RE I, LVCMOS Receiver enable pin: When RE is high, the receiver is disabled.

When RE is low, the receiver is enabled. There is a 300 kΩ pullup
resistor on this pin.

25, 27, 14, 16 DE I, LVCMOS Driver enable pin: When DE is low, the driver is disabled. When

DE is high, the driver is enabled. There is a 300 kΩ pulldown
resistor on this pin.

2, 4, 6, 8 DI I, LVCMOS Driver input pin.

31, DAP GND Power Ground pin and pad.

17, 19, 21, 23 A I/O, M-LVDS Non-inverting driver output pin/Non-inverting receiver input pin

18, 20, 22, 24 B I/O, M-LVDS Inverting driver output pin/Inverting receiver input pin

11, 12, 29, 30 V

DD

Power Power supply pin, +3.3V ± 0.3V

32 FSEN1 I, LVCMOS

Failsafe enable pin with a 300 kΩ pullup resistor. This pin
enables Type 2 receiver on inputs 0 and 2.
FSEN1 = L --> Type 1 receiver inputs
FSEN1 = H --> Type 2 receiver inputs

9 FSEN2 I, LVCMOS

Failsafe enable pin with a 300 kΩ pullup resistor. This pin
enables Type 2 receiver on inputs 1 and 3.
FSEN2 = L --> Type 1 receiver inputs
FSEN2 = H --> Type 2 receiver inputs

10 MDE I, LVCMOS Master enable pin. When MDE is H, the device is powered up.

When MDE is L, the device overrides all other control and powers
down.

M-LVDS Receiver Types

The EIA/TIA-899 M-LVDS standard specifies two different
types of receiver input stages. A type 1 receiver has a con­ventional threshold that is centered at the midpoint of the input
amplitude, VID/2. A type 2 receiver has a built in offset that is
100mV greater then VID/2. The type 2 receiver offset acts as
a failsafe circuit where open or short circuits at the input will
always result in the output stage being driven to a low logic
state.

30042240

FIGURE 1. M-LVDS Receiver Input Thresholds

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DS91M040

Absolute Maximum Ratings (Note 4)

If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.

Power Supply Voltage −0.3V to +4V
LVCMOS Input Voltage −0.3V to (VDD + 0.3V)

LVCMOS Output Voltage −0.3V to (VDD + 0.3V)

M-LVDS I/O Voltage −5.5V to +5.5V
M-LVDS Output Short Circuit

Current Duration Continuous
Junction Temperature +140°C
Storage Temperature Range −65°C to +150°C
Lead Temperature Range
Soldering (4 sec.) +260°C
Maximum Package Power Dissipation @ +25°C
SQ Package 833 mW
Derate SQ Package 6.67 mW/°C above +25°C
Package Thermal Resistance

 θ

JA

+150°C/W

 θ

JC

+63.8°C/W

ESD Susceptibility
HBM (Note 1)

≥8 kV

MM (Note 2)

≥250V

CDM (Note 3)

≥1250V

Note 1: Human Body Model, applicable std. JESD22-A114C

Note 2: Machine Model, applicable std. JESD22-A115-A

Note 3: Field Induced Charge Device Model, applicable std.

JESD22-C101-C

Recommended Operating
Conditions

Min Typ Max Units

Supply Voltage, V

DD

3.0 3.3 3.6 V

Voltage at Any Bus Terminal −1.4 +3.8 V

(Separate or Common-Mode)
Differential Input Voltage V

ID

2.4 V

LVTTL Input Voltage High V

IH

2.0 V

DD

V

LVTTL Input Voltage Low V

IL

0 0.8 V

Operating Free Air
Temperature T

A

−40 +25 +85 °C

DC Electrical Characteristics (Notes 5, 6, 7, 9)

Over recommended operating supply and temperature ranges unless otherwise specified.

Symbol Parameter Conditions Min Typ Max Units

M-LVDS Driver

|VAB| Differential output voltage magnitude

RL = 50Ω, CL = 5 pF

480 650 mV

ΔV

AB

Change in differential output voltage magnitude
between logic states

Figures 2, 4

−50 0 +50 mV

V

OS(SS)

Steady-state common-mode output voltage

RL = 50Ω, CL = 5 pF

0.3 1.6 2.1 V

|ΔV

OS(SS)

|

Change in steady-state common-mode output
voltage between logic states

Figures 2, 3

0 +50 mV

V

A(OC)

Maximum steady-state open-circuit output voltage Figure 5 0 2.4 V

V

B(OC)

Maximum steady-state open-circuit output voltage

0 2.4 V

V

P(H)

Voltage overshoot, low-to-high level output
(Note 12)

RL = 50Ω, CL = 5pF, CD = 0.5 pF
Figures 7, 8

1.2V

SS

V

V

P(L)

Voltage overshoot, high-to-low level output
(Note 12)

−0.2V

S

S

V

I

IH

High-level input current (LVTTL inputs) VIH = 2.0V -15 15

μA

I

IL

Low-level input current (LVTTL inputs) VIL = 0.8V -15 15

μA

V

CL

Input Clamp Voltage (LVTTL inputs) IIN = -18 mA -1.5 V

I

OS

Differential short-circuit output current (Note 8) Figure 6 -43 43 mA

M-LVDS Receiver

V

IT+

Positive-going differential input voltage threshold See Function Tables Type 1 16 50 mV

Type 2 100 150 mV

V

IT−

Negative-going differential input voltage threshold See Function Tables Type 1 −50 20 mV

Type 2 50 94 mV

V

OH

High-level output voltage (LVTTL output) IOH = −8mA 2.4 2.7

V

V

OL

Low-level output voltage (LVTTL output) IOL = 8mA 0.28

0.4 V

I

OZ

TRI-STATE output current VO = 0V or 3.6V −10 10

μA

I

OSR

Short-circuit receiver output current (LVTTL output) VO = 0V -50 -90 mA

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DS91M040

Symbol Parameter Conditions Min Typ Max Units

M-LVDS Bus (Input and Output) Pins

I

A

Transceiver input/output current VA = 3.8V, VB = 1.2V 32 µA

VA = 0V or 2.4V, VB = 1.2V −20 +20 µA

VA = −1.4V, VB = 1.2V −32 µA

I

B

Transceiver input/output current VB = 3.8V, VA = 1.2V 32 µA

VB = 0V or 2.4V, VA = 1.2V −20 +20 µA

VB = −1.4V, VA = 1.2V −32 µA

I

AB

Transceiver input/output differential current (IA − IB)

VA = VB, −1.4V ≤ V ≤ 3.8V

−4 +4 µA

I

A(OFF)

Transceiver input/output power-off current VA = 3.8V, VB = 1.2V,

DE = VCC = 1.5V

32 µA

VA = 0V or 2.4V, VB = 1.2V,
DE = VCC = 1.5V

−20 +20 µA

VA = −1.4V, VB = 1.2V,
DE = VCC = 1.5V

−32 µA

I

B(OFF)

Transceiver input/output power-off current VB = 3.8V, VA = 1.2V,

DE = VCC = 1.5V

32 µA

VB = 0V or 2.4V, VA = 1.2V,
DE = VCC = 1.5V

−20 +20 µA

VB = −1.4V, VA = 1.2V,
DE = VCC = 1.5V

−32 µA

I

AB(OFF)

Transceiver input/output power-off differential
current (I

A(OFF)

− I

B(OFF)

)

VA = VB, −1.4V ≤ V ≤ 3.8V,
VDD = 1.5V, DE = 1.5V

−4 +4 µA

C

A

Transceiver input/output capacitance VDD = OPEN 7.8 pF

C

B

Transceiver input/output capacitance 7.8 pF

C

AB

Transceiver input/output differential capacitance 3 pF

C

A/B

Transceiver input/output capacitance balance (CA/
CB)

1

SUPPLY CURRENT (VCC)

I

CCD

Driver Supply Current

RL = 50Ω, DE = H, RE = H

67 75 mA

I

CCZ

TRI-STATE Supply Current DE = L, RE = H 22 26 mA

I

CCR

Receiver Supply Current DE = L, RE = L 32 38 mA

I

CCPD

Power Down Supply Current MDE = L 3 5 mA

Note 4: “Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur, including inoperability and degradation of device reliability
and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or other conditions beyond those indicated in
the Recommended Operating Conditions is not implied. The Recommended Operating Conditions indicate conditions at which the device is functional and the
device should not be operated beyond such conditions.

Note 5: The Electrical Characteristics tables list guaranteed specifications under the listed Recommended Operating Conditions except as otherwise modified
or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and are not guaranteed.

Note 6: Current into device pins is defined as positive. Current out of device pins is defined as negative. All voltages are referenced to ground except VOD and
ΔVOD.

Note 7: Typical values represent most likely parametric norms for VDD = +3.3V and TA = +25°C, and at the Recommended Operation Conditions at the time of
product characterization and are not guaranteed.

Note 8: Output short circuit current (IOS) is specified as magnitude only, minus sign indicates direction only.

Note 9: CL includes fixture capacitance and CD includes probe capacitance.

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DS91M040