NSC DS90LV031ATMX, DS90LV031ATM Datasheet

DS90LV031A 3V LVDS Quad CMOS Differential Line Driver
General Description
The DS90LV031Ais a quad CMOS differential line driver de­signed for applications requiring ultra low power dissipation and high data rates. The device is designed to support data rates in excess of 400 Mbps (200 MHz) utilizing Low Voltage Differential Signaling (LVDS) technology.
The DS90LV031Aaccepts low voltage TTL/CMOS input lev­els and translates them to low voltage (350 mV) differential output signals. In addition the driver supports aTRI-STATE
®
function that may be used to disable the output stage, dis­abling the load current, and thus dropping the device to an ultra low idle power state of 13 mW typical.
Features
n
>
400 Mbps (200 MHz) switching rates
n 0.1 ns typical differential skew n 0.4 ns maximum differential skew n 2.0 ns maximum propagation delay n 3.3V power supply design
n
±
350 mV differential signaling
n Low power dissipation (13mW at 3.3V static) n Interoperable with existing 5V LVDS devices n Compatible with IEEE 1596.3 SCI LVDS standard n Compatible with TIA/EIA-644 LVDS standard n Industrial and Military operating temperature range n Available in SOIC, TSSOP and Cerpack surface mount
packaging
n Standard Microcircuit Drawing (SMD) 5962-9865201
Connection Diagram Functional Diagram
Truth Table
DRIVER
Enables Input Outputs
EN EN
*
D
IN
D
OUT+DOUT−
LHXZZ
All other combinations of ENABLE inputs
LLH
HHL
TRI-STATE®is a registered trademark of National Semiconductor Corporation.
Dual-In-Line
DS100095-1
Order Number DS90LV031ATM
or DS90LV031ATMTC
or DS90LV031AW
See NS Package Number M16A or MTC16 or W16A
DS100095-2
July 1999
DS90LV031A 3V LVDS Quad CMOS Differential Line Driver
© 1999 National Semiconductor Corporation DS100095 www.national.com
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications.
Supply Voltage (V
CC
) −0.3V to +4V
Input Voltage (D
IN
) −0.3V to (VCC+ 0.3V)
Enable Input Voltage (EN, EN
*
) −0.3V to (VCC+ 0.3V)
Output Voltage (D
OUT+,DOUT−
) −0.3V to +3.9V
Short Circuit Duration
(D
OUT+,DOUT−
) Continuous
Maximum Package Power Dissipation
@
+25˚C M Package 1088 mW MTC Package 866 mW W Package 845 mW
Derate M Package 8.5 mW/˚C above +25˚C Derate MTC Package 6.9 mW/˚C above +25˚C Derate W Package 6.8 mW/˚C above +25˚C
Storage Temperature Range −65˚C to +150˚C Lead Temperature Range
Soldering (4 sec.) +260˚C Maximum Junction Temperature +150˚C ESD Rating (Note 10)
(HBM, 1.5 k, 100 pF) 6kV
Recommended Operating Conditions
Min Typ Max Units
Supply Voltage (V
CC
) +3.0 +3.3 +3.6 V
Operating Free Air Temperature (T
A
)
Industrial −40 +25 +85 ˚C
Military -55 +25 +125 ˚C
Electrical Characteristics
Over supply voltage and operating temperature ranges, unless otherwise specified. (Notes 2, 3, 4)
Symbol Parameter Conditions Pin Min Typ Max Units
V
OD1
Differential Output Voltage R
L
=
100(
Figure 1
)D
OUT−
D
OUT+
250 350 450 mV
V
OD1
Change in Magnitude of V
OD1
for Complementary Output States
4 35 |mV|
V
OS
Offset Voltage 1.125 1.25 1.375 V
V
OS
Change in Magnitude of VOSfor Complementary Output States
5 25 |mV|
V
OH
Output Voltage High 1.38 1.6 V
V
OL
Output Voltage Low 0.90 1.03 V
V
IH
Input Voltage High DIN,
EN, EN*
2.0 V
CC
V
V
IL
Input Voltage Low GND 0.8 V
I
IH
Input Current V
IN
=
V
CC
or 2.5V −10
±
1 +10 µA
I
IL
Input Current V
IN
=
GND or 0.4V −10
±
1 +10 µA
V
CL
Input Clamp Voltage I
CL
=
−18 mA −1.5 −0.8 V
I
OS
Output Short Circuit Current ENABLED, (Note 11)
D
IN=VCC,DOUT+
=0Vor
D
IN
= GND, D
OUT−
=0V
D
OUT−
D
OUT+
−6.0 −9.0 mA
I
OSD
Differential Output Short Circuit Current
ENABLED, VOD=0V (Note 11)
−6.0 −9.0 mA
I
OFF
Power-off Leakage V
OUT
=
0V or 3.6V,
V
CC
=
0V or Open
−20
±
1 +20 µA
I
OZ
Output TRI-STATE Current EN = 0.8V and EN* = 2.0V
V
OUT
=
0V or V
CC
−10
±
1 +10 µA
I
CC
No Load Supply Current Drivers Enabled
DIN=VCCor GND V
CC
5.0 8.0 mA
I
CCL
Loaded Supply Current Drivers Enabled
RL= 100All Channels, DIN= V
CC
or GND (all inputs)
23 30 mA
I
CCZ
No Load Supply Current Drivers Disabled
DIN=VCCor GND, EN = GND, EN* = V
CC
2.6 6.0 mA
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Switching Characteristics - Industrial
V
CC
=
+3.3V
±
10%,T
A
=
−40˚C to +85˚C (Notes 3, 9, 12)
Symbol Parameter Conditions Min Typ Max Units
t
PHLD
Differential Propagation Delay High to Low RL= 100,CL=10pF
(
Figure 2
and
Figure 3
)
0.8 1.18 2.0 ns
t
PLHD
Differential Propagation Delay Low to High 0.8 1.25 2.0 ns
t
SKD1
Differential Pulse Skew |t
PHLD−tPLHD
|
(Note 5)
0 0.07 0.4 ns
t
SKD2
Channel-to-Channel Skew (Note 6) 0 0.1 0.5 ns
t
SKD3
Differential Part to Part Skew (Note 7) 0 1.0 ns
t
SKD4
Differential Part to Part Skew (Note 8) 0 1.2 ns
t
TLH
Rise Time 0.38 1.5 ns
t
THL
Fall Time 0.40 1.5 ns
t
PHZ
Disable Time High to Z RL= 100,CL=10pF
(
Figure 4
and
Figure 5
)
5ns
t
PLZ
Disable Time Low to Z 5ns
t
PZH
Enable Time Z to High 7ns
t
PZL
Enable Time Z to Low 7ns
f
MAX
Maximum Operating Frequency (Note 14) 200 250 MHz
Switching Characteristics - Military
V
CC
=
+3.3V
±
10%,T
A
=
−55˚C to +125˚C (Notes 9, 12)
Symbol Parameter Conditions Min Max Units
t
PHLD
Differential Propagation Delay High to Low RL= 100,CL=10pF
(
Figure 2
and
Figure 3
)
0.8 2.0 ns
t
PLHD
Differential Propagation Delay Low to High 0.8 2.0 ns
t
SKD1
Differential Pulse Skew |t
PHLD−tPLHD
|
(Note 5)
0 0.4 ns
t
SKD2
Channel-to-Channel Skew (Note 6) 0 0.5 ns
t
SKD3
Differential Part to Part Skew (Note 7) 0 1.0 ns
t
SKD4
Differential Part to Part Skew (Note 8) 0 1.2 ns
t
TLH
Rise Time 1.5 ns
t
THL
Fall Time 1.5 ns
t
PHZ
Disable Time High to Z RL= 100,CL=10pF
(
Figure 4
and
Figure 5
)
5ns
t
PLZ
Disable Time Low to Z 5ns
t
PZH
Enable Time Z to High 7ns
t
PZL
Enable Time Z to Low 7ns
f
MAX
Maximum Operating Frequency (Note 14) 200 MHz
Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the devices should be operated at these limits. The table of “Electrical Characteristics” specifies conditions of device operation.
Note 2: Current into device pins is defined as positive. Current out of device pins is defined as negative. All voltages are referenced to ground except: V
OD1
and
V
OD1
.
Note 3: All typicals are given for: V
CC
=
+3.3V, T
A
=
+25˚C.
Note 4: The DS90LV031Ais a current mode device and only functions within datasheet specifications when a resistive load is applied to the driver outputs typical range is (90to 110)
Note 5: t
SKD1
,|t
PHLD−tPLHD
| is the magnitude difference in differential propagation delay time between the positive going edge and the negative going edge of the
same channel. Note 6: t
SKD2
is the Differential Channel-to-Channel Skew of any event on the same device.
Note 7: t
SKD3
, Differential Part to Part Skew, is defined as the difference between the minimum and maximum specified differential propagation delays. This speci-
fication applies to devices at the same V
CC
and within 5˚C of each other within the operating temperature range.
Note 8: t
SKD4
, part to part skew, is the differential channel-to-channel skew of any event between devices. This specification applies to devices over recommended
operating temperature and voltage ranges, and across process distribution. t
SKD4
is defined as |Max − Min| differential propagation delay.
Note 9: Generator waveform for all tests unless otherwise specified: f=1 MHz, Z
O
=
50,t
r
1 ns, and tf≤ 1 ns.
Note 10: ESD Ratings:
HBM (1.5 k, 100 pF) 6kV
Note 11: Output short circuit current (I
OS
) is specified as magnitude only, minus sign indicates direction only.
Note 12: C
L
includes probe and jig capacitance.
Note 13: All input voltages are for one channel unless otherwise specified. Other inputs are set to GND. Note 14: f
MAX
generator input conditions: t
r
=
t
f
<
1ns, (0%to 100%), 50%duty cycle, 0V to 3V.Output Criteria: duty cycle=45%/55%, VOD>250mV,all channels
switching.
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Parameter Measurement Information
DS100095-3
FIGURE 1. Driver VODand VOSTest Circuit
DS100095-4
FIGURE 2. Driver Propagation Delay and Transition Time Test Circuit
DS100095-5
FIGURE 3. Driver Propagation Delay and Transition Time Waveforms
DS100095-6
FIGURE 4. Driver TRI-STATE Delay Test Circuit
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