NSC DS90LV028ATMX, DS90LV028ATM Datasheet
DS90LV028A
3V LVDS Dual CMOS Differential Line Receiver
General Description
The DS90LV028A is a dual CMOS differential line receiver
designed for applications requiring ultra low power dissipation, low noiseandhighdatarates. The device is designed to
support data rates in excess of 400 Mbps (200 MHz) utilizing
Low Voltage Differential Signaling (LVDS) technology.
The DS90LV028A accepts low voltage (350 mV typical) differential input signals and translates them to 3V CMOS output levels. The receiver also supports open, shorted and terminated (100Ω) input fail-safe. The receiver output will be
HIGH for all fail-safe conditions. The DS90LV028A has a
flow-through design for easy PCB layout.
The DS90LV028A and companion LVDS line driver provide a
new alternative to high power PECL/ECL devices for high
speed point-to-point interface applications.
Features
n
>
400 Mbps (200 MHz) switching rates
n 50 ps differential skew (typical)
n 0.1 ns channel-to-channel skew (typical)
n 2.5 ns maximum propagation delay
n 3.3V power supply design
n Flow-through pinout
n Power down high impedance on LVDS inputs
n Low Power design (18mW
@
3.3V static)
n Interoperable with existing 5V LVDS networks
n Accepts small swing (350 mV typical) differential signal
levels
n Supports open, short and terminated input fail-safe
n Conforms to ANSI/TIA/EIA-644 Standard
n Industrial temperature operating range
(−40˚C to +85˚C)
n Available in SOIC package
Connection Diagram Functional Diagram
Truth Table
INPUTS OUTPUT
[R
IN
+]−[RIN−] R
OUT
VID≥ 0.1V H
V
ID
≤ −0.1V L
Full Fail-safe
OPEN/SHORT
or Terminated
H
Dual-in-Line
DS100077-1
Order Number DS90LV028ATM
See NS Package Number M08A
DS100077-2
June 1998
DS90LV028A 3V LVDS Dual CMOS Differential Line Receiver
© 1998 National Semiconductor Corporation DS100077 www.national.com
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage (V
CC
) −0.3V to +4V
Input Voltage (R
IN
+, RIN−) −0.3V to +3.9V
Output Voltage (R
OUT
) −0.3V to VCC+ 0.3V
Maximum Package Power Dissipation +25˚C
M Package 1025 mW
Derate M Package 8.2 mW/˚C above +25˚C
Storage Temperature Range −65˚C to +150˚C
Lead Temperature Range Soldering
(4 sec.) +260˚C
Maximum Junction Temperature +150˚C
ESD Rating (Note 4)
(HBM 1.5 kΩ, 100 pF) ≥ 7kV
(EIAJ 0Ω, 200 pF) ≥ 500 V
Recommended Operating
Conditions
Min Typ Max Units
Supply Voltage (V
CC
) +3.0 +3.3 +3.6 V
Receiver Input Voltage GND 3.0 V
Operating Free Air
Temperature (T
A
) −40 25 +85 ˚C
Electrical Characteristics
Over Supply Voltage and Operating Temperature ranges, unless otherwise specified. (Notes 2, 3)
Symbol Parameter Conditions Pin Min Typ Max Units
V
TH
Differential Input High Threshold VCM= +1.2V, 0V, 3V (Note 12) RIN+, +100 mV
V
TL
Differential Input Low Threshold RIN− −100 mV
I
IN
Input Current VIN= +2.8V VCC= 3.6V or 0V −10
±
1 +10 µA
V
IN
= 0V −10
±
1 +10 µA
V
IN
= +3.6V VCC= 0V -20 +20 µA
V
OH
Output High Voltage IOH= −0.4 mA, VID= +200 mV R
OUT
2.7 3.1 V
I
OH
= −0.4 mA, Inputs terminated 2.7 3.1 V
I
OH
= −0.4 mA, Inputs shorted 2.7 3.1 V
V
OL
Output Low Voltage IOL= 2 mA, VID= −200 mV 0.3 0.5 V
I
OS
Output Short Circuit Current V
OUT
= 0V (Note 5) −15 −50 −100 mA
V
CL
Input Clamp Voltage ICL= −18 mA −1.5 −0.8 V
I
CC
No Load Supply Current Inputs Open V
CC
5.4 9 mA
Switching Characteristics
VCC= +3.3V±10%,TA= −40˚C to +85˚C (Notes 6, 7)
Symbol Parameter Conditions Min Typ Max Units
t
PHLD
Differential Propagation Delay High to Low CL= 15 pF 1.0 1.6 2.5 ns
t
PLHD
Differential Propagation Delay Low to High VID= 200 mV 1.0 1.7 2.5 ns
t
SKD1
Differential Pulse Skew |t
PHLD−tPLHD
| (Note 8) (
Figure 1
and
Figure 2
) 0 50 400 ps
t
SKD2
Differential Channel-to-Channel Skew-same device
(Note 9)
0 0.1 0.5 ns
t
SKD3
Differential Part to Part Skew (Note 10) 0 1.0 ns
t
SKD4
Differential Part to Part Skew (Note 11) 0 1.5 ns
t
TLH
Rise Time 325 800 ps
t
THL
Fall Time 225 800 ps
f
MAX
Maximum Operating Frequency (Note 13) 200 250 MHz
Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the devices
should be operated at these limits. The table of “Electrical Characteristics” specifies conditions of device operation.
Note 2: Current into device pins is defined as positive. Current out of device pins is defined as negative. All voltages are referenced to ground unless otherwise specified (such as V
ID
).
Note 3: All typicals are given for: V
CC
= +3.3V and TA= +25˚C.
Note 4: ESD Rating: HBM (1.5 kΩ, 100 pF) ≥ 7kV
EIAJ (0Ω, 200 pF) ≥ 500V
Note 5: Output short circuit current (I
OS
) is specified as magnitude only, minus sign indicates direction only. Only one output should be shorted at a time, do not ex-
ceed maximum junction temperature specification.
Note 6: C
L
includes probe and jig capacitance.
Note 7: Generator waveform for all tests unless otherwise specified:f=1MHz, Z
O
=50Ω,trand tf(0%to 100%) ≤ 3 ns for RIN.
Note 8: t
SKD1
is the magnitude difference in differential propagation delay time between the positive-going-edge and the negative-going-edge of the same channel.
www.national.com 2
Switching Characteristics (Continued)
Note 9: t
SKD2
is the differential channel-to-channel skew of any event on the same device. This specification applies to devices having multiple receivers within the
integrated circuit.
Note 10: t
SKD3
, part to part skew, is the differential channel-to-channel skew of any event between devices. This specification applies to devices at the same V
CC
and within 5˚C of each other within the operating temperature range.
Note 11: t
SKD4
, part to part skew, is the differential channel-to-channel skew of any event between devices. This specification applies to devices over the recom-
mended operating temperature and voltage ranges, and across process distribution. t
SKD4
is defined as |Max − Min| differential propagation delay.
Note 12: V
CC
is always higher than RIN+ and RIN− voltage. RIN+ and RIN− are allowed to have voltage range −0.05V to +3.05V. VIDis not allowed to be greater
than 100 mV when V
CM
=0Vor3V.
Note 13: f
MAX
generator input conditions: t
r
=
t
f
<
1ns(0%to 100%), 50%duty cycle, differential (1.05V to 1.35 peak to peak). Output criteria: 60%/40%duty cycle,
V
OL
(max 0.4V), VOH(min 2.7V), load=15 pF (stray plus probes).
Parameter Measurement Information
Typical Application
Applications Information
General application guidelines and hints for LVDS drivers
and receivers may be found in the following application
notes: LVDS Owner’s Manual (lit #550062-001), AN808,
AN1035, AN977, AN971, AN916, AN805, AN903.
LVDSdrivers and receivers are intended to be primarily used
in an uncomplicated point-to-point configuration as is shown
in
Figure 3
. This configuration provides a clean signaling environment for the fast edge rates of the drivers. The receiver
is connected to the driver through a balanced media which
may be a standard twisted pair cable, a parallel pair cable, or
simply PCB traces. Typically the characteristic impedance of
the media is in the range of 100Ω. A termination resistor of
100Ω should be selected to match the media, and is located
as close to the receiver input pins as possible. The termination resistor converts the driver output (current mode) into a
voltage that is detected by the receiver.Other configurations
are possible such as a multi-receiver configuration, but the
effects of a mid-stream connector(s), cable stub(s), and
other impedance discontinuities as well as ground shifting,
noise margin limits, and total termination loading must be
taken into account.
The DS90LV028A differential line receiver is capable of detecting signals as low as 100 mV,over a
±
1V common-mode
range centered around +1.2V.This is related to the driver off-
DS100077-3
FIGURE 1. Receiver Propagation Delay and Transition Time Test Circuit
DS100077-4
FIGURE 2. Receiver Propagation Delay and Transition Time Waveforms
Balanced System
DS100077-5
FIGURE 3. Point-to-Point Application
3 www.national.com
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