NSC DS90LV012ATMFX, DS90LV012ATMF, DS90LV012ATLDX, DS90LV012ATLD Datasheet
DS90LV012A/DS90LT012A
3V LVDS Single CMOS Differential Line Receiver
General Description
The DS90LV012A and DS90LT012A are single CMOS differential line receivers designed for applications requiring ultra
low power dissipation, low noise, and high data rates. The
devices are designed to support data rates in excess of 400
Mbps (200 MHz) utilizing Low Voltage Differential Swing
(LVDS) technology
The DS90LV012A and DS90LT012A accept low voltage (350
mV typical) differential input signals and translates them to
3V CMOS output levels. The receivers also support open,
shorted, and terminated (100Ω) input fail-safe. The receiver
output will be HIGH for all fail-safe conditions. The
DS90LV012A has a pinout designed for easy PCB layout.
The DS90LT012A includes an input line termination resistor
for point-to-point applications.
The DS90LV012A and DS90LT012A, and companion LVDS
line driver provide a new alternative to high power PECL/
ECL devices for high speed interface applications.
Features
n Compatible with ANSI TIA/EIA-644-A Standard
n
>
400 Mbps (200 MHz) switching rates
n 100 ps differential skew (typical)
n 3.5 ns maximum propagation delay
n Integrated line termination resistor (102Ω typical)
n Single 3.3V power supply design (2.7V to 3.6V range)
n Power down high impedance on LVDS inputs
n Accepts small swing (350 mV typical) differential signal
levels
n LVDS receiver inputs accept LVDS/BLVDS/LVPECL
inputs
n Supports open, short and terminated input fail-safe
n Pinout simplifies PCB layout
n Low Power Dissipation (10mW typical
@
3.3V static)
n SOT-23 5-lead package
n Leadless LLP-8 package (3x3 mm body size)
n SOT version pin compatible with SN65LVDS2,
SN65LVDT2
n Electrically similar to the DS90LV018A
n Fabricated with advanced CMOS process technology
n Industrial temperature operating range
(−40˚C to +85˚C)
Connection Diagrams
20015026
(Top View)
Order Number DS90LV012ATMF, DS90LT012ATMF
See NS Package Number MF05A
20015027
(Top View)
Order Number DS90LV012ATLD, DS90LT012ATLD
See NS Package Number LDA08A
Functional Diagram
DS90LV012A
20015002
DS90LT012A
20015025
Truth Table
INPUTS OUTPUT
[IN+] − [IN−] TTL OUT
V
ID
≥ 0V H
V
ID
≤ −0.1V L
Full Fail-safe OPEN/SHORT or
Terminated
H
August 2002
DS90LV012A/DS90LT012A 3V LVDS Single CMOS Differential Line Receiver
© 2002 National Semiconductor Corporation DS200150 www.national.com
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage (V
DD
) −0.3V to +4V
Input Voltage (IN+, IN−) −0.3V to +3.9V
Output Voltage (TTL OUT) −0.3V to (V
DD
+ 0.3V)
Output Short Circuit Current −100mA
Maximum Package Power Dissipation
@
+25˚C
LDA Package 2.26 W
Derate LDA Package 18.1 mW/˚C above +25˚C
Thermal resistance (θ
JA
) 55.3˚C/W
MF Package 902mW
Derate MF Package 7.22 mW/˚C above +25˚C
Thermal resistance (θ
JA
) 138.5˚C/W
Storage Temperature Range −65˚C to +150˚C
Lead Temperature Range Soldering
(4 sec.) +260˚C
Maximum Junction
Temperature +150˚C
ESD Ratings (Note 4)
Recommended Operating
Conditions
Min Typ Max Units
Supply Voltage (V
DD
) +2.7 +3.3 +3.6 V
Operating Free Air
Temperature (T
A
) −40 25 +85 ˚C
Electrical Characteristics
Over Supply Voltage and Operating Temperature ranges, unless otherwise specified. (Notes 2, 3)
Symbol Parameter Conditions Pin Min Typ Max Units
V
TH
Differential Input High Threshold VCMdependant on VDD(Note 11) IN+, IN− −30 0 mV
V
TL
Differential Input Low Threshold −100 −30 mV
V
CM
Common-Mode Voltage VDD= 2.7V, VID= 100mV 0.05 2.35 V
V
DD
= 3.0V to 3.6V, VID= 100mV 0.05 VDD- 0.3V V
I
IN
Input Current (DS90LV012A) VIN= +2.8V VDD= 3.6V or 0V −10
±
1 +10 µA
V
IN
= 0V −10
±
1 +10 µA
V
IN
= +3.6V VDD= 0V −20 +20 µA
∆I
IN
Change in Magnitude of I
IN
VIN= +2.8V VDD= 3.6V or 0V 4 µA
V
IN
=0V 4 µA
V
IN
= +3.6V VDD=0V 4 µA
I
IND
Differential Input Current V
IN+
= +0.4V, V
IN−
= +0V
3 3.9 4.4 mA
(DS90LT012A) V
IN+
= +2.4V, V
IN−
= +2.0V
R
T
Integrated Termination Resistor
(DS90LT012A)
102 Ω
C
IN
Input Capacitance IN+ = IN− = GND 3 pF
V
OH
Output High Voltage IOH= −0.4 mA, VID= +200 mV TTL OUT 2.4 3.1 V
I
OH
= −0.4 mA, Inputs terminated 2.4 3.1 V
I
OH
= −0.4 mA, Inputs shorted 2.4 3.1 V
V
OL
Output Low Voltage IOL= 2 mA, VID= −200 mV 0.3 0.5 V
I
OS
Output Short Circuit Current V
OUT
= 0V (Note 5) −15 −50 −100 mA
V
CL
Input Clamp Voltage ICL= −18 mA −1.5 −0.7 V
I
DD
No Load Supply Current Inputs Open V
DD
5.4 9 mA
DS90LV012A/DS90LT012A
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Switching Characteristics
Over Supply Voltage and Operating Temperature ranges, unless otherwise specified. (Notes 6, 7)
Symbol Parameter Conditions Min Typ Max Units
t
PHLD
Differential Propagation Delay High to Low CL= 15 pF 1.0 1.8 3.5 ns
t
PLHD
Differential Propagation Delay Low to High VID= 200 mV 1.0 1.7 3.5 ns
t
SKD1
Differential Pulse Skew |t
PHLD−tPLHD
| (Note 8) (Figure 1 and Figure 2) 0 100 400 ps
t
SKD3
Differential Part to Part Skew (Note 9) 0 0.3 1.0 ns
t
SKD4
Differential Part to Part Skew (Note 10) 0 0.4 1.5 ns
t
TLH
Rise Time 350 800 ps
t
THL
Fall Time 175 800 ps
f
MAX
Maximum Operating Frequency (Note 12) 200 250 MHz
Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the devices
should be operated at these limits. The table of “Electrical Characteristics” specifies conditions of device operation.
Note 2: Current into device pins is defined as positive. Current out of device pins is defined as negative. All voltages are referenced to ground unless otherwise
specified (such as V
ID
).
Note 3: All typicals are given for: V
DD
= +3.3V and TA= +25˚C.
Note 4: ESD Ratings:
DS90LV012A:
HBM (1.5 kΩ, 100 pF) ≥ 2kV
EIAJ (0Ω, 200 pF) ≥ 900V
CDM ≥ 2000V
IEC direct (330Ω, 150 pF) ≥ 5kV
DS90LT012A:
HBM (1.5 kΩ, 100 pF) ≥ 2kV
EIAJ (0Ω, 200 pF) ≥ 700V
CDM ≥ 2000V
IEC direct (330Ω, 150 pF) ≥ 7kV
Note 5: Output short circuit current (I
OS
) is specified as magnitude only, minus sign indicates direction only. Only one output should be shorted at a time, do not
exceed maximum junction temperature specification.
Note 6: C
L
includes probe and jig capacitance.
Note 7: Generator waveform for all tests unless otherwise specified:f=1MHz, Z
O
=50Ω,trand tf(0% to 100%) ≤ 3 ns for IN±.
Note 8: t
SKD1
is the magnitude difference in differential propagation delay time between the positive-going-edge and the negative-going-edge of the same channel.
Note 9: t
SKD3
, part to part skew, is the differential channel-to-channel skew of any event between devices. This specification applies to devices at the same V
DD
and within 5˚C of each other within the operating temperature range.
Note 10: t
SKD4
, part to part skew, is the differential channel-to-channel skew of any event between devices. This specification applies to devices over the
recommended operating temperature and voltage ranges, and across process distribution. t
SKD4
is defined as |Max − Min| differential propagation delay.
Note 11: V
DD
is always higher than IN+ and IN− voltage. IN+ and IN− are allowed to have voltage range −0.05V to +2.35V when VDD= 2.7V and |VID|/2to
V
DD
− 0.3V when VDD= 3.0V to 3.6V. VIDis not allowed to be greater than 100 mV when VCM= 0.05V to 2.35V when VDD= 2.7V or when VCM=|VID|/2to
V
DD
− 0.3V when VDD= 3.0V to 3.6V.
Note 12: f
MAX
generator input conditions: tr=t
f
<
1 ns (0% to 100%), 50% duty cycle, differential (1.05V to 1.35 peak to peak). Output criteria: 60%/40% duty cycle,
V
OL
(max 0.4V), VOH(min 2.4V), load = 15 pF (stray plus probes). The parameter is guaranteed by design. The limit is based on the statistical analysis of the device
over the PVT range by the transition times (t
TLH
and t
THL
).
Parameter Measurement Information
20015003
FIGURE 1. Receiver Propagation Delay and Transition Time Test Circuit
DS90LV012A/DS90LT012A
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