NSC DS90CR564MTD Datasheet

DS90CR563/DS90CR564
LVDS 18-Bit Color Flat Panel Display (FPD) Link—
65 MHz

DS90CR563/DS90CR564 LVDS 18-Bit Color Flat Panel Display (FPD) Link—65 MHz

July 1997

General Description

The DS90CR563 transmitter converts 21 bits of CMOS/TTL
data into three LVDS (Low Voltage Differential Signaling)
data streams. A phase-locked transmit clock is transmitted in
parallel with the data streams over a fourth LVDS link. Every
cycle of the transmit clock 21 bits of input data are sampled
and transmitted. The DS90CR564 receiver converts the
LVDS data streams back into 21 bits of CMOS/TTL data. At
a transmit clock frequency of 65 MHz, 18 bits of RGB data
and 3 bits of LCD timing and control data (FPLINE,
FPFRAME, DRDY) are transmitted at a rate of 455 Mbps per
LVDSdata channel. Using a 65 MHz clock, the data through­put is 171 Mbytes per second. These devices are offered
with rising edge data strobes for convenient interface with a
variety of graphics and LCD panel controllers.

This chipset is an ideal means to solve EMI and cable size
problems associated with wide, high speed TTL interfaces.

Block Diagrams

DS90CR563

Features

n 20 to 65 MHz shift clk support
n Up to 171 Mbytes/s bandwidth
n Cable size is reduced to save cost
n 290 mV swing LVDS devices for low EMI
n Low power CMOS design (
n Power-down mode saves power (
n PLL requires no external components
n Low profile 48-lead TSSOP package
n Rising edge data strobe
n Compatible with TIA/EIA-644 LVDS standard
n Single pixel per clock XGA (1024 x 768)
n Supports VGA, SVGA, XGA and higher
n 1.3 Gbps throughput

<

550 mW typ)

DS90CR564

<

0.25 mW)

DS012617-2

Order Number DS90CR563MTD

See NS Package Number MTD48

TRI-STATE®is a registered trademark of National Semiconductor Corporation.

© 1998 National Semiconductor Corporation DS012617 www.national.com

Order Number DS90CR564MTD

See NS Package Number MTD48

DS012617-1

Block Diagrams (Continued)

DS012617-3

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Absolute Maximum Ratings (Note 1)

If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.

Supply Voltage (V
CMOS/TTL Input Voltage −0.3V to (V
CMOS/TTL Output Voltage −0.3V to (V
LVDS Receiver Input Voltage −0.3V to (V
LVDS Driver Output Voltage −0.3V to (V
LVDS Output Short Circuit

Duration Continuous
Junction Temperature +150˚C
Storage Temperature −65˚C to +150˚C
Lead Temperature

(Soldering, 4 sec) +260˚C

Maximum Package Power Dissipation

MTD48 (TSSOP) Package:

) −0.3V to +6V

CC

@

CC
CC
CC
CC

+25˚C

+ 0.3V)
+ 0.3V)
+ 0.3V)
+ 0.3V)

DS90CR563 1.98W
DS90CR564 1.89W

Package Derating:

DS90CR563 16 mW/˚C above +25˚C
DS90CR564 15 mW/˚C above +25˚C

This device does not meet 2000V ESD rating (Note 4).

Recommended Operating
Conditions

Supply Voltage (V

) 4.75 5.0 5.25 V

CC

Operating Free Air −10 +25 +70 ˚C

Temperature (T

)

A

Receiver Input Range 0 2.4 V
Supply Noise Voltage (V

Min Nom Max Units

) 100 mV

CC

Electrical Characteristics

Over recommended operating supply and temperature ranges unless otherwise specified

Symbol Parameter Conditions Min Typ Max Units

CMOS/TTL DC SPECIFICATIONS

V

High Level Input Voltage 2.0 V

IH

V

Low Level Input Voltage GND 0.8 V

IL

V

High Level Output Voltage I

OH

V

Low Level Output Voltage I

OL

V

Input Clamp Voltage I

CL

I

Input Current V

IN

I

Output Short Circuit Current V

OS

=

−0.4 mA 3.8 4.9 V

OH

=

2 mA 0.1 0.3 V

OL

=

−18 mA −0.79 −1.5 V

CL

=

, GND, 2.5V or 0.4V

V

IN

CC

=

0V −120 mA

OUT

LVDS DRIVER DC SPECIFICATIONS

V

Differential Output Voltage R

OD

∆V

Change in VODbetween

OD

Complementary Output States
Common Mode Voltage 1.1 1.25 1.375 V

V

CM

∆V

Change in VCMbetween

CM

Complementary Output States
High Level Output Voltage 1.3 1.6 V

V

OH

V

Low Level Output Voltage 0.9 1.01 V

OL

I

Output Short Circuit Current V

OS

I

Output TRI-STATE®Current Power Down=0V, V

OZ

=

100Ω 250 290 450 mV

L

=

=

OUT

0V, R

100Ω −2.9 −5 mA

L

OUT

=

0V or V

CC

LVDS RECEIVER DC SPECIFICATIONS

V

Differential Input High

TH

Threshold
Differential Input Low Threshold −100 mV

V

TL

I

Input Current V

IN

=

V

+1.2V +100 mV

CM

=

+2.4V V

IN

=

V

0V

IN

=

5.5V

CC

TRANSMITTER SUPPLY CURRENT

I

Transmitter Supply Current,

CCTW

Worst Case

I

Transmitter Supply Current,

CCTG

16 Grayscale

=

R

100Ω,C

L

Worst Case Pattern

Figures 1, 3

(

=

R

100Ω,C

L

16 Grayscale Pattern

Figures 2, 3

(

=

5 pF,

L

)

=

5 pF,

L

)

f=32.5 MHz 49 63 mA
f=37.5 MHz 51 64 mA
f=65 MHz 70 84 mA
f=32.5 MHz 40 55 mA
f=37.5 MHz 41 55 mA
f=65 MHz 55 67 mA

±

5.1±10 µA

±1±

CC

35 mV

35 mV

10 µA

±

10 µA

±

10 µA

V

P-P

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Electrical Characteristics (Continued)

Over recommended operating supply and temperature ranges unless otherwise specified

Symbol Parameter Conditions Min Typ Max Units

TRANSMITTER SUPPLY CURRENT

I

Transmitter Supply Current,

CCTZ

Power Down

Power Down=Low

125µA

RECEIVER SUPPLY CURRENT

I

Receiver Supply Current,

CCRW

Worst Case

I

Receiver Supply Current,

CCRG

16 Grayscale

I

Receiver Supply Current,

CCRZ

Power Down

Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the device
should be operated at these limits. The tables of “Electrical Characteristics” specify conditions for device operation.

Note 2: Typical values are given for V
Note 3: Current into device pins is defined as positive. Current out of device pins is defined as negative. Voltages are referenced to ground unless otherwise speci-

fied (except V
Note 4: ESD Rating: HBM (1.5 kΩ, 100 pF)

and ∆VOD).

OD

PLL V

≥ 1000V

CC

All other pins ≥ 2000V
EIAJ (0Ω, 200 pF) ≥ 150V

CC

=

5.0V and T

=

C

8 pF,

L

Worst Case Pattern

Figures 1, 4

(
C

L

16 Grayscale Pattern

Figures 2, 4

(

=

)

8 pF,

)

f=32.5 MHz 64 77 mA
f=37.5 MHz 70 85 mA
f=65 MHz 110 140 mA
f=32.5 MHz 35 55 mA
f=37.5 MHz 37 55 mA
f=65 MHz 55 67 mA

Power Down=Low 110µA

=

+25˚C.

A

Transmitter Switching Characteristics

Over recommended operating supply and temperature ranges unless otherwise specified

Symbol Parameter Min Typ Max Units

Figure 3

LLHT LVDS Low-to-High Transition Time (
LHLT LVDS High-to-Low Transition Time (
TCIT TxCLK IN Transition Time (

Figure 5

TCCS TxOUT Channel-to-Channel Skew (Note 5) (
TCCD TxCLK IN to TxCLK OUT Delay

(

Figure 9

)
TCIP TxCLK IN Period (
TCIH TxCLK IN High Time (
TCIL TxCLK IN Low Time (

Figure 7

Figure 7

Figure 7

TSTC TxIN Setup to TxCLK IN (
THTC TxIN Hold to TxCLK IN (
TPDD Transmitter Powerdown Delay (

@

25˚C, V

) 15 T 50 ns

) 0.35T 0.5T 0.65T ns

) 0.35T 0.5T 0.65T ns

Figure 7

)f

Figure 7

) 2.5 1.5 ns

Figure 18

TPLLS Transmitter Phase Lock Loop Set (
TPPos0 Transmitter Output Pulse Position 0 (
TPPos1 Transmitter Output Pulse Position 1 1.70 1/7 T
TPPos2 Transmitter Output Pulse Position 2 3.60 2/7 T
TPPos3 Transmitter Output Pulse Position 3 5.90 3/7 T
TPPos4 Transmitter Output Pulse Position 4 8.30 4/7 T
TPPos5 Transmitter Output Pulse Position 5 10.40 5/7 T
TPPos6 Transmitter Output Pulse Position 6 12.70 6/7 T

Note 5: This limit based on bench characterization.

) 0.75 1.5 ns

Figure 3

) 0.75 1.5 ns

)8ns

Figure 6

) 350 ps

=

5.0V 3.5 8.5 ns

CC

=

65 MHz 5 3.5 ns

) 100 ns

Figure 11

)10ms

Figure 13

) −0.30 0 0.30 ns

2.50 ns

clk

4.50 ns

clk

6.75 ns

clk

9.00 ns

clk

11.10 ns

clk

13.40 ns

clk

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