NSC DS90CR483VJDX, DS90CR483VJD, CLINK3V48BT-112 Datasheet
DS90CR483 / DS90CR484
48-Bit LVDS Channel Link Serializer/Deserializer
General Description
The DS90CR483 transmitter converts 48 bits of CMOS/TTL
data into eight LVDS (Low Voltage Differential Signaling)
data streams.Aphase-locked transmit clockis transmitted in
parallel with the data streams over a ninth LVDS link. Every
cycle of the transmit clock 48 bits of input data are sampled
and transmitted. The DS90CR484 receiver converts the
LVDS data streams back into 48 bits of CMOS/TTL data. At
a transmit clock frequency of 112MHz, 48 bits of TTL data
are transmitted at a rate of 672Mbps per LVDSdata channel.
Using a 112MHz clock, the data throughput is 5.38Gbit/s
(672Mbytes/s).
The multiplexing of data lines provides a substantial cable
reduction. Long distance parallel single-ended buses typically require a ground wire per active signal (and have very
limited noise rejection capability). Thus, for a 48-bit wide
data and one clock, up to 98 conductors are required. With
this Channel Link chipset as few as 19 conductors (8 data
pairs, 1 clock pair and a minimum of one ground) are
needed. This provides an 80% reduction in cable width,
which provides a system cost savings, reduces connector
physical size and cost, and reduces shielding requirements
due to the cables’ smaller form factor.
The 48 CMOS/TTL inputs can support a variety of signal
combinations. For example, 6 8-bit words or 5 9-bit (byte +
parity) and 3 controls.
The DS90CR483/DS90CR484 chipset is improved over prior
generations of Channel Link devices and offers higher bandwidth support and longer cable drive with three areas of enhancement. To increase bandwidth, the maximum clock rate
is increased to 112 MHz and 8 serialized LVDS outputs are
provided. Cable drive is enhanced with a user selectable
pre-emphasis feature that provides additional output current
during transitions to counteract cable loading effects. DC
balancing on a cycle-to-cycle basis, is also provided to reduce ISI (Inter-Symbol Interference). With pre-emphasis and
DC balancing, a low distortion eye-pattern is provided at the
receiver end of the cable. A cable deskew capability has
been added to deskew long cables of pair-to-pair skew of up
to +/−1 LVDS data bit time (up to 80 MHz Clock Rate). These
three enhancements allow cables 5+ meters in length to be
driven.
The chipset is an ideal means to solve EMI and cable size
problems associated with wide, high speed TTL interfaces.
For more details, please refer to the “Applications Information” section of this datasheet.
Features
n Up to 5.38 Gbits/sec bandwidth
n 33 MHz to 112 MHz input clock support
n LVDS SER/DES reduces cable and connector size
n Pre-emphasis reduces cable loading effects
n DC balance data transmission provided by transmitter
reduces ISI distortion
n Cable Deskew of +/−1 LVDS data bit time (up to 80
MHz Clock Rate)
n 5V Tolerant TxIN and control input pins
n Flow through pinout for easy PCB design
n +3.3V supply voltage
n Transmitter rejects cycle-to-cycle jitter
n Conforms to ANSI/TIA/EIA-644-1995 LVDS Standard
Generalized Block Diagrams
TRI-STATE®is a registered trademark of National Semiconductor Corporation.
DS100918-1
February 2000
DS90CR483/DS90CR484 48-Bit LVDS Channel Link Serializer / Deserializer
© 2000 National Semiconductor Corporation DS100918 www.national.com
Generalized Transmitter Block Diagram
Generalized Receiver Block Diagram
DS100918-2
DS100918-3
DS90CR483/DS90CR484
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Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage (V
CC
) −0.3V to +4V
CMOS/TTL Input Voltage −0.3V to +5.5V
CMOS/TTL Output
Voltage −0.3V to (V
CC
+ 0.3V)
LVDS Receiver Input
Voltage −0.3V to +3.6V
LVDS Driver Output
Voltage −0.3V to +3.6V
LVDS Output Short Circuit
Duration Continuous
Junction Temperature +150˚C
Storage Temperature −65˚C to +150˚C
Lead Temperature
(Soldering, 4 sec.) +260˚C
Maximum Package Power Dissipation Capacity
@
25˚C
100 TQFP Package:
DS90CR483 2.8W
DS90CR484 2.8W
Package Derating:
DS90CR483 18.2mW/˚C above +25˚C
DS90CR484 18.2mW/˚C above +25˚C
ESD Rating:
DS90CR483
(HBM, 1.5kΩ, 100pF)
>
6kV
(EIAJ, 0Ω, 200pF)
>
300 V
DS90CR484
(HBM, 1.5kΩ, 100pF)
>
2kV
(EIAJ, 0Ω, 200pF)
>
200 V
Recommended Operating
Conditions
Min Nom Max Units
Supply Voltage (V
CC
) 3.0 3.3 3.6 V
Operating Free Air
Temperature (T
A)
−10 +25 +70 ˚C
Receiver Input Range 0 2.4 V
Supply Noise Voltage (V
CC
) 100 mV
p-p
Electrical Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Units
CMOS/TTL DC SPECIFICATIONS
V
IH
High Level Input
Voltage
2.0 V
CC
V
V
IL
Low Level Input
Voltage
GND 0.8 V
V
OH
High Level Output
Voltage
IOH= −0.4 mA 2.7 2.9 V
I
OH
= −2mA 2.7 2.85 V
V
OL
Low Level Output
Voltage
IOL= 2 mA 0.1 0.3 V
V
CL
Input Clamp Voltage ICL= −18 mA −0.79 −1.5 V
I
IN
Input Current VIN= 0.4V, 2.5V or V
CC
+1.8 +15 µA
V
IN
= GND −15 0 µA
I
OS
Output Short Circuit
Current
V
OUT
= 0V −120 mA
LVDS DRIVER DC SPECIFICATIONS
V
OD
Differential Output
Voltage
RL= 100Ω 250 345 450 mV
∆V
OD
Change in V
OD
between
Complimentary Output
States
35 mV
V
os
Offset Voltage 1.125 1.25 1.375 V
∆V
os
Change in V
os
between
Complimentary Output
States
35 mV
I
OS
Output Short Circuit
Current
V
OUT
= 0V, RL= 100Ω −3.5 −5 mA
I
OZ
Output TRI-STATE
®
Current
PD = 0V, V
OUT
=0VorV
CC
±
1
±
10 µA
DS90CR483/DS90CR484
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Electrical Characteristics (Continued)
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Units
LVDS RECEIVER DC SPECIFICATIONS
V
TH
Differential Input High
Threshold
VCM= +1.2V +100 mV
V
TL
Differential Input Low
Threshold
−100 mV
I
IN
Input Current VIN= +2.4V, VCC= 3.6V
±
10 µA
V
IN
= 0V, VCC= 3.6V
±
10 µA
TRANSMITTER SUPPLY CURRENT
ICCTW Transmitter Supply
Current
Worst Case
R
L
= 100Ω,CL= 5 pF,
Worst Case Pattern
(
Figures 1, 2
)
f = 33 MHz 91.4 140 mA
f = 66 MHz 106 160 mA
f = 112 MHz 155 190 mA
ICCTZ Transmitter Supply
Current
Power Down
PD = Low
550µA
Driver Outputs in TRI-STATE under Powerdown
Mode
RECEIVER SUPPLY CURRENT
ICCRW Receiver Supply
Current
Worst Case
C
L
= 8 pF,
Worst Case Pattern
(
Figures 1, 3
)
f = 33 MHz 125 150 mA
f = 66 MHz 215 250 mA
f = 112 MHz 350 380 mA
ICCRZ Receiver Supply
Current
Power Down
PD = LowReceiver Outputs stay low during
Power down mode.
20 100 µA
Recommended Transmitter Input Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol Parameter Min Typ Max Units
TCIT TxCLK IN Transition Time (
Figure 4
) 1.0 2.0 3.0 ns
TCIP TxCLK IN Period (
Figure 5
) 8.928 T 30.3 ns
TCIH TxCLK in High Time (
Figure 5
) 0.35T 0.5T 0.65T ns
TCIL TxCLK in Low Time (
Figure 5
) 0.35T 0.5T 0.65T ns
TXIT TxIN Transition Time 1.5 6.0 ns
Transmitter Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol Parameter Min Typ Max Units
LLHT LVDS Low-to-High Transition Time, (
Figure 2
),
PRE = 0.75V (disabled)
0.14 0.7 ns
LVDS Low-to-High Transition Time, (
Figure 2
),
PRE = Vcc (max)
0.11 0.6 ns
LHLT LVDS High-to-Low Transition Time, (
Figure 2
),
PRE = 0.75V (disabled)
0.16 0.8 ns
LVDS High-to-Low Transition Time, (
Figure 2
),
PRE = Vcc (max)
0.11 0.7 ns
TBIT Transmitter Bit Width 1/7 TCIP ns
TCCS TxOUT Channel to Channel Skew 100 ps
TSTC TxIN Setup to TxCLK IN, (
Figure 5
) 2.5 ns
THTC TxIN Hold to TxCLK IN, (
Figure 5
)0 ns
TPDL Transmitter Propagation Delay - Latency, (
Figure 7
) 1.5(TCIP)+3.72 1.5(TCIP)+4.4 1.5(TCIP)+6.24 ns
TPLLS Transmitter Phase Lock Loop Set, (
Figure 9
)10ms
TPDD Transmitter Powerdown Delay, (
Figure 11
) 100 ns
DS90CR483/DS90CR484
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Receiver Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol Parameter Min Typ Max Units
CLHT CMOS/TTL Low-to-High Transition Time, (
Figure 3
),
Rx data out
2.0 ns
CMOS/TTL Low-to-High Transition Time, (
Figure 3
),
Rx clock out
1.0 ns
CHLT CMOS/TTL High-to-Low Transition Time, (
Figure 3
),
Rx data out
2.0 ns
CMOS/TTL High-to-Low Transition Time, (
Figure 3
),
Rx clock out
1.0 ns
RCOP RxCLK OUT Period, (
Figure 6
) 8.928 T 30.3 ns
RCOH RxCLK OUT High Time, (
Figure
6
), (Note 4)
f = 112 MHz 3.5 ns
f = 66 MHz 6.0 ns
RCOL RxCLK OUT Low Time, (
Figure 6
),
(Note 4)
f = 112 MHz 3.5 ns
f = 66 MHz 6.0 ns
RSRC RxOUT Setup to RxCLK OUT,
(
Figure 6
), (Note 4)
f = 112 MHz 2.4 ns
f = 66 MHz 3.6 ns
RHRC RxOUT Hold to RxCLK OUT,
(
Figure 6
), (Note 4)
f = 112 MHz 3.4 ns
f = 66 MHz 7.0 ns
RPDL Receiver Propagation Delay - Latency, (
Figure 8
) 3(TCIP)+4.0 3(TCIP)+4.8 3(TCIP)+6.5 ns
RPLLS Receiver Phase Lock Loop Set ,(
Figure 10
)10ms
RPDD Receiver Powerdown Delay, (
Figure 12
)1µs
RSKM Receiver Skew Margin without
Deskew, (
Figure 13
), (Notes 4, 5)
f = 112 MHz 170 210 ps
f = 85 MHz 160 200 ps
f = 66 MHz 210 275 ps
RDR Receiver Deskew Range f = 80 MHz
±
1.786
(
±
1TBIT)
(
±
1.3 TBIT) ns
RDSS Receiver Deskew Step Size f = 80 MHz 0.3 TBIT ns
Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the device
should be operated at these limits. The tables of “Electrical Characteristics” specify conditions for device operation.
Note 2: Typical values are given for V
CC
= 3.3V and TA= +25˚C.
Note 3: Current into device pins is defined as positive. Current out of device pins is defined as negative. Voltagesare referenced to ground unless otherwise specified (except V
TH,VTL,VOD
and ∆VOD).
Note 4: The Minimum and Maximum Limits are based on statistical analysis of the device performance over voltage and temperature ranges. This parameter is functionally tested on Automatic Test Equipment (ATE). ATE is limited to 85MHz. A sample of characterization parts have been bench tested to verify functional performance.
Note 5: Receiver Skew Margin is defined as the valid data sampling region at the receiver inputs. This margin takes into account transmitter output pulse positions
(min and max) and the receiver input setup and hold time (internal data sampling window - RSPOS). This margin allows for LVDS interconnect skew, inter-symbol
interference (both dependent on type/length of cable) and clock jitter.
RSKM ≥ cable skew (type, length) + source clock jitter (cycle to cycle).
DS90CR483/DS90CR484
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AC Timing Diagrams
Note 6: The worst case test pattern produces a maximum toggling of digital circuits, LVDS I/O and CMOS/TTL I/O.
DS100918-10
FIGURE 1. “Worst Case” Test Pattern
DS100918-12
FIGURE 2. DS90CR483 (Transmitter) LVDS Output Load and Transition Times
DS100918-13
FIGURE 3. DS90CR484 (Receiver) CMOS/TTL Output Load and Transition Times
DS100918-14
FIGURE 4. DS90CR483 (Transmitter) Input Clock Transition Time
DS100918-15
FIGURE 5. DS90CR483 (Transmitter) Setup/Hold and High/Low Times
DS90CR483/DS90CR484
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