NSC DS90CR284MTDX, DS90CR284MTD, DS90CR284MDC Datasheet
DS90CR283/DS90CR284
28-Bit Channel Link-66 MHz
General Description
The DS90CR283 transmitter converts 28 bits of CMOS/TTL
data intofour LVDS (Low Voltage Differential Signaling) data
streams. A phase-locked transmit clock is transmitted in parallel with the data streams over a fifth LVDS link. Every cycle
of the transmit clock 28 bits of input data are sampled and
transmitted. The DS90CR284 receiver converts the LVDS
data streams back into 28 bits of CMOS/TTL data. At a transmit clock frequency of 66 MHz, 28 bits of TTL data are transmitted at a rate of 462 Mbps per LVDS data channel. Using
a 66 MHz clock, the data throughput is 1.848 Gbit/s
(231 Mbytes/s).
The multiplexing of the data lines provides a substantial
cable reduction. Long distance parallel single-ended buses
typically require a ground wire per active signal (and have
very limited noise rejection capability). Thus, for a 28-bit wide
data bus and one clock, up to 58 conductors are required.
With the Channel Link chipset as few as 11 conductors (4
data pairs, 1 clock pair and a minimum of one ground) are
needed. This provides a 80%reduction in required cable
width, which provides a system cost savings, reduces connector physical size and cost, and reduces shielding requirements due to the cables’ smaller form factor.
The 28 CMOS/TTL inputs can support a variety of signal
combinations. For example, 7 4-bit nibbles or 3 9-bit (byte +
parity) and 1 control.
Features
n 66 MHz clock support
n Up to 231 Mbytes/s bandwidth
n Low power CMOS design (
<
610 mW)
n Power Down mode (
<
0.5 mW total)
n Up to 1.848 Gbit/s data throughput
n Narrow bus reduces cable size and cost
n 290 mV swing LVDS devices for low EMI
n PLL requires no external components
n Low profile 56-lead TSSOP package
n Rising edge data strobe
n Compatible with TIA/EIA-644 LVDS Standard
Block Diagrams
TRI-STATE®is a registered trademark of National Semiconductor Corporation.
DS90CR283
DS012889-27
Order Number DS90CR283MTD
See NS Package Number MTD56
DS90CR284
DS012889-1
Order Number DS90CR284MTD
See NS Package Number MTD56
July 1997
DS90CR283/DS90CR284 28-Bit Channel Link-66 MHz
© 1998 National Semiconductor Corporation DS012889 www.national.com
Pin Diagrams
Typical Application
DS90CR283
DS012889-21
DS90CR284
DS012889-22
DS012889-23
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Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage (V
CC
) −0.3V to +6V
CMOS/TTL Input Voltage −0.3V to (V
CC
+ 0.3V)
CMOS/TTL Ouput Voltage −0.3V to (V
CC
+ 0.3V)
LVDS Receiver Input Voltage −0.3V to (V
CC
+ 0.3V)
LVDS Driver Output Voltage −0.3V to (V
CC
+ 0.3V)
LVDS Output Short Circuit
Duration Continuous
Junction Temperature +150˚C
Storage Temperature Range −65˚C to +150˚C
Lead Temperature
(Soldering, 4 sec.) +260˚C
Maximum Package Power Dissipation
@
+25˚C
MTD56(TSSOP) Package:
DS90CR283 1.63W
DS90CR284 1.61W
Package Derating:
DS90CR283 12.5 mW/˚C above +25˚C
DS90CR284 12.4 mW/˚C above +25˚C
This device does not meet 2000V ESD rating (Note 4)
Recommended Operating
Conditions
Min Nom Max Units
Supply Voltage (V
CC
) 4.75 5.0 5.25 V
Operating Free Air
Temperature (T
A
) −10 +25 +70 ˚C
Receiver Input Range 0 2.4 V
Supply Noise Voltage
(V
CC
) 100 mV
P-P
Electrical Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified
Symbol Parameter Conditions Min Typ Max Units
CMOS/TTL DC SPECIFICATIONS
V
IH
High Level Input Voltage 2.0 V
CC
V
V
IL
Low Level Input Voltage GND 0.8 V
V
OH
High Level Output Voltage I
OH
=
−0.4 mA 3.8 4.9 V
V
OL
Low Level Output Voltage I
OL
=
2 mA 0.1 0.3 V
V
CL
Input Clamp Voltage I
CL
=
−18 mA −0.79 −1.5 V
I
IN
Input Current V
IN
=
V
CC
, GND, 2.5V or 0.4V
±
5.1
±
10 µA
I
OS
Output Short Circuit Current V
OUT
=
0V −120 mA
LVDS DRIVER DC SPEClFlCATIONS
V
OD
Differential Output Voltage R
L
=
100Ω 250 290 450 mV
∆V
OD
Change in VODbetween 35 mV
Complementary Output States
V
OS
Offset Voltage 1.1 1.25 1.375 V
∆V
OS
Change in Magnitude of V
OS
between Complementary Output
States
35 mV
I
OS
Output Short Circuit Current V
OUT
=
OV, R
L
=
100Ω −2.9 −5 mA
I
OZ
Output TRI-STATE®Current Power Down=0V, V
OUT
=
0V or V
CC
±
1
±
10 µA
LVDS RECEIVER DC SPECIFlCATIONS
V
TH
Differential Input High Threshold V
CM
=
+1.2V +100 mV
V
TL
Differential Input Low Threshold −100 mV
I
IN
Input Current V
IN
=
+2.4V, V
CC
=
5.0V
±
10 µA
V
IN
=
0V, V
CC
=
5.0V
±
10 µA
TRANSMITTER SUPPLY CURRENT
I
CCTW
Transmitter Supply Current, R
L
=
100Ω,C
L
=
5 pF, f=32.5 MHz 49 63 mA
Worst Case Worst Case Pattern f=37.5 MHz 51 64 mA
(
Figures 1, 2
)f
=
66 MHz 70 84 mA
I
CCTZ
Transmitter Supply Current, Power Down=Low
Power Down Driver Outputs in TRI-STATE
under Power Down Mode 1 25 µA
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Electrical Characteristics (Continued)
Over recommended operating supply and temperature ranges unless otherwise specified
Symbol Parameter Conditions Min Typ Max Units
RECEIVER SUPPLY CURRENT
I
CCRW
Receiver Supply Current,
Worst Case
C
L
=
8 pF, f=32.5 MHz 64 77 mA
Worst Case Pattern f=37.5 MHz 70 85 mA
(
Figures 1, 3
)f
=
66 MHz 110 140 mA
I
CCRZ
Receiver Supply Current, Power Down=Low
Power Down Receiver Outputs in Previous State
during Power Down Mode 1 10 µA
Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the device
should be operated at these limits. The tables of “Electrical Characteristics” specify conditions for device operation.
Note 2: Typical values are given for V
CC
=
5.0V and T
A
=
+25˚C.
Note 3: Current into device pins is defined as positive. Current out of device pins is defined as negative. Voltages are referenced to ground unless otherwise specified (except V
OD
and ∆VOD).
Note 4: ESD Rating: HBM (1.5 kΩ, 100 pF)
PLL V
CC
≥ 1000V
All other pins ≥ 2000V
EIAJ (0Ω, 200 pF) ≥ 150V
Note 5: V
OS
previously referred as VCM.
Transmitter Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified
Symbol Parameter Min Typ Max Units
LLHT LVDS Low-to-High Transition Time (
Figure 2
) 0.75 1.5 ns
LHLT LVDS High-to-Low Transition Time (
Figure 2
) 0.75 1.5 ns
TCIT TxCLK IN Transition Time (
Figure 4
)8ns
TCCS TxOUT Channel-to-Channel Skew (Note 6) (
Figure 5
) 350 ps
TPPos0 Transmitter Output Pulse Position for Bit 0 f=66 MHz
−0.30 0 0.30
ns
(
Figure 16
)
TPPos1 Transmitter Output Pulse Position for Bit 1 1.70 (1/7)T
clk
2.50 ns
TPPos2 Transmitter Output Pulse Position for Bit 2 3.60 (2/7)T
clk
4.50 ns
TPPos3 Transmitter Output Pulse Position for Bit 3 5.90 (3/7)T
clk
6.75 ns
TPPos4 Transmitter Output Pulse Position for Bit 4 8.30 (4/7)T
clk
9.00 ns
TPPos5 Transmitter Output Pulse Position for Bit 5 10.40 (5/7)T
clk
11.10 ns
TPPos6 Transmitter Output Pulse Position for Bit 6 12.70 (6/7)T
clk
13.40
TCIP TxCLK IN Period (
Figure 6
) 15 T 50 ns
TCIH TxCLK IN High Time (
Figure 6
) 0.35T 0.5T 0.65T ns
TCIL TxCLK IN Low Time (
Figure 6
) 0.35T 0.5T 0.65T ns
TSTC TxIN Setup to TxCLK IN (
Figure 6
) 5 3.5 ns
THTC TxIN Hold to TxCLK IN (
Figure 6
) 2.5 1.5 ns
TCCD TxCLK IN to TxCLK OUT Delay
@
25˚C, 3.5 8.5 ns
V
CC
=
5.0V (
Figure 8
)
TPLLS Transmitter Phase Lock Loop Set (
Figure 10
)10ms
TPDD Transmitter Power Down Delay (
Figure 14
) 100 ns
Note 6: This limit based on bench characterization.
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Receiver Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified
Symbol Parameter Min Typ Max Units
CLHT CMOS/TTL Low-to-High Transition Time (
Figure 3
) 2.5 4.0 ns
CHLT CMOS/TTL High-to-Low Transition Time (
Figure 3
) 2.0 4.0 ns
RSKM RxIN Skew Margin (Note 7), f=40 MHz 700 ps
V
CC
=
5V, T
A
=
25˚C (
Figure 17
)f
=
66 MHz 600 ps
RCOP RxCLK OUT Period (
Figure 7
) 15 T 50 ns
RCOH RxCLK OUT High Time (
Figure 7
)f
=
40 MHz 6 ns
f=66 MHz 4.3 5 ns
RCOL RxCLK OUT Low Time (
Figure 7
)f
=
40 MHz 10.5 ns
f=66 MHz 7.0 9 ns
RSRC RxOUT Setup to RxCLK OUT (
Figure 7
)f
=
40 MHz 4.5 ns
f=66 MHz 2.5 4.2 ns
RHRC RxOUT Hold to RxCLK OUT (
Figure 7
)f
=
40 MHz 6.5 ns
f=66 MHz 4 5.2 ns
RCCD RxCLK IN to RxCLK OUT Delay
@
25˚C, 6.4 10.7 ns
V
CC
=
5.0V (
Figure 9
)
RPLLS Receiver Phase Lock Loop Set (
Figure 11
)10ms
RPDD Receiver Power Down Delay (
Figure 11
)1µs
Note 7: Receiver Skew Margin is defined as the valid data sampling region at the receiver inputs. This margin takes into account transmitter output skew (TCCS)
and the setup and hold time (internal data sampling window), allowing for LVDS cable skew dependent on type/length and source clock (TxCLK IN) jitter.
RSKM ≥ cable skew (type, length) + source clock jitter (cycle to cycle)
AC Timing Diagrams
DS012889-2
FIGURE 1. “WORST CASE” Test Pattern
DS012889-3
DS012889-4
FIGURE 2. DS90CR283 (Transmitter) LVDS Output Load and Transition Timing
DS012889-5
DS012889-6
FIGURE 3. DS90CR284 (Receiver) CMOS/TTL Output Load and Transition Timing
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