NSC DS90CF584MTDX, DS90CF584MTD Datasheet
DS90CF583/DS90CF584
LVDS 24-Bit Color Flat Panel Display (FPD) Link—
65 MHz
General Description
The DS90CF583 transmitter converts 28 bits of CMOS/TTL
data into four LVDS (Low Voltage Differential Signaling) data
streams. A phase-locked transmit clock is transmitted in parallel with the data streams over a fifthLVDS link. Every cycle
of the transmit clock 28 bits of input data are sampled and
transmitted. The DS90CF584 receiver converts the LVDS
data streams backinto 28 bitsof CMOS/TTL data.Ata transmit clock frequency of 65 MHz, 24 bits of RGB data and 4
bits of LCD timing and control data (FPLINE, FPFRAME,
DRDY, CONTROL) are transmitted at a rateof 455 Mbps per
LVDSdata channel. Usinga 65 MHz clock, thedata throughput is 227 Mbytes per second. These devices are offered
with falling edge data strobes for convenient interface with a
variety of graphics and LCD panel controllers.
This chipset is an ideal means to solve EMI and cable size
problems associated with wide, high speed TTL interfaces.
Features
n 20 to 65 MHz shift clk support
n Up to 227 Mbytes/s bandwidth
n Cable size is reduced to save cost
n 290 mV swing LVDS devices for low EMI
n Low power CMOS design (
<
550 mW typ)
n Power-down mode saves power (
<
0.25 mW)
n PLL requires no external components
n Low profile 56-lead TSSOP package
n Falling edge data strobe
n Compatible with TIA/EIA-644 LVDS standard
n Single pixel per clock XGA (1024 x 768)
n Supports VGA, SVGA, XGA and higher
n 1.8 Gbps throughput
Block Diagrams
TRI-STATE®is a registered trademark of National Semiconductor Corporation.
DS012616-24
Order Number DS90CF583MTD
See NS Package Number MTD56
DS012616-1
Order Number DS90CF584MTD
See NS Package Number MTD56
November 1996
DS90CF583/DS90CF584 LVDS 24-Bit Color Flat Panel Display (FPD) Link—65 MHz
© 1998 National Semiconductor Corporation DS012616 www.national.com
Block Diagrams (Continued)
DS012616-2
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Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage (V
CC
) −0.3V to +6V
CMOS/TTL Input Voltage −0.3V to (V
CC
+ 0.3V)
CMOS/TTL Output Voltage −0.3V to (V
CC
+ 0.3V)
LVDS Receiver Input Voltage −0.3V to (V
CC
+ 0.3V)
LVDS Driver Output Voltage −0.3V to (V
CC
+ 0.3V)
LVDS Output Short Circuit Duration Continuous
Junction Temperature +150˚C
Storage Temperature −65˚C to +150˚C
Lead Temperature (Soldering, 4 sec) +260˚C
Maximum Power Dissipation
@
25˚C
MTD56 (TSSOP) Package:
DS90CF583 1.63W
DS90CF584 1.61W
Package Derating:
DS90CF583 12.5 mW/˚C above +25˚C
DS90CF584 12.4 mW/˚C above +25˚C
This device does not meet 2000V ESD rating (Note 4) .
Recommended Operating
Conditions
Min Nom Max Units
Supply Voltage (V
CC
) 4.75 5.0 5.25 V
Operating Free Air −10 +25 +70 ˚C
Temperature (T
A
)
Receiver Input Range 0 2.4 V
Supply Noise Voltage (V
CC
) 100 mV
P-P
Electrical Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified
Symbol Parameter Conditions Min Typ Max Units
CMOS/TTL DC SPECIFICATIONS
V
IH
High Level Input Voltage 2.0 V
CC
V
V
IL
Low Level Input Voltage GND 0.8 V
V
OH
High Level Output Voltage I
OH
=
−0.4 mA 3.8 4.9 V
V
OL
Low Level Output Voltage I
OL
=
2 mA 0.1 0.3 V
V
CL
Input Clamp Voltage I
CL
=
−18 mA −0.79 −1.5 V
I
IN
Input Current V
IN
=
V
CC
, GND, 2.5V or 0.4V
±
5.1±10 µA
I
OS
Output Short Circuit Current V
OUT
=
0V −120 mA
LVDS DRIVER DC SPECIFICATIONS
V
OD
Differential Output Voltage R
L
=
100Ω 250 290 450 mV
∆V
OD
Change in VODbetween 35 mV
Complementary Output States
V
CM
Common Mode Voltage 1.1 1.25 1.375 V
∆V
CM
Change in VCMbetween 35 mV
Complementary Output States
V
OH
High Level Output Voltage 1.3 1.6 V
V
OL
Low Level Output Voltage 0.9 1.01 V
I
OS
Output Short Circuit Current V
OUT
=
0V, R
L
=
100Ω −2.9 −5 mA
I
OZ
Output TRI-STATE®Current Power Down=0V, V
OUT
=
0V or V
CC
±1±
10 µA
LVDS RECEIVER DC SPECIFICATIONS
V
TH
Differential Input High
Threshold
V
CM
=
+1.2V +100 mV
V
TL
Differential Input Low Threshold −100 mV
I
IN
Input Current V
IN
=
+2.4V V
CC
=
5.5V
±
10 µA
V
IN
=
0V
±
10 µA
TRANSMITTER SUPPLY CURRENT
I
CCTW
Transmitter Supply Current, R
L
=
100Ω,C
L
=
5 pF, f=32.5 MHz 49 63 mA
Worst Case Worst Case Pattern f=37.5 MHz 51 64 mA
(
Figure 1,Figure 3
)f
=
65 MHz 70 84 mA
I
CCTG
Transmitter Supply Current, R
L
=
100Ω,C
L
=
5 pF, f=32.5 MHz 40 55 mA
16 Grayscale 16 Grayscale Pattern f=37.5 MHz 41 55 mA
(
Figure 2,Figure 3
)f
=
65 MHz 55 67 mA
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Electrical Characteristics (Continued)
Over recommended operating supply and temperature ranges unless otherwise specified
Symbol Parameter Conditions Min Typ Max Units
TRANSMITTER SUPPLY CURRENT
I
CCTZ
Transmitter Supply Current, Power Down=Low 125µA
Power Down
RECEIVER SUPPLY CURRENT
I
CCRW
Receiver Supply Current, C
L
=
8 pF, f=32.5 MHz 64 77 mA
Worst Case Worst Case Pattern f=37.5 MHz 70 85 mA
(
Figure 1,Figure 4
)f
=
65 MHz 110 140 mA
I
CCRG
Receiver Supply Current, C
L
=
8 pF, f=32.5 MHz 35 55 mA
16 Grayscale 16 Grayscale Pattern f=37.5 MHz 37 55 mA
(
Figure 2,Figure 4
)f
=
65 MHz 55 67 mA
I
CCRZ
Receiver Supply Current, Power Down=Low 110µA
Power Down
Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the device
should be operated at these limits. The tables of “Electrical Characteristics” specify conditions for device operation.
Note 2: Typical values are given for V
CC
=
5.0V and T
A
=
+25˚C.
Note 3: Current into device pins is defined as positive. Current out of device pins is defined as negative. Voltages are referenced to ground unless otherwisespecified (except V
OD
and ∆VOD).
Note 4: ESD Rating: HBM (1.5 kΩ, 100 pF)
PLL V
CC
≥ 1000V
All other pins ≥ 2000V
EIAJ (0Ω, 200 pF) ≥ 150V
Transmitter Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified
Symbol Parameter Min Typ Max Units
LLHT LVDS Low-to-High Transition Time (
Figure 3
) 0.75 1.5 ns
LHLT LVDS High-to-Low Transition Time (
Figure 3
) 0.75 1.5 ns
TCIT TxCLK IN Transition Time (
Figure 5
)8ns
TCCS TxOUT Channel-to-Channel Skew (Note 5) (
Figure 6
) 350 ps
TCCD TxCLK IN to TxCLK OUT Delay
@
25˚C, V
CC
=
5.0V 3.5 8.5 ns
(
Figure 9
)
TCIP TxCLK IN Period (
Figure 7
) 15 T 50 ns
TCIH TxCLK IN High Time (
Figure 7
) 0.35T 0.5T 0.65T ns
TCIL TxCLK IN Low Time (
Figure 7
) 0.35T 0.5T 0.65T ns
TSTC TxIN Setup to TxCLK IN (
Figure 7
)f
=
65 MHz 5 3.5 ns
THTC TxIN Hold to TxCLK IN (
Figure 7
) 2.5 1.5 ns
TPDD Transmitter Powerdown Delay (
Figure 18
) 100 ns
TPLLS Transmitter Phase Lock Loop Set (
Figure 11
)10ms
TPPos0 Transmitter Output Pulse Position 0 (
Figure 13
) −0.30 0 0.30 ns
TPPos1 Transmitter Output Pulse Position 1 1.70 1/7 T
clk
2.50 ns
TPPos2 Transmitter Output Pulse Position 2 3.60 2/7 T
clk
4.50 ns
TPPos3 Transmitter Output Pulse Position 3 5.90 3/7 T
clk
6.75 ns
TPPos4 Transmitter Output Pulse Position 4 8.30 4/7 T
clk
9.00 ns
TPPos5 Transmitter Output Pulse Position 5 10.40 5/7 T
clk
11.10 ns
TPPos6 Transmitter Output Pulse Position 6 12.70 6/7 T
clk
13.40 ns
Note 5: This limit based on bench characterization.
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