General Description (Continued)
ductor, then developed by the IEEE to enhance the performance of backplane buses. BTL compatible transceivers
feature low output capacitance drivers to minimize bus loading, a 1V nominal signal swing for reduced power consumption and receivers with precision thresholds for maximum
noise immunity. BTL eliminates settling time delays that severely limit TTL bus performance, and thus provide significantly higher bus transfer rates. The backplane bus is intended to be operated with termination resistors (selected
to match the bus impedance) connected to 2.1V at both
ends. The low voltage is typically 1V.
Separate ground pins are provided for each BTL output to
minimize induced ground noise during simultaneous switching.
The transceiver’s control and driver inputs are designed
with high impedance PNP input structures and are fully TTL
compatible.
The receiver is a high speed comparator that utilizes a
bandgap reference for precision threshold control allowing
maximum noise immunity to the BTL 1V signaling level.
Separate QV
CC
and QGND pins are provided to minimize
the effects of high current switching noise. The output is
TRI-STATE
É
and fully TTL compatible.
The signals abk7:0ldesignate the arbitration bus number
which this transceiver places on the bus. The signal names
AB
k
7:0ldesignate the open collector Wired-OR signals
on the backplane bus.
The DS3885 implements an odd parity check on the arbitration bus bits AB
k
7:0l, with ABP being the parity bit. The
signal PER
will indicate the parity check result. For a quick
indication of current bus conditions, the bus status block
generates ALL1
(all asserted) status when all bits
(AB
k
7:0l) are asserted by any module. This signal is used
by the DS3875 Arbitration Controller to detect the Arbitration message number (during phase 1) or the powerfail message number (during phase 2).
To latch the arbitration number into the transceiver, it is
placed onto the CN
k
7:0lport, and the CNÐLE signal is
asserted. When the CMPT
signal is asserted, the arbitration
number is placed on the bus lines AB
k
7:0l. The WIN
Ð
GT
signal serves two purposes during the arbitration cycle. If
the CMPT
signal is not asserted during the arbitration cycle,
the transceiver compares its internally latched number to
the number on the AB
k
7:0lbus lines. If the internal number on the transceiver is greater than or equal to the number
on the AB
k
7:0llines, the WIN
Ð
GT
signal is asserted.
However, if the CMPT
signal is asserted, the transceiver
participates in the competition. If the transceiver wins the
arbitration, the WIN
Ð
GT
signal is asserted to confirm the
winning. The ABÐRE
signal is used to enable the on-chip
receiver outputs.
The DS3885 supports live insertion as defined in IEEE
896.2 through the LI (Live Insertion) pin. To implement live
insertion the LI pin should be connected to the live insertion
power connector. If this function is not supported the LI pin
must be tied to the V
CC
pin. The DS3885 also provides
glitch free power-up/down protection during power sequencing.
The DS3885 has two types of power connections in addition
to the LI pin. They are the Logic V
CC(VCC
) and the Quiet
V
CC
(QVCC). There are two VCCpins on the DS3885 that
provide the supply voltage for the logic and control circuitry.
Multiple power pins reduce the effects of package inductance and thereby minimize switching noise. As these pins
are common to the V
CC
bus internal to the device, a voltage
difference should never exist between these pins and the
voltage difference between V
CC
and QVCCshould never
exceed
g
0.5V because of ESD circuitry.
Additionally, the ESD circuitry between the V
CC
pins and all
other pins except for BTL I/O’s and LI pins requires that any
voltage on these pins should not exceed the voltage on V
CC
a
0.5V
There are three different types of ground pins on the
DS3885. They are the logic ground (GND), BTL grounds
(AB0GND–AB7GND/ABPGND) and the Bandgap reference ground (QGND). All of these reference pins are isolated within the chip to minimize the effects of high current
switching transients. For optimum performance the QGND
should be returned to the connector through a quiet channel
that does not carry transient switching current. The GND
and AB0GND – AB7GND/ABPGND should be connected to
the nearest backplane ground pin with the shortest possible
path.
Since many different grounding schemes could be implemented and ESD circuitry exists on the DS3885, it is important to note that any voltage difference between ground
pins, QGND, GND or AB0GND –AB7GND and ABPGND
should not exceed
g
0.5V including power-up/down se-
quencing.
Three additional transceivers are included in the Futurebus
a
family. They are the DS3883A BTL 9-bit Transceiver.
The DS3884A BTL Handshake Transceiver features selectable Wired-OR glitch filtering. The DS3886A BTL 9-bit
Latching Data Transceiver contains edge triggered latches
in the driver which may be bypassed during a fall-through
mode. In addition, the device contains a transparent latch in
the receiver section.
The DS3875 Arbitration Controller included in the Futurebus
a
family supports all the required and optional modes
for Futurebus
a
arbitration protocol. It is designed to be
used in conjunction with the DS3884A and DS3885 transceivers.
The LOGICAL INTERFACE FUTUREBUS
a
ENGINE (LIFE)
is a high performance Futurebus
a
Protocol Controller designed for IEEE 896.1. The LIFE will handle all handshaking
signals between the Futurebus
a
and the local bus inter-
face. The Protocol Controller supports the Futurebus
a
compelled mode data transfer as both master and slave.
The Protocol Controller can be configured to operate in
compliance to IEEE 896.2 Profile B mode. The LIFE incorporates a DMA controller and 64-bit FIFO’s for fast queuing.
All of the transceivers are offered in 44-pin PLCC and PQFP
high density package styles.
2