NSC DP83907VF Datasheet

DP83907 AT/LANTICTMII

DP83907 AT/LANTIC II

PRELIMINARY

November 1995

General Description

The DP83907 Twisted-Pair Enhanced Coaxial Network Interface Controller is a CMOS VLSI device designed for easy implementation of CSMA/CD local area networks.

Unique to the DP83907 is the integration of the entire bus interface for PCAT ISA (Industry Standard Architecture) bus based systems. Hardware and software selectable options allow the DP83907’s bus interface to be configured in the same manner as an NE2000 Architecture. All bus drivers and control logic are integrated to reduce board cost and area.

Supported network interfaces include 10BASE5 or 10BASE2 Ethernet via an external transceiver connected to its AUl port, and Twisted-pair Ethernet

(10BASE-T) using

the on-board transceiver. The DP83907 provides the Ethernet Media Access Control (MAC), Encode-Decode (ENDEC) with an AUl interface, and 10BASE-T transceiver functions in accordance with the lEEE 802.3 standards.

The DP83907’s integrated 10BASE-T transceiver fully complies with the IEEE standard. This functional block incorporates the receiver, transmitter, collision, heartbeat, loopback, jabber, and link integrity blocks as defined in the standard. The transceiver when combined with equalization resistors, transmit/receive filters, and pulse transformers provides a complete physical interface from the DP83907’s ENDEC module and the twisted pair medium. (continued)

1.0 System Diagram

Features

Controller and integrated bus interface solution for IEEE

802.3, 10BASE5, 10BASE2, and 10BASE-T

Software compatible with industry standard Ethernet Adapters: Novell

No external bus logic or drivers needed

Supports jumpered or jumperless configuration

Provides EEPROM interface for non-volatile storage of configuration data, user-defined data and Ethernet Physical Address

Allows in-situ programming of EEPROM

Integrated controller, ENDEC, and transceiver

Full IEEE 802.3 compliant AUI interface

Single 5V supply

10BASE-T TRANSCEIVER MODULE:

Integrates transceiver functionality

Transmitter and receiver functions

Collision detect, heartbeat and jabber

Selectable link integrity test or link disable

Polarity Detection/Correction

Auto switch

On chip filter

ENDEC MODULE:

10 Mbit/s Manchester encoding/decoding

Squelch on receive and collision pairs

MAC/CONTROLLER MODULE:

Software compatible with DP8390, DP83901, DP83902

Efficient buffer management implementation

IN-CIRCUIT TEST

’s NE2000

TL/F/12082– 1

TRI-STATEÉis a registered trademark of National Semiconductor Corporation.

AT/LANTIC Ethernet NetWare Novell

1995 National Semiconductor Corporation RRD-B30M115/Printed in U. S. A.

is a trademark of National Semiconductor Corporation.

is a registered trademark of Xerox Corporation.

is a trademark of Novell Incorporated.

is a registered trademark of Novell Incorporated.

TL/F/12082

General Description (Continued)

The integrated ENDEC module allows Manchester encoding and decoding via a differential transceiver and phase lock loop decoder at 10 Mbit/sec. Also included are a collision detect translator and diagnostic loopback capability. The ENDEC module interfaces directly to the transceiver module, and also provides a fully IEEE compliant AUI (Attachment Unit Interface) for connection to other media transceivers.

The Media Access Control function which is provided by the Network Interface Control module (NIC) provides simple and efficient packet transmission and reception control by means of off-board memory which can be accessed through an I/O port.

The DP83907 provides a comprehensive solution for 10BASE-T IEEE 802.3 networks. Due to the inherent constraints of CMOS processing, isolation is required at the AUI differential signal interface for 10BASE5 and 10BASE2 applications.

TabIe Of Contents

1.0 SYSTEM DIAGRAM

1.1 Connection Diagram

2.0 PIN DESCRIPTION

3.0 SIMPLIFIED APPLICATION DIAGRAM

4.0 FUNCTIONAL DESCRIPTION

4.1 Bus Interface Block

4.2 Power on RESET Operation

4.3 EEPROM OperatIon

4.4 Jumperless Operation Support

4.5 Ethernet Cable Configuratlon

4.6 Interrupt AND LED OperatIon

4.7 Boot PROM OperatIon

4.8 DP8390 Core (Network interface Controller)

4.9 Twisted Pair Interface Module

4.10 Encoder/Decoder (ENDEC) Module

5.0 REGISTER DESCRIPTIONS

5.1 Configuration Registers

5.2 NIC Core Registers

5.3 DP8390 Core DMA Registers

6.0 OPERATION OF DP83907

6.1 Transmit/Receive Packet Encapsulation/Decapsulation

6.2 Buffer Memory Access Control (DMA)

6.3 Packet Reception

6.4 Packet TransmissIon

6.5 Loopback DIagnostics

6.6 Memory Arbitration and Bus Operation

6.7 Functional Bus TimIng

7.0 IN-CIRCUIT TEST (ICT) DESCRIPTION

Connection Diagram

Order Number DP83907VF

See NS Package Number VF132A

TL/F/12082– 2

2.0 Pin Description

Pin No. Pin Name Type Description

ISA BUS INTERFACE PINS

119–127, SA0–SA9 I LATCHED ADDRESS BUS: Low-order 10 bits of the system’s latched 20-bit address 132 TTL

1–7 SA13–SA19 I LATCHED ADDRESS BUS: 7 bits of the system’s latched 20-bit address bus that are

10, 11 SMRD,IBOOT PROM STROBES: These inputs are used to access the BOOT PROM.

SMWR

15, 16, 18 SD0–SD7 I/O SYSTEM DATA BUS: 16-bit system data bus. Used to transfer data between the 19, 21, 22 SD8–SD15 3ST 24, 25, 98 99, 101, 102, 104, 105, 107, 108

118 IOCS16 O 16 BIT I/O TRANSFER: This signal indicates that the DP83907 is responding to a 16-

9 IOWR I I/O WRITE STROBE: Strobe from system to write to the DP83907’s I/O map.

8 IORD I I/O READ STROBE: Strobe from system to read from the DP83907’s I/O map.

30 RESET I RESET: This signal is output by the system to reset all devices on the bus.

13 CHRDY O CHANNEL READY: This signal is used to insert wait states into system accesses.

12 AEN I DMA ACTIVE: This signal indicates that the systems DMA has control of the bus.

29, 111, IRQ3, 4, 5, 9, 10, O INTERRUPT REQUEST: The operation of these outputs is determined by 112, 114, 11, 12, 15 3ST 115, 128 129, 130

Note: Driver Types are: IeInput, OeOutput, I/OeBi-directional Output, OCHeOpen Collector, 3STeTRI-STATEÉOutput, TTLeTTL Compatible,

Attachment Unit Interface, TPIeTwisted Pair Interface, LEDeLED Drive, MOSeCMOS Level Compatible, XTALeCrystal.

AUI

bus. These bits are used to decode accesses to the DP83907’s I/O map.

used to decode accesses to the DP83907’s boot PROM.

TTL

system and the DP83907.

bit I/O access by driving 16 bits of data on the bus.

OCH

TTL

OCH

TTL

Configuration Register A.

2.0 Pin Description (Continued)

Pin No. Pin Name Type Description

NETWORK INTERFACE PINS

44–47 TxOda, TXOb,OTWISTED PAIR TRANSMIT OUTPUTS: These high drive CMOS level outputs are

TXO

42, 43 RXIa, RXI

33, 34 TX

36, 37 RX

38, 39 CD

b a

55 ACT

56 COL

54 GDLNK

TXOd

led O ACTIVITY: An open-drain active low output. It is asserted for approximately 50 ms

led O COLLISION: An open-drain active low output. It is asserted for approximately 50 ms

led O GOOD LINK: An open-drain active low output. This pin operates as an output to display link

53 REQ I EQUALIZATION RESISTOR: A resistor can be connected from this pin to GND or VCCto

52 RTX I TRANSMIT LEVEL RESISTOR: A resistor can be connected from this pin to GND or VCCto

59 X1 (OSCIN) I CRYSTAL ON EXTERNAL OSCILLATOR INPUT

58 X2 (OSCOUT) O CRYSTAL FEEDBACK OUTPUT: Used in crystal connections only. Should be left

31 THIN O THIN CABLE: This output is high if DP83907 is configured for thin cable. It can be used to

Note: Driver Types are: IeInput, OeOutput, I/OeBi-directional Output, OCHeOpen Collector, 3STeTRI-STATE Output, TTLeTTL Compatible,

Attachment Unit Interface, TPIeTwisted Pair Interface, LEDeLED Drive, MOSeCMOS Level Compatible, XTALeCrystal.

AUI

resistively combined external to the chip to produce a differential output signal with

TPI

equalization to compensate for Intersymbol Interference (ISI) on the twisted pair medium.

I TWISTED PAIR RECEIVE INPUTS: These inputs feed a differential amplifier which passes

valid data to the ENDEC module.

TPI

O AUI TRANSMIT OUTPUT: Differential driver which sends the encoded data to the

transceiver.

AUI

I AUI RECEIVE INPUT: Differential receive input pair from the transceiver.

AUI

I AUI COLLISION INPUT: Differential collision pair input from the transceiver.

AUI

whenever the DP83907 transmits or receives data in either AUI or TPI modes.

LED

whenever the DP83907 detects a collision in either either AUI or TPI modes.

LED

integrity status if this function has not been disabled by the GDLNK bit in Configuratioin

LED

integrity is bad (i.e., the twisted pair link has been broken). This output is on if the DP83907 is in Twisted Pair interface (TPI) mode, link integrity

checking is enabled and the link integrity is good (i.e., the twisted pair link has not been broken) or if the link testing is disabled.

change the equalization of the TP output.

change the TP output amplitude level.

XTAL

unconnected when using an oscillator module.

XTAL

enable the DC-DC converter required by the thin Ethernet configuration.

DCDC

2.0 Pin Description (Continued)

Pin No. Pin Name Type Description

EXTERNAL MEMORY SUPPORT

87–94 MSD0–7 or I/O–I–O MEMORY SUPPORT DATA BUSÐCONFIGURATION REGISTER A INPUT: EEPROM

CA0–7 or MOS DO, DI, SK

77–82 MSD8–15 or I/O–I MEMORY SUPPORT DATA BUSÐCONFIGURATION REGISTER B INPUT: 85, 86 CB0–7 MOS MSD8 –15: When RESET is inactive these pins are used to access external memory.

60–67 MSA1–8 or O–I MEMORY SUPPORT ADDRESS BUSÐCONFIGURATION REGISTER C INPUT:

CC0–7 MOS MSA1 –8: When RESET is inactive these pins drive the memory support address bus.

68, 69 MSA9–13 or O– I MEMORY SUPPORT ADDRESS BUSÐDWID, EECONFIG AND SIGNATURE REGISTER: 71–73 DWID, MOS MSA9 –13: When RESET is inactive these pins drive the memory support address bus.

EECONFIG DWID (MSA9): When RESET is active this input specifies whether the DP83907 is interfacing and SIG 5–7

76 MSRD O MEMORY SUPPORT BUS READ: Strobes data from the external RAM into the DP83907 via

MOS

74 MSWR O MEMORY SUPPORT BUS WRITE: Strobes data from the DP83907 into the external RAM

MOS

Note: Driver Types are: IeInput, OeOutput, I/OeBi-directional Output, OCHeOpen Collector, 3STeTRI-STATE Output, TTLeTTL Compatible,

Attachment Unit Interface, TPIeTwisted Pair Interface, LEDeLED Drive, MOSeCMOS Level Compatible, XTALeCrystal.

AUI

SIGNALS:

MSD0–7: When RESET is inactive these pins are used to access external memory and boot PROM.

CA0–7: When RESET is active Configuration Register A is loaded with the data value on these pins. If the user puts an external pull-up on any of these pins then the corresponding register bit is set to a 1. If the pin is left unconnected then the register bit is 0.

DO, DI, SK: When RESET goes from an active to an inactive level DP83907 will read the contents of a serial EEPROM, using these signals, and load the contents into internal registers. These internal registers are mapped into the space taken up by the PROM in the NE2000 Architecture. After the EEPROM read operation has completed these pins will revert to MSD0–2 (D0

MSD0, DIeMSD1, SKeMSD2).

CB0–7: When RESET is active Configuration Register B is loaded with the data value on these pins. If the user puts an external pull-up on any of these pins then the corresponding register bit is set to a 1. If the pin is left unconnected then the register bit is 0.

CC0–7: When RESET is active Configuration Register C is loaded with the data value on these pins. If the user puts an external pull-up on any of these pins then the corresponding register bit is set to a 1. If the pin is left unconnected then the register bit is 0.

to an 8-bit or 16-bit ISA bus. If the user puts an external pull-up on this pin then the bus is considered to be 16-bit. If the pin is left unconnected then the bus is considered to be 8-bit.

EECONFIG(MSA10): When RESET is active this input specifies whether the DP83907 loads the configuration from an EEPROM or from the MSD0–15 and MSA1 –8 pins. If the user puts an external pull-up on this pin then configuration data is loaded from the EEPROM. If the pin is left unconnected then configuration data is loaded from the memory support bus.

SIG 5–7(MSA11 –13): When RESET is active the most significant 3 bits of the signature register are loaded with the data value on these pins. If the user puts an external pull-up on any of these pins then the corresponding register bit is set to a 1. If the pin is left unconnected then the register bit is 0.

the memory support data bus.

via the memory support data bus.

2.0 Pin Description (Continued)

Pin No. Pin Name Type Description

EXTERNAL MEMORY SUPPORT (Continued)

95 RCS O RAM CHIP SELECT: Drives the chip select of the external RAM.

97 BPCS O BOOT PROM CHIP SELECT: Selects the boot PROM on the memory support data bus.

96 EECS O EEPROM CHIP SELECT: Strobes data from the EEPROM onto the memory support

POWER SUPPLY PINS

40 AV

41 AGND ANALOG NEGATIVE (GROUND) SUPPLY PIN.

35, 48 XVCC, TPV

32, 49 XGND, TPGND PHYSICAL MEDIA NEGATIVE (GROUND) SUPPLY PINS: This pin is the ground to the

26, 109 coreV

27, 110 coreGND NEGATIVE (GROUND) SUPPLY PINS: These are the supply pins for the DP83907. It is

20, 70, 103 V

14, 17, 23, GND NEGATIVE (GROUND) SUPPLY PINS: These are the supply pins for the DP83907 28, 57, 75, 100, 106,113, 116, 131

Note: Driver Types are: IeInput, OeOutput, I/OeBi-directional Output, OCHeOpen Collector, 3STeTRI-STATE Output, TTLeTTL Compatible,

Attachment Unit Interface, TPIeTwisted Pair Interface, LEDeLED Drive, MOSeCMOS Level Compatible, XTALeCrystal.

AUI

MOS

This is for READ only.

MOS

data bus.

MOS

ANALOG 5V SUPPLY PIN: This pin supplies 5V to the DP83907’s analog circuitry. To maximize data recovery it is recommended that analog layout and decoupling rules be applied between this pin and AGND.

PHYSICAL MEDIA 5V SUPPLY PINS: This pin supplies 5V to the DP83907’s analog physical media interface circuitry.

DP83907’s analog physical media interface circuitry.

POSITIVE 5V SUPPLY PINS: These pins suppy power to the DP83907.

suggested that decoupling capacitors be connected between the V is essential to provide a path to ground for the GND pins with the lowest possible

impedance.

POSITIVE 5V SUPPLY PINS: These pins supply power to the DP83907 Output Drivers e.g., SD, MSD, MSA, Chip selects.

Drivers. It is suggested that decoupling capacitors be connected between the V GND pins. It is essential to provide a path to ground for the GND pins with the lowest possible impedance.

and GND pins. It

and

3.0 Simplified Application Diagram

TL/F/12082– 3

3.0 Simplified Application Diagram (Continued)

FIGURE 1. Block Diagram of DP83907

4.0 Functional Description

The DP83907 is a highly integrated and configurable Ethernet controller making it suitable for most Ethernet applications. The DP83907 integrates the functions of the following blocks:

1. ISA Bus Interface containing all logic required to connect the DP8390 core to a packet buffer RAM and the ISA bus.

2. DP8390 Ethernet Controller Core and Media Access Control logic.

3. Media Interface which includes a TPI transceiver.

4.1 BUS INTERFACE BLOCK

The DP83907’s Bus interface block provides the circuitry to interface the Ethernet controller logic and the external packet buffer RAM to an ISA (Industry Standard Architecture)

TL/F/12082– 4

Bus. The bus interface provides an NE2000 Architecture compatible I/O port architecture, supporting both 8-bit and 16-bit wide ISA Bus slots.

DETERMINING 8-BIT OR 16-BIT WIDE DATA

DP83907 can treat the system data bus and all internal data busses as 8 bits or 16 bits wide. 8-bit or 16-bit mode is determined by MSA9 at reset. For an adapter card this pin can be used to automatically detect if the card has been plugged into an 8-bit or 16-bit slot by connecting MSA9 via a 10 kX pull-up resistor to a V will be pulled high when plugged into a 16-bit slot, enabling 16-bit mode, and floating when plugged into an 8-bit slot. When floating the internal pull-down resistor will enable 8-bit mode.

on the upper connector. It

4.0 Functional Description (Continued)

The DP83907 register space within this area are 8 bits wide, but the data transfer port is 16 bits wide. The DP83907’s registers can be programmed to control the passing of data between its internal memory and the data transfer port. By accessing the data transfer port (using I/O instructions) the user can transfer data to or from the DP83907’s internal memory. The DP83907’s internal memory map is as shown below.

0000h

001Fh

D15 D0

00 PROM

Aliased PROM

FIGURE 2. I/O Port

The DP83907’s internal memory map is accessed one byte or word at a time, via a port within the systems I/O space. DP83907 is programmed by the user to control the transfers between its internal memory and the I/O port. The DP83907’s internal registers and the memory access port are accessed within the system’s I/O map. The address within this I/O map is, set by Configuration Register A.

16-BIT I/O PORT COMPATIBLE MODE I/O ADDRESS MAPPING

This mode is compatible with Novell’s NE2000 Architecture. The base I/O address of DP83907 is configured by Configuration Register A (either upon power up or by software writing to this register). At the base I/O address the following stwcture appears.

Basea00h

Base

0Fh

Basea10h

Base

17h Port

Basea18h

Base

1Fh

FIGURE 3. I/O Port Mode Register I/O Map

Data Transfer

Reset Port

TL/F/12082– 5

DP8390

Core

4000h

8kx16

7FFFh Buffer RAM

8000h

Aliased PROM

C000h

Aliased

Buffer RAM

FFFh

(a)

D15 D0

001Eh 00 57h

001Ch 00 57h

00 RESERVED

00Ah 00 E’net Address 5

0008h 00 E’net Address 4

0006h 00 E’net Address 3

0004h 00 E’net Address 2

0002h 00 E’net Address 1

0000h 00 E’net Address 0

(b)

FIGURE 4. a) NIC Core’s 16-Bit Memory Map

b) 16-Bit PROM Map

DP83907 has a 64k address range but only does partial decoding through this space. The PROM data is mirrored from all decodes up to 4000H and the entire map is repeated at 8000H. To access either the PROM or the RAM the user must initiate a Remote DMA transfer between the I/O port and memory.

4.0 Functional Description (Continued)

On a remote read the DP83907 moves data from its internal memory map to the I/O port and the host system reads it by using an ‘‘INW’’ or ‘‘INSW’’ instruction from the I/O address of the data transfer port. If the system attempts to read the port before DP83907 has written the next word of data to it DP83907 will insert wait states into the system cycle using the CHRDY line. DP83907 will not begin the next memory read until the previous word of data has been read.

On a remote write the system writes data to the I/O port, using an ‘‘OUTW’’ or ‘‘OUTSW’’ instruction, and DP83907 moves it to its buffer memory. If the system attempts to write to the port before DP83907 has moved the data to memory, DP83907 will insert wait states into the system cycle using the CHRDY line. DP83907 will not begin the next memory write until a new word has been written to the I/O port.

Addresses 00H to 1FH are specified as the PROM space for compatibility with the NE2000 Architecture. This is actually an array of 8-bit registers which are loaded from an external EEPROM after DP83907 is initialized by an ISA RESET. They should contain the same data as the PROM did in the NE2000 Architecture and in the same format. To transfer the data out the user must initiate a 16-bit DMA read transfer and discard the most significant byte of data on each transfer.

At address 00H of the PROM is a six byte Ethernet address for this node. The upper two addresses of the PROM store contain bytes which identify whether the DP83907 is in 8-bit or 16-bit mode. For 16-bit mode these bytes both contain the value 57H, for 8-bit mode they both contain 42H.

8-BIT I/O PORT COMPATIBLE MODE

This mode is compatible with the 8-bit mode offered by Novells NE2000 Architecture. The NE2000 automatically detects whether it is in an 8-bit or 16-bit slot and configures itself appropriately. As explained in the previous paragraphs, the user can determine whether the board is in 8-bit or 16-bit mode by reading the PROM. In 8-bit mode only 8 Kbytes of RAM are addressable, as in the 8-bit mode of the NE2000 Architecture. The I/O map is the same as the 16-bit mode, the memory map is shown in the PROM has only a partial decode, so is mirrored at all addresses up to 4000H. The PROM still occupies 32 bytes of address space, although it only has 16 bytes of data, as the data at all odd address locations is merely a mirror of the data at the previous even address location.

A low cost card, using only one 8 Kbyte RAM, can be designed. If the function on MSA9 is left unconnected, then the DP83907 will always operate in 8-bit mode, regardless of the slot the board is in.

Figure 5

. Again

0000h PROM 0020h

Aliased PROM

4000h

8k x 8 BUFFER RAM

6000h

RESERVED

7FFFh

(a)

D15 D0

1Eh 42h 42h

1Ch 42h 42h

RESERVED RESERVED

0Ah E’net Address 5 E’net Address 5

08h E’net Address 4 E’net Address 4

06h E’net Address 3 E’net Address 3

04h E’net Address 2 E’net Address 2

02h E’net Address 1 E’net Address 1

00h E’net Address 0 E’net Address 0

(b)

FIGURE 5. a) 8-Bit NIC Core’s Memory Map

4.2 POWER ON RESET OPERATION

The DP83907 configures itself after a Reset signal is applied. To be recognized as a valid Power-On-Reset the Reset signal must be active for at least 415 ms. how the RESET circuitry operates.

b) 8-Bit PROM Map

Figure 6

shows

FIGURE 6. RESET Operation

TL/F/12082– 6

4.0 Functional Description (Continued)

The ISA standard determines that within 500 ns of RESET going active all devices should enter the appropriate reset condition. The DP83907 will generate the internal signal IOinactive after RESET has been active for 400 ns, which will disable all outputs and cause RESET to be the only input monitored. The DP83907 will not respond to a RESET pulse of shorter duration than this. An internal timer continues to monitor the amount of time RESET is active. After 415 ms it is considered a valid Power-On-Reset and an internal signal called RegLoad is generated.

When a Power-On-Reset occurs the DP83907 latches in the values on the configuration pins and uses these to configure the internal registers and options. Internally these pins contain pull-down resistors, which are enabled when IOinactive goes active. If any pins are unconnected they default to a logic zero. The intemal pull-down resistor has a high resistance to allow the external pull-up resistors to be of a high value. This limits the current taken by the memory support bus. The suggested external resistor value is 10 kX. The configuration registers are loaded from the memory support bus when RESET goes inactive if RegLoad is active. The internal pull-down resistors are enabled onto the bus until RegLoad has gone inactive.

A Power-On-Reset also causes the DP83907 to load the internal PROM space from the EEPROM, which can take up to 320 ms. This occurs after RegLoad has gone inactive. The DP83907 will be inaccessible during this time. If EECONFIG is held high the configuration data loaded on the falling edge of RESET will be overwritten with data read from the serial EEPROM. Regardless of the level on EECONFIG, the PROM space will always be loaded with data from the serial EEPROM during the time specified as EELoad.

4.3 EEPROM OPERATION

The DP83907 uses an NMC93C06, or another serial EEPROM with compatible timings. The NMC93C06 is a 256bit device, arranged as 16 words by 16 bits wide. The programmed contents of the EEPROM is shown in

D15 D0

0Fh EEPROM Code Config. C

0Eh Config. B Config. A

## ## ##

08h 42h 42h

07h 57h 57h

## ## ##

03h Reserved Reserved

02h E’net Address 5 E’net Address 4

01h E’net Address 3 E’net Address 2

00h E’net Address 1 E’net Address 0

FIGURE 7. EEPROM Programming Map

Figure 7

Mapping EEPROM into PROM Space

Data is read from the EEPROM at boot time and stored in registers within the DP83907. While this operation takes place the DP83907 can not be accessed by the system. These registers are mapped into the space traditionally occupied by the PROM in the NE2000

The user should program the EEPROM to contain the Ethernet address in the first six bytes and whatever is required in the next 8 bytes. The user should then program 5757H and 4242H into address 07h and 08h respectively. The DP83907 device driver may determine that this is a 16-bit board by checking this value.

The DP83907 reads the first 8 words from the EEPROM and maps them into the memory map at the appropriate address.

In Circuit ProgrammIng the EEPROM

If the upper byte of address 0Fh in the EEPROM does not contain 073H then the DP83907 enters a mode that allows the EEPROM contents to be programmed. This can be used in production to program the EEPROM in-situ. By programming 073H into the uppermost byte the EEPROM is protected from future adaptation, except for configuration data which can always be modified.

If the EEPR bit of the Signature Register is low the EEPROM program mode may be entered. The EEPR bit is low if the EEPROM code is not programmed as 73H. In this mode, if the EELOAD bit of Configuration Register B is set the user can directly control the EEPROM signals by writing to the Data Transfer Port. The user can write to the Data Transfer Port and the value on the SD3, SD2 and SD1 pins will be driven onto the EECS, SK and DI outputs. These outputs will be latched. The user can generate a clock on SK by repetitively writing 1 then 0 to the appropriate bit. This can be used to generate the EEPROM signals, as per the NM93C06 data sheet.

When the EEPROM has been programmed the user must give the DP83907 a reset signal to return to normal operation and to read in the new data.

Storing and Loading Configuration from EEPROM

If the EECONFIG function on MSA10 is high during boot up the DP83907’s configuration is read from the EEPROM, before the PROM data is read. The configuration data is stored within the upper two words of the EEPROM’s address space. Configuration Registers A and B are located in the lower of these words, Register C in the lower byte of the upper word, as shown in

To write this configuration into the EEPROM the user must follow the routine specified in the pseudo code below. If the EEPROM code byte in the EEPROM is programmed as 73H the Configuration Registers may be written to in the EPROM. This operation will work regardless of the level on EECONFIG. The EELOAD bit of Configuration Register B being set starts the EEPROM write process. Care should be taken not to accidentally set the GDLlNK bit and therefore disable link integrity checking. The next 3 writes to this register load the values that will be stored in the configuration register (note that the last 2 of these writes do not have to follow the normal practice of preceding a write to this register with a read to this address). The DP83907 will then commence the EEPROM write. The write has been completed when the EELOAD bit goes to zero. This loading proce-

Figure 7

4.0 Functional Description (Continued)

dure should be followed exactly and interrupts should be disabled until it has completed, to prevent any accidental accesses to the DP83907.

EEPROM

LOAD()

DISABLE INTERRUPTS();

value 4 READ(CONFIG B);

value 4 value AND ! GDLINK;

value 4 value OR EELOAD;

WRITE(CONFIG B, value);

READ(CONFIG

WRITE(CONFIG B, config for A);

WRITE(CONFIG B, config for B);

WRITE(CONFIG B, config for C);

while (value AND EELOAD)

ENABLE INTERRUPTS();

4.4 JUMPERLESS OPERATION SUPPORT

One of the biggest problems in installing new adapters in a PC is not knowing the available resources within that machine. DP83907’s software configuration overcomes that problem. The conflicts possible in the I/O base selection can be overcome by a special mode for software configuration of the I/O base address. By using this mode, and by using the configuration storage capability of the EEPROM, a fully software configurable design on the ISA bus can be realized without address conflict problems.

This mode is invoked by having the DP83907 default to jumperless software configuration option in the I/O base selection. This mode enables configuration register A to be mapped to address location 278H which is defined to be a printer port’s data register. If software writes to this location four consecutive times, on the fourth write the DP83907 will load the data written into the I/O address bits of Configuration Register A. This data should set the I/O base address to a known conflict-free value. The DP83907 can now be configured and operated at the desired base I/O address. If desired, the configuration software could change the EEPROM content to the new values eliminating the need to reconfigure upon each power up. Alternately the software could leave the EEPROM alone and execute the configuration using the printer port’s data register upon each power up. This configuration scheme will only work once after each power-up. Therefore the user can not enable the DP83907 from reserved mode, change it back into reserved mode and enable it again. A power-on reset must occur between the first time it is enabled from the reserved mode and the second.

4.5 ETHERNET CABLE CONFIGURATION

DP83907 offers the choice of all the possible Ethernet cabling options, that is Ethernet (10BASE5), Thin Ethernet (10BASE2) and Twisted-pair Ethernet (10BASE-T). The

B);

value 4 READ(CONFIG B);

WAIT();

type of cabling used is controlled by Configuration Register B. DP83907 also supplies a THIN output signal which can be used to disable/enable an external DC-DC converter which is required for 10BASE2.

4.6 INTERRUPT AND LED OPERATION

The DP83907 has only one Interrupt Mode. There are 8 possible interrupts. Configuration Register A controls which of the 8 interrupt lines are driven, the others are TRI-STATE.

The interrupt outputs should be connected to the following ISA Interrupt lines, In the order given, to maintain NE2000 Architecture compatibility: 3, 4, 5, 9, 10, 11, 12, 15.

4.7 BOOT PROM OPERATION

The DP83907 supports an optional boot PROM, the address and size of which can be set in Configuration Register C. This boot PROM can be any 8-bit wide storage device implemented with a non-volatile technology. Write cycles to this device can be enabled and disabled by programming Configuration Register B. This can be used to prevent unwanted write cycles to certain devices, such as a Flash EEPROM. The DP83907 supplies the chip select to the device and buffers the data on to and from the ISA bus, so the memory support data bus should be connected to the boot PROM’s data pins.

4.8 DP8390 CORE (NETWORK INTERFACE CONTROLLER)

The DP8390 Core logic, Deserializer which is controlled by the Protocol PLA, DMA Control, FIFO, Address Comparator and Multicast Hashing Register. The DP8390 core implements all of the IEEE

802.3 Media access control functions for the DP83907 and interfaces to the internal ENDEC (on the left of the block diagram) and to the Bus Interface and memory support bus via a number of address, data and control signals (the right side of the block diagram). The following sections describe the functions of the DP8390 core.

Receive Deseriallzer

The Receive Deserializer is activated when the input signal Carrier Sense is asserted to allow incoming bits to be shifted into the shift register by the receive clock. The serial receive data is also routed to the CRC generator/checker. The Receive Deserializer includes a synch detector which detects the SFD (Start of Frame Delimiter) to establish where byte boundaries within the serial bit stream are located. After every eight receive clocks, the byte wide data is transferred to the 16-byte FIFO and the Receive Byte Count is incremented. The first six bytes after the SFD are checked for valid comparison by the Address Recognition Logic. If the Address Recognition Logic does not recognize the packet, the FlFO is cleared.

CRC Generator/Checker

During transmission, the CRC logic generates a local CRC field for the transmitted bit sequence. The CRC encodes all fields after the SFD. The CRC is shifted out MSB first follow-

Figure 12

, contains the Serializer/

4.0 Functional Description (Continued)

FIGURE 12. DP8390 Core Simplified Block Diagram

ing the last transmit byte. During reception the CRC logic generates a CRC field from the incoming packet. This local CRC is serially compared to the incoming CRC appended to the end of the packet by the transmitting node. If the local and received CRC match, a specific pattern will be generated and decoded to indicate no data errors. Transmission errors result in different pattern and are detected, resulting in rejection of a packet.

Transmit Serializer

The Transmit Serializer reads parallel data from the FIFO and serializes it for transmission. The serializer is clocked by the transmit clock generated internally. The serial data is also shifted into the CRC generator/checker. At the beginning of each transmission, the Preamble and SFD Generator append 62 bits of 1,0 preamble and a 1,1 synch pattern. After the last data byte of the packet has been serialized the 32-bit FCS (Frame Check Sequence) field is shifted directly out of the CRC generator. In the event of a collision the Preamble and SFD generator is used to generate a 32-bit JAM pattern of all 1’s.

Comparator-Address Recognition Logic

The address recognition logic compares the Destination Address Field (first 6 bytes of the received packet) to the Physical address registers stored in the Address Register Array.

TL/F/12082– 7

If any one of the six bytes does not match the pre-programmed physical address, the Protocol Control Logic rejects the packet. All multicast destination addresses are filtered using a hashing technique. (See register description.) If the multicast address indexes a bit that has been set in the filter bit array of the Multicast Address Register Array the packet is accepted, otherwise it is rejected by the Protocol Control Logic. Each destination address is also checked for all 1’s which is the reserved broadcast address.

FIFO and Packet Data Operations

OVERVIEW

To accommodate the different rates at which data comes from (or goes to) the network and goes to (or comes from) the packet buffer memory, the DP83907 contains a 16-byte FIFO for buffering data between the media and the buffer RAM located on the memory support bus. The FIFO threshold is programmable. When the FIFO has filled to its programmed threshold, the local DMA channel transfers these bytes (or words) into local memory (via the memory bus). It is crucial that the local DMA is given access to the bus within a minimum bus latency time; otherwise a FIFO underrun (or overrun) occurs.

4.0 Functional Description (Continued)

FIFO underruns or overruns are caused when a local DMA request is issued while an ISA bus access is current and the ISA cycle takes longer to complete than the local DMA’s tolerable latency. This tolerable latency depends on the FIFO threshold, whether it is in byte or word wide mode and the speed of the DMA clock (BSCLK frequency). Note that this refers to standard ISA cycles, NOT those where the CHRDY is deasserted extending the cycle.

FIFO THRESHOLD DETECTION

To assure that no overwriting of data in the FIFO, the FIFO logic flags a FIFO overrun as the 13th byte is written into the FIFO, effectively shortening the FIFO to 13 bytes. The FIFO logic also operates differently in Byte Mode and in Word Mode. In Byte Mode, a threshold is indicated when the n byte has entered the FIFO; thus, with an 8 byte threshold, the DP83907 issues a request to the buffer RAM when the 9th byte has entered the FIFO, making the effective threshold 9 bytes. For Word Mode, the request is not generated until the n

2 bytes have entered the FIFO. Thus, with a 4 word threshold (equivalent to 8 byte threshold), a request to the buffer RAM is issued when the 10th byte has entered the FIFO, making the effective threshold 10 bytes.

TOLERABLE LATENCY CALCULATION

To prevent a FIFO overrun a byte (or word) of data must be removed from the FIFO before the 13th byte is written.

Therefore the worst case tolerable latency is the time from the effective threshold being reached to the time the 13th byte is written minus the time taken to load the first byte (or word) of data to the FIFO during a local DMA burst (8 BSCLKs).

tolerable latency

((overrunbeffective) threshold

time to transfer byte on network)

time to fill 1st FIFO location

For the case of a 4 word threshold using a 20 MHz BSCLK:

tolerable latency

((13b10)c800)b(8c50) ns

2 ms

To prevent a FIFO underrun a byte (or word) of data must be added to the FIFO before the last byte is removed. Therefore the worst case tolerable latency is the time from the effective threshold being reached to the time the last byte is removed minus the time taken to load the first byte (or word) of data to the FIFO during a local DMA burst (8 BSCLKs).

tolerable latency

(threshold

time to transfer byte on network)

time to fill 1st FIFO location

For the case of a 4 word threshold using a 20 MHz BSCLK:

tolerable latency

(4c800)b(8c50) ns

2.8 ms

The worst case latency, either overrun or underrun, ultimately limits the overall latency that the DP83907 can tolerate. If the standard ISA cycles are shorter than the worst case latency, then no FIFO overruns or underruns will occur.

BEGINNING OF RECEIVE

At the beginning or reception, the DP83907 stores the entire Address field of each incoming packet in the FIFO to deter-

mine whether the packet matches its Physical Address Registers or maps to one of its Multicast Registers. This causes the FIFO to accumulate 8 bytes. Furthermore, there are some synchronization delays in the DMA PLA. Thus, the actual time that a request to access the buffer RAM is asserted from the time the Start of Frame Delimiter (SFD) is detected is 7.8 ms. This operation affects the bus latencies at 2 and 4 byte thresholds during the first receive request since the FIFO must be filled to 8 bytes (or 4 words) before issuing a request to the buffer RAM.

END OF RECEIVE

When the end of a packet is detected by the ENDEC module, the DP83907 enters its end of packet processing sequence, emptying its FIFO and writing the status information

at the beginning of the 1st buffer. The DP83907 holds onto the memory bus for the entire sequence. The longest time that local DMA will hold the buffer RAM occurs when a packet ends just as the DP83907 performs its last FIFO burst. The DP83907, in this case, performs a programmed burst transfer followed by flushing the remaining bytes in the FIFO, and completed by writing the header information to the buffer memory. The following steps occur during this sequence.

1. DP83907 issues request to access the RAM because the FIFO threshold has been reached.

2. During the burst, the packet ends, resulting in the request being extended.

3. DP83907 flushes remaining bytes from FIFO.

4. DP83907 performs internal processing to prepare for writing the header.

5. DP83907 writes 4-byte (2-word) header

6. DP83907 de-asserts access to the buffer RAM.

BEGINNING OF TRANSMIT

Before transmitting, the DP83907 performs a prefetch from memory to load the FIFO. The number of bytes prefetched is the programmed FIFO threshold. The next request to the buffer RAM is not issued until after the DP83907 actually begins transmitting data, i.e., after SFD.

READING THE FIFO

If the FIFO is read during normal operation the DP83907 will ‘‘hang’’ the ISA bus by deasserting CHRDY and never asserting it. The FIFO should only be read during loopback diagnostics.

PROTOCOL PLA

The protocol PLA is responsible for implementing the IEEE

802.3 protocol, including collision recovery with random

backoff. The Protocol PLA also formats packets during transmission and strips preamble and synch during reception.

DMA AND BUFFER CONTROL LOGIC

The DMA and Buffer Control Logic is used to control two 16-bit DMA channels. During reception, the Local DMA stores packets in a receive buffer ring, located in buffer memory. During transmission the Local DMA uses programmed pointer and length registers to transfer a packet from local buffer memory to the FIFO.

4.0 Functional Description (Continued)

FIGURE 13. Twisted Pair Interface Module Block Diagram

A second DMA channel (Remote DMA) is used as a slave DMA to transfer data between the local buffer memory and the host system. The Local DMA and Remote DMA are internally arbitrated, with the Local DMA channel having highest priority. Both DMA channels use a common external bus clock to generate all required bus timing. External arbitration is performed with a standard bus request, bus acknowledge handshake protocol.

4.9 TWISTED PAIR INTERFACE MODULE

The TPI consists of five main logical functions:

a) The Receiver/Smart Squelch, responsible for determin-

ing when valid data is present on the differential receive inputs (RXI

) and receiving the data.

b) The Collision function checks for simultaneous transmis-

sion and reception of data on the TXO

c) The Link Detector/Generator checks the integrity of the

cable connecting the two twisted pair MAUs.

d) The Jabber disables the transmitter if it attempts to

transmit a longer than legal packet.

e) The TX Driver and Pre-emphasis transmits Manchester

encoded data to the twisted pair network via the summing resistors and transformer/filter.

and RXIgpins.

TL/F/12082– 8

4.0 Functional Description (Continued)

Receiver and Smart Squelch

The DP83907 implements an intelligent receive squelch on

the RXI the receive inputs will not be mistaken for a valid signal.

The squelch circuitry employs a combination of amplitude and timing measurements to determine the validity of data on the twisted pair inputs. There are two voltage level options for the smart squelch. One mode, 10BASE-T mode, uses levels that meet the 10BASE-T specification. The second mode, reduced squelch mode, uses a lower squelch threshold level, and can be used in longer cable applications where due to attenuation smaller signal levels may be present. The squelch level mode can be selected in the DP83907 configuration registers.

Figure 14

10BASE-T mode.

The signal at the start of packet is checked by the smart squelch and any pulses not exceeding the squelch level (either positive or negative, depending upon polarity) will be rejected. Once this first squelch level is overcome correctly the opposite squelch level must then be exceeded within 150 ns later. Finally the signal must exceed the original squelch level within a further 150 ns to ensure that the input waveform will not be rejected. The checking procedure results in the loss of typically three bits at the beginning of each packet.

Only after all these conditions have been satisfied will a control signal be generated to indicate to the remainder of the circuitry that valid data is present. At this time the smart squelch circuitry is reset.

In the reduced squelch mode the operation is identical except that the lower squelch levels shown in the figure are used.

Valid data is considered to be present until either squelch level has not been generated for a time longer than 150 ns, indicating End of Packet. Once good data has been detected the squelch levels are reduced to minimize the effect of noise causing premature End of Packet detection.

differential inputs to ensure that impulse noise on

shows the operation of the smart squelch in

Collision

A collision is detected by the TPI module when the receive and transmit channels are active simultaneously. If the TPI is receiving when a collision is detected it is reported to the controller immediately. If, however, the TPI is transmitting when a collision is detected the collision is not reported until seven bits have been received while in the collision state. This prevents a collision being reported incorrectly due to noise on the network. The signal to the controller remains for the duration of the collision.

Approximately 1 m sec after the transmission of each packet a signal called the Signal Quality Error (SQE) consisting of typically 10 cycles of 10 MHz is generated. This 10 MHz signal, also called the Heartbeat, ensures the continued functioning of the collision circuitry.

Link Detector/Generator

The link generator is a timer circuit that generates a link pulse as defined by the 10 Base-T specification that will be generated by the transmitter section. The pulse which is 100 ns wide is transmitted on the TXO the absence of transmit data.

The pulse is used to check the integrity of the connection to the remote MAU. The link detection circuit checks for valid pulses from the remote MAU and if valid link pulses are not received the link detector will disable the transmit, receive and collision detection functions.

The GDLNK output can directly drive a LED to show that there is a good twisted pair link. For normal conditions the LED will be on. The link integrity function can be disabled by setting the GDLNK bit of Configuration Register B.

Jabber

The jabber timer monitors the transmitter and disables the transmission if the transmitter is active for greater than 26 ms. The transmitter is then disabled for the whole time that the Endec module’s internal transmit enable is asserted. This signal has to be deasserted for approximately 750 ms (the unjab time) before the Jabber re-enables the transmit outputs.

output, every 16 ms, in

FIGURE 14. Twisted Pair Squelch Waveform

TL/F/12082– 9

4.0 Functional Description (Continued)

Transmitter

The transmitter consists of four signals, the true and compliment Manchester encoded data (TXO delayed by 50 ns (TXOd

These four signals are resistively combined TXOawith

TXOd

and TXObwith TXOda. This is known as digital

pre-emphasis and is required to compensate for the twisted pair cable which acts like a low pass filter causing greater attenuation to the 10 MHz (50 ns) pulses of the Manchester encoded waveform than the 5 MHz (100 ns) pulses.

An example of how these signals are combined is shown in the following diagram.

) and these signals

FIGURE 15. Typical Summed Transmit Waveform

The signal with pre-emphasis shown above is generated by resistively combining TXOaand TXOdb. This signal along with its compliment is passed to the transmit filter.

TL/F/12082– 11

FIGURE 16a. Circuitry to Connect DP83907 to Twisted Pair Cable with External Filter

TL/F/12082– 10

4.0 Functional Description (Continued)

FIGURE 16b. Circuitry to Connect DP83907 to Twisted Pair Cable with Internal Filter

On-Chip Filters

The on-chip filters are enabled via an external pull-up resistors on MSD

k12l

at configuration. Only an isolation transformer and impedance matching resistors are needed for the transmit and receive twisted pair interface.

UTP/STP Function

The TPI transceiver supports both shielded and unshielded twisted pair cable. UTP is default but STP can be enabled during configuration by a pull-up on MSA bit D6 of configuration register C. In UTP mode TXO

TXOD

are driven and TXOband TXODbare TRI-STAT-

ED. In STP mode, TXO

TXO

and TXODaare TRI-STATED.

and TXODbare driven and

k7l

or by setting

and

Auto-Switch Function

When an auto-switch function is enabled at configuration by a pull-up on MSA

k5l

or by setting bit D4 of the configuration register C, it allows the transceiver to switch between TP and AUI outputs. If there is an absence of link pulses, the transceiver will switch to AUI mode. Similarly, when the transceiver starts detecting link pulses it will switch to TP mode. The switching from one mode to the next is only done after the current package has been transmitted or received. If the twisted pair output is jabbering and gets into link fail state, then the switch to AUI mode is only done after the jabbering is done, including the time it takes to unjab (unjab time). When auto-switching is enabled the THIN output is automatically generated if AUI is selected.

TL/F/12082– 52

TL/F/12082– 12

FIGURE 17. Typical DP83907 LED Connection

Status Information

Status information is provided by the DP83907 on the ACTÐled, COLÐled and GDLNKÐled outputs as described in the pin description table. These outputs are suitable for driving status LED’s as shown in

Figure 17

. All out-

puts are open drain.

Recommended Transformers for Internal Filter mode:

1) Valor PT4160

2) Pulse PE-68029

3) PCA EPE6087A

4) Delta THX16B02

5) Belfus A553-3899-06

6) Kappa TP3036

4.0 Functional Description (Continued)

FIGURE 18. Encoder/Decode Block Diagram

4.10 ENCODER/DECODER (ENDEC) MODULE

The ENDEC consists of four main logical blocks:

a) The oscillator generates the 10 MHz transmit clock sig-

nal for system timing.

b) The Manchester encoder accepts NRZ data from the

controller, encodes the data to Manchester, and transmits the data differentially to the transceiver, through the differential transmit driver.

c) The Manchester decoder receives Manchester data from

the transceiver, converts it to NRZ data and clock pulses, and sends it to the controller.

d) The collision translator indicates to the controller the

presence of a valid 10 MHz collision signal to the PLL.

Oscillator

The oscillator is controlled by a 20 MHz parallel resonant crystal connected between X1 and X2 or by an external clock on X1. The 20 MHz output of the oscillator is divided by 2 to generate the 10 MHz transmit clock for the controller. The oscillator also provides internal clock signals to the encoding and decoding circuits.

CRYSTAL OPERATION

If the crystal used with the internal oscillator circuit is not properly selected, the DP83907 oscillator may not reliably start oscillation under all conditions.

If this occurs, it could be deceiving to a designer, since his prototypes may work fine. However, when the designer does qualification testing or starts production, he may en-

TL/F/12082– 13

counter a higher than expected board yield loss due to the oscillator not starting. The DP83907’s oscillator circuit clocks the Encoder-Decoder logic. The DP83907’s oscillator also clocks the twisted pair interface block. If the oscillator does not start, the DP83907 will not be able to transmit or receive.

TL/F/12082– 14

FIGURE 19. Crystal Connection to DP83907

(see text for component values)

4.0 Functional Description (Continued)

If a crystal is connected to the DP83907, it is recommended that the circuit shown in components used meet the following:

Crystal XT1: AT cut parallel resonant crystal

Series Resistance:

Specified Load Capacitance:s20 pF

Accuracy: 0.005% (50 ppm)

Typical Load: 50 mW–75 mW

The recommended values for capacitors C1 and C2 should be 26 pF minus the board capacitance on that pin. Therefore if both X1 and X2 have 4 pF of board capacitance then a 22 pF capacitor should be used.

According to the IEEE 802.3 standard, the entire oscillator circuit (crystal and amplifier) must be accurate to 0.01%. When using a crystal, the X2 pin is not guaranteed to provide a TTL compatible logic output, and should not be used to drive external standard logic. If additional logic needs to be driven, then an external oscillator should be used, as described in the following section.

Oscillator Module Operation

If the designer wishes to use a crystal clock oscillator, one that provides the following should be employed:

1) TTL or CMOS output with a 0.01% frequency tolerance

2) 40 – 60% duty cycle

The circuit is shown in lator it is recommended that the designer connect the oscillator output to the X1 pin and leave the X2 pin floating.

Figure 19

Figure 20

be used and that the

25X

. When using a clock oscil-

FIGURE 20. DP83907 Connection for Oscillator Module

TL/F/12082– 15

Manchester Encoder and DIfferential Driver

The differential transmit pair, on the secondary of the employed transformer, drives up to 50 meters of twisted pair AUI cable.

The DP83907 allows full-step to be compatible with IEEE

802.3. Transmit

and Transmitbare equal in the idle state, providing zero differential voltage to operate with transformer coupled loads.

FIGURE 21. Connection from DP83907’s AUI Port to a AUI Connector

TL/F/12082– 16

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